// SPDX-License-Identifier: MIT /* * Copyright © 2014 Intel Corporation #include "gem/i915_gem_lmem.h" #include "gen8_engine_cs.h" #include "i915_drv.h" #include "i915_perf.h" #include "i915_reg.h" #include "intel_context.h" #include "intel_engine.h" #include "intel_engine_regs.h" #include "intel_gpu_commands.h" #include "intel_gt.h" #include "intel_gt_regs.h" #include "intel_lrc.h" #include "intel_lrc_reg.h" #include "intel_ring.h" #include "shmem_utils.h" /* * The per - platform tables are u8 - encoded in @ data . Decode @ data and set the * addresses ' offset and commands in @ regs . The following encoding is used * for each byte . There are 2 steps : decoding commands and decoding addresses . * * Commands : * [ 7 ] : create NOPs - number of NOPs are set in lower bits * [ 6 ] : When creating MI_LOAD_REGISTER_IMM command , allow to set * MI_LRI_FORCE_POSTED * [ 5 : 0 ] : Number of NOPs or registers to set values to in case of * MI_LOAD_REGISTER_IMM * * Addresses : these are decoded after a MI_LOAD_REGISTER_IMM command by " count " * number of registers . They are set by using the REG / REG16 macros : the former * is used for offsets smaller than 0 x200 while the latter is for values bigger * than that . Those macros already set all the bits documented below correctly : * * [ 7 ] : When a register offset needs more than 6 bits , use additional bytes , to * follow , for the lower bits * [ 6 : 0 ] : Register offset , without considering the engine base . * * This function only tweaks the commands and register offsets . Values are not * filled out . static void set_offsets(u32 *regs,const u8 *data,const struct intel_engine_cs *engine,bool close)#define NOP(x) (BIT(7 ) | (x))#define LRI(count, flags) ((flags) << 6 | (count) | BUILD_BUG_ON_ZERO(count >= BIT(6 )))#define POSTED BIT(0 )#define REG(x) (((x) >> 2 ) | BUILD_BUG_ON_ZERO(x >= 0 x200))#define REG16(x) \9 ) | BIT(7 ) | BUILD_BUG_ON_ZERO(x >= 0 x10000)), \2 ) & 0 x7f)#define END 0 const u32 base = engine->mmio_base;while (*data) {if (*data & BIT(7 )) { /* skip */ 7 );continue ;0 x3f;6 ;if (flags & POSTED)if (GRAPHICS_VER(engine->i915) >= 11 )do {0 ;do {7 ;7 );while (v & BIT(7 ));0 ] = base + (offset << 2 );2 ;while (--count);if (close) {/* Close the batch; used mainly by live_lrc_layout() */ if (GRAPHICS_VER(engine->i915) >= 11 )0 );static const u8 gen8_xcs_offsets[] = {1 ),11 , 0 ),0 x244),0 x034),0 x030),0 x038),0 x03c),0 x168),0 x140),0 x110),0 x11c),0 x114),0 x118),9 ),9 , 0 ),0 x3a8),0 x28c),0 x288),0 x284),0 x280),0 x27c),0 x278),0 x274),0 x270),13 ),2 , 0 ),0 x200),0 x028),static const u8 gen9_xcs_offsets[] = {1 ),14 , POSTED),0 x244),0 x034),0 x030),0 x038),0 x03c),0 x168),0 x140),0 x110),0 x11c),0 x114),0 x118),0 x1c0),0 x1c4),0 x1c8),3 ),9 , POSTED),0 x3a8),0 x28c),0 x288),0 x284),0 x280),0 x27c),0 x278),0 x274),0 x270),13 ),1 , POSTED),0 x200),13 ),44 , POSTED),0 x028),0 x09c),0 x0c0),0 x178),0 x17c),0 x358),0 x170),0 x150),0 x154),0 x158),0 x41c),0 x600),0 x604),0 x608),0 x60c),0 x610),0 x614),0 x618),0 x61c),0 x620),0 x624),0 x628),0 x62c),0 x630),0 x634),0 x638),0 x63c),0 x640),0 x644),0 x648),0 x64c),0 x650),0 x654),0 x658),0 x65c),0 x660),0 x664),0 x668),0 x66c),0 x670),0 x674),0 x678),0 x67c),0 x068),static const u8 gen12_xcs_offsets[] = {1 ),13 , POSTED),0 x244),0 x034),0 x030),0 x038),0 x03c),0 x168),0 x140),0 x110),0 x1c0),0 x1c4),0 x1c8),0 x180),0 x2b4),5 ),9 , POSTED),0 x3a8),0 x28c),0 x288),0 x284),0 x280),0 x27c),0 x278),0 x274),0 x270),static const u8 dg2_xcs_offsets[] = {1 ),15 , POSTED),0 x244),0 x034),0 x030),0 x038),0 x03c),0 x168),0 x140),0 x110),0 x1c0),0 x1c4),0 x1c8),0 x180),0 x2b4),0 x120),0 x124),1 ),9 , POSTED),0 x3a8),0 x28c),0 x288),0 x284),0 x280),0 x27c),0 x278),0 x274),0 x270),static const u8 gen8_rcs_offsets[] = {1 ),14 , POSTED),0 x244),0 x034),0 x030),0 x038),0 x03c),0 x168),0 x140),0 x110),0 x11c),0 x114),0 x118),0 x1c0),0 x1c4),0 x1c8),3 ),9 , POSTED),0 x3a8),0 x28c),0 x288),0 x284),0 x280),0 x27c),0 x278),0 x274),0 x270),13 ),1 , 0 ),0 x0c8),static const u8 gen9_rcs_offsets[] = {1 ),14 , POSTED),0 x244),0 x34),0 x30),0 x38),0 x3c),0 x168),0 x140),0 x110),0 x11c),0 x114),0 x118),0 x1c0),0 x1c4),0 x1c8),3 ),9 , POSTED),0 x3a8),0 x28c),0 x288),0 x284),0 x280),0 x27c),0 x278),0 x274),0 x270),13 ),1 , 0 ),0 xc8),13 ),44 , POSTED),0 x28),0 x9c),0 xc0),0 x178),0 x17c),0 x358),0 x170),0 x150),0 x154),0 x158),0 x41c),0 x600),0 x604),0 x608),0 x60c),0 x610),0 x614),0 x618),0 x61c),0 x620),0 x624),0 x628),0 x62c),0 x630),0 x634),0 x638),0 x63c),0 x640),0 x644),0 x648),0 x64c),0 x650),0 x654),0 x658),0 x65c),0 x660),0 x664),0 x668),0 x66c),0 x670),0 x674),0 x678),0 x67c),0 x68),static const u8 gen11_rcs_offsets[] = {1 ),15 , POSTED),0 x244),0 x034),0 x030),0 x038),0 x03c),0 x168),0 x140),0 x110),0 x11c),0 x114),0 x118),0 x1c0),0 x1c4),0 x1c8),0 x180),1 ),9 , POSTED),0 x3a8),0 x28c),0 x288),0 x284),0 x280),0 x27c),0 x278),0 x274),0 x270),1 , POSTED),0 x1b0),10 ),1 , 0 ),0 x0c8),static const u8 gen12_rcs_offsets[] = {1 ),13 , POSTED),0 x244),0 x034),0 x030),0 x038),0 x03c),0 x168),0 x140),0 x110),0 x1c0),0 x1c4),0 x1c8),0 x180),0 x2b4),5 ),9 , POSTED),0 x3a8),0 x28c),0 x288),0 x284),0 x280),0 x27c),0 x278),0 x274),0 x270),3 , POSTED),0 x1b0),0 x5a8),0 x5ac),6 ),1 , 0 ),0 x0c8),3 + 9 + 1 ),51 , POSTED),0 x588),0 x588),0 x588),0 x588),0 x588),0 x588),0 x028),0 x09c),0 x0c0),0 x178),0 x17c),0 x358),0 x170),0 x150),0 x154),0 x158),0 x41c),0 x600),0 x604),0 x608),0 x60c),0 x610),0 x614),0 x618),0 x61c),0 x620),0 x624),0 x628),0 x62c),0 x630),0 x634),0 x638),0 x63c),0 x640),0 x644),0 x648),0 x64c),0 x650),0 x654),0 x658),0 x65c),0 x660),0 x664),0 x668),0 x66c),0 x670),0 x674),0 x678),0 x67c),0 x068),0 x084),1 ),static const u8 dg2_rcs_offsets[] = {1 ),15 , POSTED),0 x244),0 x034),0 x030),0 x038),0 x03c),0 x168),0 x140),0 x110),0 x1c0),0 x1c4),0 x1c8),0 x180),0 x2b4),0 x120),0 x124),1 ),9 , POSTED),0 x3a8),0 x28c),0 x288),0 x284),0 x280),0 x27c),0 x278),0 x274),0 x270),3 , POSTED),0 x1b0),0 x5a8),0 x5ac),6 ),1 , 0 ),0 x0c8),static const u8 mtl_rcs_offsets[] = {1 ),15 , POSTED),0 x244),0 x034),0 x030),0 x038),0 x03c),0 x168),0 x140),0 x110),0 x1c0),0 x1c4),0 x1c8),0 x180),0 x2b4),0 x120),0 x124),1 ),9 , POSTED),0 x3a8),0 x28c),0 x288),0 x284),0 x280),0 x27c),0 x278),0 x274),0 x270),2 ),2 , POSTED),0 x5a8),0 x5ac),6 ),1 , 0 ),0 x0c8),#undef END#undef REG16#undef REG#undef LRI#undef NOPstatic const u8 *reg_offsets(const struct intel_engine_cs *engine)/* * The gen12 + lists only have the registers we program in the basic * default state . We rely on the context image using relative * addressing to automatic fixup the register state between the * physical engines for virtual engine . 12 &&if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12 , 70 ))return mtl_rcs_offsets;else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12 , 55 ))return dg2_rcs_offsets;else if (GRAPHICS_VER(engine->i915) >= 12 )return gen12_rcs_offsets;else if (GRAPHICS_VER(engine->i915) >= 11 )return gen11_rcs_offsets;else if (GRAPHICS_VER(engine->i915) >= 9 )return gen9_rcs_offsets;else return gen8_rcs_offsets;else {if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12 , 55 ))return dg2_xcs_offsets;else if (GRAPHICS_VER(engine->i915) >= 12 )return gen12_xcs_offsets;else if (GRAPHICS_VER(engine->i915) >= 9 )return gen9_xcs_offsets;else return gen8_xcs_offsets;static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12 , 55 ))return 0 x70;else if (GRAPHICS_VER(engine->i915) >= 12 )return 0 x60;else if (GRAPHICS_VER(engine->i915) >= 9 )return 0 x54;else if (engine->class == RENDER_CLASS)return 0 x58;else return -1 ;static int lrc_ring_bb_offset(const struct intel_engine_cs *engine)if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12 , 55 ))return 0 x80;else if (GRAPHICS_VER(engine->i915) >= 12 )return 0 x70;else if (GRAPHICS_VER(engine->i915) >= 9 )return 0 x64;else if (GRAPHICS_VER(engine->i915) >= 8 &&class == RENDER_CLASS)return 0 xc4;else return -1 ;static int lrc_ring_gpr0(const struct intel_engine_cs *engine)if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12 , 55 ))return 0 x84;else if (GRAPHICS_VER(engine->i915) >= 12 )return 0 x74;else if (GRAPHICS_VER(engine->i915) >= 9 )return 0 x68;else if (engine->class == RENDER_CLASS)return 0 xd8;else return -1 ;static int lrc_ring_wa_bb_per_ctx(const struct intel_engine_cs *engine)if (GRAPHICS_VER(engine->i915) >= 12 )return 0 x12;else if (GRAPHICS_VER(engine->i915) >= 9 || engine->class == RENDER_CLASS)return 0 x18;else return -1 ;static int lrc_ring_indirect_ptr(const struct intel_engine_cs *engine)int x;if (x < 0 )return x;return x + 2 ;static int lrc_ring_indirect_offset(const struct intel_engine_cs *engine)int x;if (x < 0 )return x;return x + 2 ;static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12 , 55 ))/* * Note that the CSFE context has a dummy slot for CMD_BUF_CCTL * simply to match the RCS context image layout . return 0 xc6;else if (engine->class != RENDER_CLASS)return -1 ;else if (GRAPHICS_VER(engine->i915) >= 12 )return 0 xb6;else if (GRAPHICS_VER(engine->i915) >= 11 )return 0 xaa;else return -1 ;static u32const struct intel_engine_cs *engine)if (GRAPHICS_VER(engine->i915) >= 12 )return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;else if (GRAPHICS_VER(engine->i915) >= 11 )return GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;else if (GRAPHICS_VER(engine->i915) >= 9 )return GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;else if (GRAPHICS_VER(engine->i915) >= 8 )return GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;8 );return 0 ;static void const struct intel_engine_cs *engine,1 );1 ] =static void const struct intel_engine_cs *engine,1 );1 ] =1 );1 ] =6 ;static bool ctx_needs_runalone(const struct intel_context *ce)struct i915_gem_context *gem_ctx;bool ctx_is_protected = false ;/* * Wa_14019159160 - Case 2 . * On some platforms , protected contexts require setting * the LRC run - alone bit or else the encryption / decryption will not happen . * NOTE : Case 2 only applies to PXP use - case of said workaround . if (GRAPHICS_VER_FULL(ce->engine->i915) >= IP_VER(12 , 70 ) &&class == COMPUTE_CLASS || ce->engine->class == RENDER_CLASS)) {if (gem_ctx)return ctx_is_protected;static void init_common_regs(u32 * const regs,const struct intel_context *ce,const struct intel_engine_cs *engine,bool inhibit)int loc;if (inhibit)if (GRAPHICS_VER(engine->i915) < 11 )/* Wa_14019159160 - Case 2.*/ if (ctx_needs_runalone(ce))if (loc != -1 )1 ] = 0 ;static void init_wa_bb_regs(u32 * const regs,const struct intel_engine_cs *engine)const struct i915_ctx_workarounds * const wa_ctx = &engine->wa_ctx;if (wa_ctx->per_ctx.size) {const u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);1 );1 ] =0 x01;if (wa_ctx->indirect_ctx.size) {static void init_ppgtt_regs(u32 *regs, const struct i915_ppgtt *ppgtt)if (i915_vm_is_4lvl(&ppgtt->vm)) {/* 64b PPGTT (48bit canonical) * PDP0_DESCRIPTOR contains the base address to PML4 and * other PDP Descriptors are ignored . else {3 );2 );1 );0 );static struct i915_ppgtt *vm_alias(struct i915_address_space *vm)if (i915_is_ggtt(vm))return i915_vm_to_ggtt(vm)->alias;else return i915_vm_to_ppgtt(vm);static void __reset_stop_ring(u32 *regs, const struct intel_engine_cs *engine)int x;if (x != -1 ) {1 ] &= ~STOP_RING;1 ] |= STOP_RING << 16 ;static void __lrc_init_regs(u32 *regs,const struct intel_context *ce,const struct intel_engine_cs *engine,bool inhibit)/* * A context is actually a big batch buffer with several * MI_LOAD_REGISTER_IMM commands followed by ( reg , value ) pairs . The * values we are setting here are only for the first context restore : * on a subsequent save , the GPU will recreate this batchbuffer with new * values ( including all the missing MI_LOAD_REGISTER_IMM commands that * we are not initializing here ) . * * Must keep consistent with virtual_update_register_offsets ( ) . if (inhibit)0 , PAGE_SIZE);void lrc_init_regs(const struct intel_context *ce,const struct intel_engine_cs *engine,bool inhibit)void lrc_reset_regs(const struct intel_context *ce,const struct intel_engine_cs *engine)static void void *vaddr, const struct intel_engine_cs *engine)if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))return ;static void const void *vaddr, const struct intel_engine_cs *engine)if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))return ;if (memchr_inv(vaddr, CONTEXT_REDZONE, I915_GTT_PAGE_SIZE))"%s context redzone overwritten!\n" ,static u32 context_wa_bb_offset(const struct intel_context *ce)return PAGE_SIZE * ce->wa_bb_page;/* * per_ctx below determines which WABB section is used . * When true , the function returns the location of the * PER_CTX_BB . When false , the function returns the * location of the INDIRECT_CTX . static u32 *context_wabb(const struct intel_context *ce, bool per_ctx)void *ptr;/* back to start of context image */ 0 ;return ptr;void lrc_init_state(struct intel_context *ce,struct intel_engine_cs *engine,void *state)bool inhibit = true ;if (ce->default_state) {0 , state, engine->context_size);false ;/* Clear the ppHWSP (inc. per-context counters) */ 0 , PAGE_SIZE);/* Clear the indirect wa and storage */ if (ce->wa_bb_page)0 , PAGE_SIZE);/* * The second page of the context object contains some registers which * must be set up prior to the first execution . const struct intel_context *ce)return i915_ggtt_offset(ce->state) + context_wa_bb_offset(ce);static u32 *setup_predicate_disable_wa(const struct intel_context *ce, u32 *cs)/* If predication is active, this will be noop'ed */ 4 - 2 );0 ;0 ; /* No predication */ /* predicated end, only terminates if SET_PREDICATE_RESULT:0 is clear */ 15 );/* Instructions are no longer predicated (disabled), we can proceed */ 4 - 2 );0 ;1 ; /* enable predication before the next BB */ return cs;static struct i915_vma *struct intel_context *ce, struct intel_engine_cs *engine)struct drm_i915_gem_object *obj;struct i915_vma *vma;if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))/* for redzone */ if (GRAPHICS_VER(engine->i915) >= 12 ) {/* INDIRECT_CTX and PER_CTX_BB need separate pages. */ 2 ;if (intel_context_is_parent(ce) && intel_engine_uses_guc(engine)) {if (IS_ERR(obj)) {if (IS_ERR(obj))return ERR_CAST(obj);/* * Wa_22016122933 : For Media version 13 . 0 , all Media GT shared * memory needs to be mapped as WC on CPU side and UC ( PAT * index 2 ) on GPU side . if (intel_gt_needs_wa_22016122933(engine->gt))if (IS_ERR(vma)) {return vma;return vma;static struct intel_timeline *struct intel_context *ce, struct intel_engine_cs *engine)struct intel_timeline *tl = fetch_and_zero(&ce->timeline);return intel_timeline_create_from_engine(engine, page_unmask_bits(tl));int lrc_alloc(struct intel_context *ce, struct intel_engine_cs *engine)struct intel_ring *ring;struct i915_vma *vma;int err;if (!intel_context_has_own_state(ce))if (IS_ERR(vma))return PTR_ERR(vma);if (IS_ERR(ring)) {goto err_vma;if (!page_mask_bits(ce->timeline)) {struct intel_timeline *tl;/* * Use the static global HWSP for the kernel context , and * a dynamically allocated cacheline for everyone else . if (unlikely(ce->timeline))else if (IS_ERR(tl)) {goto err_ring;return 0 ;return err;void lrc_reset(struct intel_context *ce)/* Scrub away the garbage */ true );int struct intel_context *ce,struct intel_engine_cs *engine,struct i915_gem_ww_ctx *ww,void **vaddr)false ) |return PTR_ERR_OR_ZERO(*vaddr);int struct intel_context *ce,struct intel_engine_cs *engine,void *vaddr)if (!__test_and_set_bit(CONTEXT_INIT_BIT, &ce->flags))return 0 ;void lrc_unpin(struct intel_context *ce)if (unlikely(ce->parallel.last_rq)) {void *)ce->lrc_reg_state - LRC_STATE_OFFSET,void lrc_post_unpin(struct intel_context *ce)void lrc_fini(struct intel_context *ce)if (!ce->state)return ;void lrc_destroy(struct kref *kref)struct intel_context *ce = container_of(kref, typeof(*ce), ref);static u32 *const struct intel_context *ce, u32 *cs)0 , 0 ));sizeof (u32);0 ;0 , 0 ));0 ));0 , 0 ));0 ));return cs;static u32 *const struct intel_context *ce, u32 *cs)1 );0 , 0 ));1 ) * sizeof (u32);0 ;return cs;static u32 *const struct intel_context *ce, u32 *cs)1 );0 , 0 ));1 ) * sizeof (u32);0 ;0 , 0 ));0 ));return cs;/* * The bspec ' s tuning guide asks us to program a vertical watermark value of * 0 x3FF . However this register is not saved / restored properly by the * hardware , so we ' re required to apply the desired value via INDIRECT_CTX * batch buffer to ensure the value takes effect properly . All other bits * in this register should remain at 0 ( the hardware default ) . static u32 *1 );0 x3FF);return cs;static u32 *1 );return cs;static u32 *const struct intel_context *ce, u32 *cs)/* Wa_16013000631:dg2 */ if (IS_DG2_G11(ce->engine->i915))0 );/* Wa_18022495364 */ if (IS_GFX_GT_IP_RANGE(ce->engine->gt, IP_VER(12 , 0 ), IP_VER(12 , 10 )))/* Wa_16014892111 */ if (IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12 , 70 ), STEP_A0, STEP_B0) ||12 , 71 ), STEP_A0, STEP_B0) ||return cs;static u32 *const struct intel_context *ce, u32 *cs)/* Wa_16013000631:dg2 */ if (IS_DG2_G11(ce->engine->i915))if (ce->engine->class == COMPUTE_CLASS)0 );return gen12_emit_aux_table_inv(ce->engine, cs);static u32 *xehp_emit_fastcolor_blt_wabb(const struct intel_context *ce, u32 *cs)struct intel_gt *gt = ce->engine->gt;int mocs = gt->mocs.uc_index << 1 ;/** * Wa_16018031267 / Wa_16018063123 requires that SW forces the * main copy engine arbitration into round robin mode . We * additionally need to submit the following WABB blt command * to produce 4 subblits with each subblit generating 0 byte * write requests as WABB : * * XY_FASTCOLOR_BLT * BG0 - > 5100000 E * BG1 - > 0000003 F ( Dest pitch ) * BG2 - > 00000000 ( X1 , Y1 ) = ( 0 , 0 ) * BG3 - > 00040001 ( X2 , Y2 ) = ( 1 , 4 ) * BG4 - > scratch * BG5 - > scratch * BG6 - 12 - > 00000000 * BG13 - > 20004004 ( Surf . Width = 2 , Surf . Height = 5 ) * BG14 - > 00000010 ( Qpitch = 4 ) * BG15 - > 00000000 16 - 2 );0 x3f;0 ;4 << 16 | 1 ;0 ;0 ;0 ;0 ;0 ;0 ;0 ;0 x20004004;0 x10;0 ;return cs;static u32 *const struct intel_context *ce, u32 *cs)/* Wa_16018031267, Wa_16018063123 */ if (NEEDS_FASTCOLOR_BLT_WABB(ce->engine))return cs;static void const struct intel_context *ce,const struct intel_engine_cs *engine,const struct intel_context *, u32 *))/* Place PER_CTX_BB on next page after INDIRECT_CTX */ const start = context_wabb(ce, true );/* PER_CTX_BB must manually terminate */ sizeof (*cs));static void const struct intel_context *ce,const struct intel_engine_cs *engine,const struct intel_context *, u32 *))const start = context_wabb(ce, false );sizeof (*cs));while ((unsigned long )cs % CACHELINE_BYTES)sizeof (*start));sizeof (*start));sizeof (*cs));/* * The context descriptor encodes various attributes of a context , * including its GTT address and some flags . Because it ' s fairly * expensive to calculate , we ' ll just do it once and cache the result , * which remains valid until the context is unpinned . * * This is what a descriptor looks like , from LSB to MSB : : * * bits 0 - 11 : flags , GEN8_CTX_ * ( cached in ctx - > desc_template ) * bits 12 - 31 : LRCA , GTT address of ( the HWSP of ) this context * bits 32 - 52 : ctx ID , a globally unique tag ( highest bit used by GuC ) * bits 53 - 54 : mbz , reserved for use by hardware * bits 55 - 63 : group ID , currently unused and set to 0 * * Starting from Gen11 , the upper dword of the descriptor has a new format : * * bits 32 - 36 : reserved * bits 37 - 47 : SW context ID * bits 48 : 53 : engine instance * bit 54 : mbz , reserved for use by hardware * bits 55 - 60 : SW counter * bits 61 - 63 : engine class * * On Xe_HP , the upper dword of the descriptor has a new format : * * bits 32 - 37 : virtual function number * bit 38 : mbz , reserved for use by hardware * bits 39 - 54 : SW context ID * bits 55 - 57 : reserved * bits 58 - 63 : SW counter * * engine info , SW context ID and SW counter need to form a unique number * ( Context ID ) per lrc . static u32 lrc_descriptor(const struct intel_context *ce)if (i915_vm_is_4lvl(ce->vm))if (GRAPHICS_VER(ce->vm->i915) == 8 )return i915_ggtt_offset(ce->state) | desc;const struct intel_context *ce,const struct intel_engine_cs *engine,struct intel_ring *ring = ce->ring;/* RPCS */ if (engine->class == RENDER_CLASS) {if (ce->wa_bb_page) {const struct intel_context *ce, u32 *cs);if (ce->engine->class == RENDER_CLASS)/* Mutually exclusive wrt to global indirect bb */ return lrc_descriptor(ce) | CTX_DESC_FORCE_RESTORE;void lrc_update_offsets(struct intel_context *ce,struct intel_engine_cs *engine)false );void lrc_check_regs(const struct intel_context *ce,const struct intel_engine_cs *engine,const char *when)const struct intel_ring *ring = ce->ring;bool valid = true ;int x;if (regs[CTX_RING_START] != i915_ggtt_offset(ring->vma)) {"%s: context submitted with incorrect RING_START [%08x], expected %08x\n" ,false ;if ((regs[CTX_RING_CTL] & ~(RING_WAIT | RING_WAIT_SEMAPHORE)) !="%s: context submitted with incorrect RING_CTL [%08x], expected %08x\n" ,false ;if (x != -1 && regs[x + 1 ] & (regs[x + 1 ] >> 16 ) & STOP_RING) {"%s: context submitted with STOP_RING [%08x] in RING_MI_MODE\n" ,1 ]);1 ] &= ~STOP_RING;1 ] |= STOP_RING << 16 ;false ;"Invalid lrc state found %s submission\n" , when);/* * In this WA we need to set GEN8_L3SQCREG4 [ 21 : 21 ] and reset it after * PIPE_CONTROL instruction . This is required for the flush to happen correctly * but there is a slight complication as this is applied in WA batch where the * values are only initialized once so we cannot take register value at the * beginning and reuse it further ; hence we save its value to memory , upload a * constant value with bit21 set and then we restore it back with the saved value . * To simplify the WA , a constant value is formed by using the default value * of this register . This shouldn ' t be a problem because we are only modifying * it for a short period and this batch in non - premptible . We can ofcourse * use additional instructions that read the actual value of the register * at that time and set our bit of interest but it makes the WA complicated . * * This WA is also required for Gen9 so extracting as a function avoids * code duplication . static u32 *struct intel_engine_cs *engine, u32 *batch)/* NB no one else is allowed to scribble over scratch + 256! */ 0 ;1 );0 x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;0 );0 ;return batch;/* * Typically we only have one indirect_ctx and per_ctx batch buffer which are * initialized at the beginning and shared across all contexts but this field * helps us to have multiple batches at different offsets and select them based * on a criteria . At the moment this batch always start at the beginning of the page * and at this point we don ' t have multiple wa_ctx batch buffers . * * The number of WA applied are not known at the beginning ; we use this field * to return the no of DWORDS written . * * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END * so it adds NOOPs as padding to make it cacheline aligned . * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together * makes a complete batch buffer . static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)/* WaDisableCtxRestoreArbitration:bdw,chv */ /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ if (IS_BROADWELL(engine->i915))/* WaClearSlmSpaceAtContextSwitch:bdw,chv */ /* Actual scratch location is at 128 bytes offset */ /* Pad to end of cacheline */ while ((unsigned long )batch % CACHELINE_BYTES)/* * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because * execution depends on the length specified in terms of cache lines * in the register CTX_RCS_INDIRECT_CTX return batch;struct lri {static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count)63 );do {while (lri++, --count);return batch;static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)static const struct lri lri[] = {/* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ 0 ),/* BSpec: 11391 */ /* BSpec: 11299 */ 3 D_CHICKEN3,3 D_CHICKEN_SF_PROVOKING_VERTEX_FIX,3 D_CHICKEN_SF_PROVOKING_VERTEX_FIX),/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ /* WaClearSlmSpaceAtContextSwitch:skl,bxt,kbl,glk,cfl */ /* WaMediaPoolStateCmdInWABB:bxt,glk */ if (HAS_POOLED_EU(engine->i915)) {/* * EU pool configuration is setup along with golden context * during context initialization . This value depends on * device type ( 2 x6 or 3 x6 ) and needs to be updated based * on which subslice is disabled especially for 2 x6 * devices , however it is safe to load default * configuration of 3 x6 device instead of masking off * corresponding bits because HW ignores bits of a disabled * subslice and drops down to appropriate config . Please * see render_state_setup ( ) in i915_gem_render_state . c for * possible configurations , to avoid duplication they are * not shown here again . 0 x00777000;0 ;0 ;0 ;/* Pad to end of cacheline */ while ((unsigned long )batch % CACHELINE_BYTES)return batch;#define CTX_WA_BB_SIZE (PAGE_SIZE)static int lrc_create_wa_ctx(struct intel_engine_cs *engine)struct drm_i915_gem_object *obj;struct i915_vma *vma;int err;if (IS_ERR(obj))return PTR_ERR(obj);if (IS_ERR(vma)) {goto err;return 0 ;return err;void lrc_fini_wa_ctx(struct intel_engine_cs *engine)0 );typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);void lrc_init_wa_ctx(struct intel_engine_cs *engine)struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;struct i915_wa_ctx_bb *wa_bb[] = {struct i915_gem_ww_ctx ww;void *batch, *batch_ptr;unsigned int i;int err;if (GRAPHICS_VER(engine->i915) >= 11 ||return ;if (GRAPHICS_VER(engine->i915) == 9 ) {0 ] = gen9_init_indirectctx_bb;1 ] = NULL;else if (GRAPHICS_VER(engine->i915) == 8 ) {0 ] = gen8_init_indirectctx_bb;1 ] = NULL;if (err) {/* * We continue even if we fail to initialize WA batch * because we only expect rare glitches but nothing * critical to prevent us from using GPU "Ignoring context switch w/a allocation error:%d\n" ,return ;if (!engine->wa_ctx.vma)return ;true );if (!err)0 , PIN_HIGH);if (err)goto err;if (IS_ERR(batch)) {goto err_unpin;/* * Emit the two workaround batch buffers , recording the offset from the * start of the workaround batch buffer object for each and their * respective sizes . for (i = 0 ; i < ARRAY_SIZE(wa_bb_fn); i++) {if (GEM_DEBUG_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset,break ;if (wa_bb_fn[i])0 , batch_ptr - batch);/* Verify that we can handle failure to setup the wa_ctx */ if (!err)if (err)if (err == -EDEADLK) {if (!err)goto retry;if (err) {/* Clear all flags to prevent further use */ 0 , sizeof (*wa_ctx));static void st_runtime_underflow(struct intel_context_stats *stats, s32 dt)#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)#endif static u32 lrc_get_runtime(const struct intel_context *ce)/* * We can use either ppHWSP [ 16 ] which is recorded before the context * switch ( and so excludes the cost of context switches ) or use the * value from the context image itself , which is saved / restored earlier * and so includes the cost of the save . return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);void lrc_update_runtime(struct intel_context *ce)struct intel_context_stats *stats = &ce->stats;if (!dt)return ;if (unlikely(dt < 0 )) {"runtime underflow: last=%u, new=%u, delta=%d\n" ,return ;#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)#include "selftest_lrc.c" #endif
Messung V0.5 in Prozent C=98 H=95 G=96
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(vorverarbeitet am 2026-10-03)
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