// SPDX-License-Identifier: MIT /* * Copyright © 2022 Intel Corporation #include <linux/debugfs.h>#include <drm/drm_blend.h>#include <drm/drm_file.h>#include <drm/drm_print.h>#include "soc/intel_dram.h" #include "i915_reg.h" #include "i915_utils.h" #include "i9xx_wm.h" #include "intel_atomic.h" #include "intel_bw.h" #include "intel_cdclk.h" #include "intel_crtc.h" #include "intel_cursor_regs.h" #include "intel_de.h" #include "intel_display.h" #include "intel_display_power.h" #include "intel_display_regs.h" #include "intel_display_rpm.h" #include "intel_display_types.h" #include "intel_fb.h" #include "intel_fixed.h" #include "intel_flipq.h" #include "intel_pcode.h" #include "intel_plane.h" #include "intel_wm.h" #include "skl_universal_plane_regs.h" #include "skl_watermark.h" #include "skl_watermark_regs.h" struct intel_dbuf_state {struct intel_global_state base;struct skl_ddb_entry ddb[I915_MAX_PIPES];unsigned int weight[I915_MAX_PIPES];bool joined_mbus;#define to_intel_dbuf_state(global_state) \struct intel_dbuf_state, base)#define intel_atomic_get_old_dbuf_state(state) \#define intel_atomic_get_new_dbuf_state(state) \static void skl_sagv_disable(struct intel_display *display);/* Stores plane specific WM parameters */ struct skl_wm_params {bool x_tiled, y_tiled;bool rc_surface;bool is_planar;struct intel_display *display)0 ;enum dbuf_slice slice;if (intel_de_read(display, DBUF_CTL_S(slice)) & DBUF_POWER_STATE)return enabled_slices;/* * FIXME : We still don ' t have the proper code detect if we need to apply the WA , * so assume we ' ll always need it in order to avoid underruns . static bool skl_needs_memory_bw_wa(struct intel_display *display)return DISPLAY_VER(display) == 9 ;bool struct intel_display *display)return HAS_SAGV(display) && display->sagv.status != I915_SAGV_NOT_CONTROLLED;static u32struct intel_display *display)if (DISPLAY_VER(display) >= 14 ) {return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val);else if (DISPLAY_VER(display) >= 12 ) {0 ;int ret;if (ret) {"Couldn't read SAGV block time!\n" );return 0 ;return val;else if (DISPLAY_VER(display) == 11 ) {return 10 ;else if (HAS_SAGV(display)) {return 30 ;else {return 0 ;static void intel_sagv_init(struct intel_display *display)if (!HAS_SAGV(display))/* * Probe to see if we have working SAGV control . * For icl + this was already determined by intel_bw_init_hw ( ) . if (DISPLAY_VER(display) < 11 )"SAGV supported: %s, original SAGV block time: %u us\n" ,/* avoid overflow when adding with wm0 latency/etc. */ if (drm_WARN(display->drm, display->sagv.block_time_us > U16_MAX,"Excessive SAGV block time %u, ignoring\n" ,0 ;if (!intel_has_sagv(display))0 ;/* * SAGV dynamically adjusts the system agent voltage and clock frequencies * depending on power and performance requirements . The display engine access * to system memory is blocked during the adjustment time . Because of the * blocking time , having this enabled can cause full system hangs and / or pipe * underruns if we don ' t meet all of the following requirements : * * - < = 1 pipe enabled * - All planes can enable watermarks for latencies > = SAGV engine block time * - We ' re not using an interlaced display configuration static void skl_sagv_enable(struct intel_display *display)int ret;if (!intel_has_sagv(display))return ;if (display->sagv.status == I915_SAGV_ENABLED)return ;"Enabling SAGV\n" );/* We don't need to wait for SAGV when enabling */ /* * Some skl systems , pre - release machines in particular , * don ' t actually have SAGV . if (display->platform.skylake && ret == -ENXIO) {"No SAGV found on system, ignoring\n" );return ;else if (ret < 0 ) {"Failed to enable SAGV\n" );return ;static void skl_sagv_disable(struct intel_display *display)int ret;if (!intel_has_sagv(display))return ;if (display->sagv.status == I915_SAGV_DISABLED)return ;"Disabling SAGV\n" );/* bspec says to keep retrying for at least 1 ms */ 1 );/* * Some skl systems , pre - release machines in particular , * don ' t actually have SAGV . if (display->platform.skylake && ret == -ENXIO) {"No SAGV found on system, ignoring\n" );return ;else if (ret < 0 ) {"Failed to disable SAGV (%d)\n" , ret);return ;static void skl_sagv_pre_plane_update(struct intel_atomic_state *state)struct intel_display *display = to_intel_display(state);const struct intel_bw_state *new_bw_state =if (!new_bw_state)return ;if (!intel_bw_can_enable_sagv(display, new_bw_state))static void skl_sagv_post_plane_update(struct intel_atomic_state *state)struct intel_display *display = to_intel_display(state);const struct intel_bw_state *new_bw_state =if (!new_bw_state)return ;if (intel_bw_can_enable_sagv(display, new_bw_state))void intel_sagv_pre_plane_update(struct intel_atomic_state *state)struct intel_display *display = to_intel_display(state);/* * Just return if we can ' t control SAGV or don ' t have it . * This is different from situation when we have SAGV but just can ' t * afford it due to DBuf limitation - in case if SAGV is completely * disabled in a BIOS , we are not even allowed to send a PCode request , * as it will throw an error . So have to check it here . if (!intel_has_sagv(display))return ;if (DISPLAY_VER(display) >= 11 )else void intel_sagv_post_plane_update(struct intel_atomic_state *state)struct intel_display *display = to_intel_display(state);/* * Just return if we can ' t control SAGV or don ' t have it . * This is different from situation when we have SAGV but just can ' t * afford it due to DBuf limitation - in case if SAGV is completely * disabled in a BIOS , we are not even allowed to send a PCode request , * as it will throw an error . So have to check it here . if (!intel_has_sagv(display))return ;if (DISPLAY_VER(display) >= 11 )else static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)struct intel_display *display = to_intel_display(crtc_state);struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);enum plane_id plane_id;int max_level = INT_MAX;if (!intel_has_sagv(display))return false ;if (!crtc_state->hw.active)return true ;if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE)return false ;const struct skl_plane_wm *wm =int level;/* Skip this plane if it's not enabled */ if (!wm->wm[0 ].enable)continue ;/* Find the highest enabled wm level for this plane */ for (level = display->wm.num_levels - 1 ;/* Highest common enabled wm level for all planes */ /* No enabled planes? */ if (max_level == INT_MAX)return true ;const struct skl_plane_wm *wm =/* * All enabled planes must have enabled a common wm level that * can tolerate memory latencies higher than sagv_block_time_us if (wm->wm[0 ].enable && !wm->wm[max_level].can_sagv)return false ;return true ;static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);enum plane_id plane_id;if (!crtc_state->hw.active)return true ;const struct skl_plane_wm *wm =if (wm->wm[0 ].enable && !wm->sagv.wm0.enable)return false ;return true ;bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)struct intel_display *display = to_intel_display(crtc_state);if (!display->params.enable_sagv)return false ;/* * SAGV is initially forced off because its current * state can ' t be queried from pcode . Allow SAGV to * be enabled upon the first real commit . if (crtc_state->inherited)return false ;if (DISPLAY_VER(display) >= 12 )return tgl_crtc_can_enable_sagv(crtc_state);else return skl_crtc_can_enable_sagv(crtc_state);static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,return end;static int intel_dbuf_slice_size(struct intel_display *display)return DISPLAY_INFO(display)->dbuf.size /static void struct intel_display *display, u8 slice_mask,struct skl_ddb_entry *ddb)int slice_size = intel_dbuf_slice_size(display);if (!slice_mask) {0 ;0 ;return ;1 ) * slice_size;static unsigned int mbus_ddb_offset(struct intel_display *display, u8 slice_mask)struct skl_ddb_entry ddb;if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2)))else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4)))return ddb.start;struct intel_display *display,const struct skl_ddb_entry *entry)int slice_size = intel_dbuf_slice_size(display);enum dbuf_slice start_slice, end_slice;0 ;if (!skl_ddb_entry_size(entry))return 0 ;1 ) / slice_size;/* * Per plane DDB entry can in a really worst case be on multiple slices * but single entry is anyway contiguous . while (start_slice <= end_slice) {return slice_mask;static unsigned int intel_crtc_ddb_weight(const struct intel_crtc_state *crtc_state)const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;int hdisplay, vdisplay;if (!crtc_state->hw.active)return 0 ;/* * Watermark / ddb requirement highly depends upon width of the * framebuffer , So instead of allocating DDB equally among pipes * distribute DDB based on resolution / width of the display . return hdisplay;static void intel_crtc_dbuf_weights(const struct intel_dbuf_state *dbuf_state,enum pipe for_pipe,unsigned int *weight_start,unsigned int *weight_end,unsigned int *weight_total)struct intel_display *display = to_intel_display(dbuf_state->base.state->base.dev);enum pipe pipe;0 ;0 ;0 ;int weight = dbuf_state->weight[pipe];/* * Do not account pipes using other slice sets * luckily as of current BSpec slice sets do not partially * intersect ( pipes share either same one slice or same slice set * i . e no partial intersection ) , so it is enough to check for * equality for now . if (dbuf_state->slices[pipe] != dbuf_state->slices[for_pipe])continue ;if (pipe < for_pipe) {else if (pipe == for_pipe) {static int struct intel_atomic_state *state, struct intel_crtc *crtc)struct intel_display *display = to_intel_display(crtc);unsigned int weight_total, weight_start, weight_end;const struct intel_dbuf_state *old_dbuf_state =struct intel_dbuf_state *new_dbuf_state =struct intel_crtc_state *crtc_state;struct skl_ddb_entry ddb_slices;enum pipe pipe = crtc->pipe;unsigned int mbus_offset = 0 ;int ret;if (new_dbuf_state->weight[pipe] == 0 ) {0 , 0 );goto out;if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] &&return 0 ;if (ret)return ret;if (IS_ERR(crtc_state))return PTR_ERR(crtc_state);/* * Used for checking overlaps , so we need absolute * offsets instead of MBUS relative offsets . "[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x\n" ,return 0 ;static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,int width, const struct drm_format_info *format,unsigned int rotation,struct skl_wm_params *wp,int color_plane, unsigned int pan_x);static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,struct intel_plane *plane,int level,unsigned int latency,const struct skl_wm_params *wp,const struct skl_wm_level *result_prev,struct skl_wm_level *result /* out */); static unsigned int skl_wm_latency(struct intel_display *display, int level,const struct skl_wm_params *wp)unsigned int latency = display->wm.skl_latency[level];if (latency == 0 )return 0 ;/* * WaIncreaseLatencyIPCEnabled : kbl , cfl * Display WA # 1141 : kbl , cfl if ((display->platform.kabylake || display->platform.coffeelake ||4 ;if (skl_needs_memory_bw_wa(display) && wp && wp->x_tiled)15 ;return latency;static unsigned int const struct intel_crtc_state *crtc_state,int num_active)struct intel_display *display = to_intel_display(crtc_state);struct intel_plane *plane = to_intel_plane(crtc_state->uapi.crtc->cursor);struct skl_wm_level wm = {};int ret, min_ddb_alloc = 0 ;struct skl_wm_params wp;int level;256 ,0 , 0 );for (level = 0 ; level < display->wm.num_levels; level++) {unsigned int latency = skl_wm_latency(display, level, &wp);if (wm.min_ddb_alloc == U16_MAX)break ;return max(num_active == 1 ? 32 : 8 , min_ddb_alloc);static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)if (entry->end)static void struct intel_display *display,const enum pipe pipe,const enum plane_id plane_id,struct skl_ddb_entry *ddb,struct skl_ddb_entry *ddb_y,/* Cursor doesn't support NV12/planar, so no extra calculation needed */ if (plane_id == PLANE_CURSOR) {return ;if (DISPLAY_VER(display) >= 30 ) {if (DISPLAY_VER(display) >= 11 )return ;static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,struct skl_ddb_entry *ddb,struct skl_ddb_entry *ddb_y,struct intel_display *display = to_intel_display(crtc);enum intel_display_power_domain power_domain;enum pipe pipe = crtc->pipe;enum plane_id plane_id;if (!wakeref)return ;struct dbuf_slice_conf_entry {bool join_mbus;/* * Table taken from Bspec 12716 * Pipes do have some preferred DBuf slice affinity , * plus there are some hardcoded requirements on how * those should be distributed for multipipe scenarios . * For more DBuf slices algorithm can get even more messy * and less readable , so decided to use a table almost * as is from BSpec itself - that way it is at least easier * to compare , change and check . static const struct dbuf_slice_conf_entry icl_allowed_dbufs[] =/* Autogenerated with igt/tools/intel_dbuf_map tool: */ /* * Table taken from Bspec 49255 * Pipes do have some preferred DBuf slice affinity , * plus there are some hardcoded requirements on how * those should be distributed for multipipe scenarios . * For more DBuf slices algorithm can get even more messy * and less readable , so decided to use a table almost * as is from BSpec itself - that way it is at least easier * to compare , change and check . static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] =/* Autogenerated with igt/tools/intel_dbuf_map tool: */ static const struct dbuf_slice_conf_entry dg2_allowed_dbufs[] = {static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = {/* * Keep the join_mbus cases first so check_mbus_joined ( ) * will prefer them over the ! join_mbus cases . true ,true ,false ,false ,static bool check_mbus_joined(u8 active_pipes,const struct dbuf_slice_conf_entry *dbuf_slices)int i;for (i = 0 ; dbuf_slices[i].active_pipes != 0 ; i++) {if (dbuf_slices[i].active_pipes == active_pipes)return dbuf_slices[i].join_mbus;return false ;static bool adlp_check_mbus_joined(u8 active_pipes)return check_mbus_joined(active_pipes, adlp_allowed_dbufs);static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus,const struct dbuf_slice_conf_entry *dbuf_slices)int i;for (i = 0 ; dbuf_slices[i].active_pipes != 0 ; i++) {if (dbuf_slices[i].active_pipes == active_pipes &&return dbuf_slices[i].dbuf_mask[pipe];return 0 ;/* * This function finds an entry with same enabled pipe configuration and * returns correspondent DBuf slice mask as stated in BSpec for particular * platform . static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)/* * FIXME : For ICL this is still a bit unclear as prev BSpec revision * required calculating " pipe ratio " in order to determine * if one or two slices can be used for single pipe configurations * as additional constraint to the existing table . * However based on recent info , it should be not " pipe ratio " * but rather ratio between pixel_rate and cdclk with additional * constants , so for now we are using only table until this is * clarified . Also this is the reason why crtc_state param is * still here - we will need it once those additional constraints * pop up . return compute_dbuf_slices(pipe, active_pipes, join_mbus,static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)return compute_dbuf_slices(pipe, active_pipes, join_mbus,static u8 adlp_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)return compute_dbuf_slices(pipe, active_pipes, join_mbus,static u8 dg2_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)return compute_dbuf_slices(pipe, active_pipes, join_mbus,static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes, bool join_mbus)struct intel_display *display = to_intel_display(crtc);enum pipe pipe = crtc->pipe;if (display->platform.dg2)return dg2_compute_dbuf_slices(pipe, active_pipes, join_mbus);else if (DISPLAY_VER(display) >= 13 )return adlp_compute_dbuf_slices(pipe, active_pipes, join_mbus);else if (DISPLAY_VER(display) == 12 )return tgl_compute_dbuf_slices(pipe, active_pipes, join_mbus);else if (DISPLAY_VER(display) == 11 )return icl_compute_dbuf_slices(pipe, active_pipes, join_mbus);/* * For anything else just return one slice yet . * Should be extended for other platforms . return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0 ;static bool const struct intel_crtc_state *crtc_state,struct intel_plane *plane)struct intel_display *display = to_intel_display(plane);/* Xe3+ are auto minimum DDB capble. So don't force minimal wm0 */ return IS_DISPLAY_VER(display, 13 , 20 ) &&unsigned int const struct intel_crtc_state *crtc_state,struct intel_plane *plane, int width, int height,int cpp)/* * We calculate extra ddb based on ratio plane rate / total data rate * in case , in some cases we should not allocate extra ddb for the plane , * so do not count its data rate , if this is the case . if (use_minimal_wm0_only(crtc_state, plane))return 0 ;return width * height * cpp;static u64const struct intel_crtc_state *crtc_state)struct intel_display *display = to_intel_display(crtc_state);struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);enum plane_id plane_id;0 ;if (plane_id == PLANE_CURSOR)continue ;if (DISPLAY_VER(display) < 11 )return data_rate;const struct skl_wm_level *const struct skl_pipe_wm *pipe_wm,enum plane_id plane_id,int level)const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];if (level == 0 && pipe_wm->use_sagv_wm)return &wm->sagv.wm0;return &wm->wm[level];const struct skl_wm_level *const struct skl_pipe_wm *pipe_wm,enum plane_id plane_id)const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];if (pipe_wm->use_sagv_wm)return &wm->sagv.trans_wm;return &wm->trans_wm;/* * We only disable the watermarks for each plane if * they exceed the ddb allocation of said plane . This * is done so that we don ' t end up touching cursor * watermarks needlessly when some other plane reduces * our max possible watermark level . * * Bspec has this to say about the PLANE_WM enable bit : * " All the watermarks at this level for all enabled * planes must be enabled before the level will be used . " * So this is actually safe to do . static void struct skl_wm_level *wm, const struct skl_ddb_entry *ddb)if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb))0 , sizeof (*wm));static void struct skl_wm_level *wm, struct skl_wm_level *uv_wm,const struct skl_ddb_entry *ddb_y, const struct skl_ddb_entry *ddb)if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb_y) ||0 , sizeof (*wm));0 , sizeof (*uv_wm));static bool skl_need_wm_copy_wa(struct intel_display *display, int level,const struct skl_plane_wm *wm)/* * Wa_1408961008 : icl , ehl * Wa_14012656716 : tgl , adl * Wa_14017887344 : icl * Wa_14017868169 : adl , tgl * Due to some power saving optimizations , different subsystems * like PSR , might still use even disabled wm level registers , * for " reference " , so lets keep at least the values sane . * Considering amount of WA requiring us to do similar things , was * decided to simply do it for all of the platforms , as those wm * levels are disabled , this isn ' t going to do harm anyway . return level > 0 && !wm->wm[level].enable;struct skl_plane_ddb_iter {static void struct skl_plane_ddb_iter *iter,struct skl_ddb_entry *ddb,const struct skl_wm_level *wm,0 ;if (data_rate) {/* * Keep ddb entry of all disabled planes explicitly zeroed * to avoid skl_ddb_add_affected_planes ( ) adding them to * the state when other planes change their allocations . if (size)static int struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_crtc_state *crtc_state =const struct intel_dbuf_state *dbuf_state =const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];struct intel_display *display = to_intel_display(state);int num_active = hweight8(dbuf_state->active_pipes);struct skl_plane_ddb_iter iter;enum plane_id plane_id;int level;/* Clear the partitioning for disabled planes. */ 0 , sizeof (crtc_state->wm.skl.plane_ddb));0 , sizeof (crtc_state->wm.skl.plane_ddb_y));0 ,sizeof (crtc_state->wm.skl.plane_min_ddb));0 ,sizeof (crtc_state->wm.skl.plane_interim_ddb));if (!crtc_state->hw.active)return 0 ;if (iter.size == 0 )return 0 ;/* Allocate fixed number of blocks for cursor. */ /* * Find the highest watermark level for which we can satisfy the block * requirement of active planes . for (level = display->wm.num_levels - 1 ; level >= 0 ; level--) {0 ;const struct skl_plane_wm *wm =if (plane_id == PLANE_CURSOR) {const struct skl_ddb_entry *ddb =if (wm->wm[level].min_ddb_alloc > skl_ddb_entry_size(ddb)) {break ;continue ;if (blocks <= iter.size) {break ;if (level < 0 ) {"Requested display configuration exceeds system DDB limitations" );"minimum required %d/%d\n" ,return -EINVAL;/* avoid the WARN later when we don't allocate any extra DDB */ if (iter.data_rate == 0 )0 ;/* * Grant each plane the blocks it requires at the highest achievable * watermark level , plus an extra share of the leftover blocks * proportional to its relative data rate . struct skl_ddb_entry *ddb =struct skl_ddb_entry *ddb_y =const struct skl_plane_wm *wm =if (plane_id == PLANE_CURSOR)continue ;if (DISPLAY_VER(display) < 11 &&else {if (DISPLAY_VER(display) >= 30 ) {0 ].min_ddb_alloc;0 || iter.data_rate != 0 );/* * When we calculated watermark values we didn ' t know how high * of a level we ' d actually be able to hit , so we just marked * all levels as " enabled . " Go back now and disable the ones * that aren ' t actually possible . for (level++; level < display->wm.num_levels; level++) {const struct skl_ddb_entry *ddb =const struct skl_ddb_entry *ddb_y =struct skl_plane_wm *wm =if (DISPLAY_VER(display) < 11 &&else if (skl_need_wm_copy_wa(display, level, wm)) {1 ].blocks;1 ].lines;1 ].ignore_lines;/* * Go back and disable the transition and SAGV watermarks * if it turns out we don ' t have enough DDB blocks for them . const struct skl_ddb_entry *ddb =const struct skl_ddb_entry *ddb_y =struct skl_plane_wm *wm =if (DISPLAY_VER(display) < 11 &&else {if (DISPLAY_VER(display) >= 30 )return 0 ;/* * The max latency should be 257 ( max the punit can code is 255 and we add 2 us * for the read latency ) and cpp should always be < = 8 , so that * should allow pixel_rate up to ~ 2 GHz which seems sufficient since max * 2 xcdclk is 1350 MHz and the pixel rate should never exceed that . static uint_fixed_16_16_tstruct intel_display *display, u32 pixel_rate,if (latency == 0 )return FP_16_16_MAX;1000 * dbuf_block_size);if (DISPLAY_VER(display) >= 10 )1 );return ret;static uint_fixed_16_16_tif (latency == 0 )return FP_16_16_MAX;1000 );return ret;static uint_fixed_16_16_tconst struct intel_crtc_state *crtc_state)struct intel_display *display = to_intel_display(crtc_state);if (!crtc_state->hw.active)return u32_to_fixed16(0 );if (drm_WARN_ON(display->drm, pixel_rate == 0 ))return u32_to_fixed16(0 );1000 , pixel_rate);return linetime_us;static int const struct intel_crtc_state *crtc_state,int width, const struct drm_format_info *format,unsigned int rotation,struct skl_wm_params *wp,int color_plane, unsigned int pan_x)struct intel_display *display = to_intel_display(crtc_state);/* only planar format has two planes */ if (color_plane == 1 &&"Non planar format have single plane\n" );return -EINVAL;if (color_plane == 1 && wp->is_planar)2 ;if (DISPLAY_VER(display) >= 11 &&1 )256 ;else 512 ;if (drm_rotation_90_or_270(rotation)) {switch (wp->cpp) {case 1 :16 ;break ;case 2 :8 ;break ;case 4 :4 ;break ;default :return -EINVAL;else {4 ;if (skl_needs_memory_bw_wa(display))2 ;if (wp->y_tiled) {if (DISPLAY_VER(display) >= 30 )0 );else if (DISPLAY_VER(display) >= 10 )else {if (!wp->x_tiled || DISPLAY_VER(display) >= 10 )return 0 ;static int const struct intel_crtc_state *crtc_state,const struct intel_plane_state *plane_state,struct skl_wm_params *wp, int color_plane)const struct drm_framebuffer *fb = plane_state->hw.fb;int width;/* * Src coordinates are already rotated by 270 degrees for * the 90 / 270 degree plane rotation cases ( to match the * GTT mapping ) , hence no need to account for rotation here . 16 ;return skl_compute_wm_params(crtc_state, width,static bool skl_wm_has_lines(struct intel_display *display, int level)if (DISPLAY_VER(display) >= 10 )return true ;/* The number of lines are ignored for the level 0 watermark. */ return level > 0 ;static int skl_wm_max_lines(struct intel_display *display)if (DISPLAY_VER(display) >= 13 )return 255 ;else return 31 ;static bool xe3_auto_min_alloc_capable(struct intel_plane *plane, int level)struct intel_display *display = to_intel_display(plane);return DISPLAY_VER(display) >= 30 && level == 0 && plane->id != PLANE_CURSOR;static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,struct intel_plane *plane,int level,unsigned int latency,const struct skl_wm_params *wp,const struct skl_wm_level *result_prev,struct skl_wm_level *result /* out */) struct intel_display *display = to_intel_display(crtc_state);0 ;if (latency == 0 ||0 )) {/* reject it */ return ;if (wp->y_tiled) {else {if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /1 ) &&1 )) {else if (latency >= wp->linetime_us) {if (DISPLAY_VER(display) == 9 )else else {if (DISPLAY_VER(display) < 30 )/* * Lets have blocks at minimum equivalent to plane_blocks_per_line * as there will be at minimum one line for lines configuration . This * is a work around for FIFO underruns observed with resolutions like * 4 k 60 Hz in single channel DRAM configurations . * * As per the Bspec 49325 , if the ddb allocation can hold at least * one plane_blocks_per_line , we should have selected method2 in * the above logic . Assuming that modern versions have enough dbuf * and method2 guarantees blocks equivalent to at least 1 line , * select the blocks as plane_blocks_per_line . * * TODO : Revisit the logic when we have better understanding on DRAM * channels ' impact on the level 0 memory latency and the relevant * wm calculations . if (skl_wm_has_lines(display, level))if (DISPLAY_VER(display) == 9 ) {/* Display WA #1125: skl,bxt,kbl */ if (level == 0 && wp->rc_surface)/* Display WA #1126: skl,bxt,kbl */ if (level >= 1 && level <= 7 ) {if (wp->y_tiled) {else {/* * Make sure result blocks for higher latency levels are * at least as high as level below the current level . * Assumption in DDB algorithm optimization for special * cases . Also covers Display WA # 1125 for RC . if (result_prev->blocks > blocks)if (DISPLAY_VER(display) >= 11 ) {if (wp->y_tiled) {int extra_lines;if (lines % wp->y_min_scanlines == 0 )else 2 -else {10 );if (!skl_wm_has_lines(display, level))0 ;if (lines > skl_wm_max_lines(display)) {/* reject it */ return ;/* * If lines is valid , assume we can use this watermark level * for now . We ' ll come back and disable it after we calculate the * DDB allocation if it turns out we don ' t actually have enough * blocks to satisfy it . /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */ 1 ;true ;if (DISPLAY_VER(display) < 12 && display->sagv.block_time_us)static void const struct intel_crtc_state *crtc_state,struct intel_plane *plane,const struct skl_wm_params *wm_params,struct skl_wm_level *levels)struct intel_display *display = to_intel_display(crtc_state);struct skl_wm_level *result_prev = &levels[0 ];int level;for (level = 0 ; level < display->wm.num_levels; level++) {struct skl_wm_level *result = &levels[level];unsigned int latency = skl_wm_latency(display, level, wm_params);static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,struct intel_plane *plane,const struct skl_wm_params *wm_params,struct skl_plane_wm *plane_wm)struct intel_display *display = to_intel_display(crtc_state);struct skl_wm_level *sagv_wm = &plane_wm->sagv.wm0;struct skl_wm_level *levels = plane_wm->wm;unsigned int latency = 0 ;if (display->sagv.block_time_us)0 , wm_params);0 , latency,0 ],static void skl_compute_transition_wm(struct intel_display *display,struct skl_wm_level *trans_wm,const struct skl_wm_level *wm0,const struct skl_wm_params *wp)/* Transition WM don't make any sense if ipc is disabled */ if (!skl_watermark_ipc_enabled(display))return ;/* * WaDisableTWM : skl , kbl , cfl , bxt * Transition WM are not recommended by HW team for GEN9 if (DISPLAY_VER(display) == 9 )return ;if (DISPLAY_VER(display) >= 11 )4 ;else 14 ;/* Display WA #1140: glk,cnl */ if (DISPLAY_VER(display) == 10 )0 ;else 10 ; /* This is configurable amount */ /* * The spec asks for Selected Result Blocks for wm0 ( the real value ) , * not Result Blocks ( the integer value ) . Pay attention to the capital * letters . The value wm_l0 - > blocks is actually Result Blocks , but * since Result Blocks is the ceiling of Selected Result Blocks plus 1 , * and since we later will have to get the ceiling of the sum in the * transition watermarks calculation , we can just pretend Selected * Result Blocks is Result Blocks minus 1 and it should work for the * current platforms . 1 ;if (wp->y_tiled) {2 , wp->y_tile_minimum);else {/* * Just assume we can enable the transition watermark . After * computing the DDB we ' ll come back and disable it if that * assumption turns out to be false . 1 );true ;static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,const struct intel_plane_state *plane_state,struct intel_plane *plane, int color_plane)struct intel_display *display = to_intel_display(crtc_state);struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];struct skl_wm_params wm_params;int ret;if (ret)return ret;0 ], &wm_params);if (DISPLAY_VER(display) >= 12 ) {return 0 ;static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,const struct intel_plane_state *plane_state,struct intel_plane *plane)struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];struct skl_wm_params wm_params;int ret;true ;/* uv plane watermarks must also be validated for NV12/Planar */ 1 );if (ret)return ret;return 0 ;static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,const struct intel_plane_state *plane_state)struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);enum plane_id plane_id = plane->id;struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];const struct drm_framebuffer *fb = plane_state->hw.fb;int ret;0 , sizeof (*wm));if (!intel_wm_plane_visible(crtc_state, plane_state))return 0 ;0 );if (ret)return ret;if (fb->format->is_yuv && fb->format->num_planes > 1 ) {if (ret)return ret;return 0 ;static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,const struct intel_plane_state *plane_state)struct intel_display *display = to_intel_display(plane_state);struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);enum plane_id plane_id = plane->id;struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];int ret;/* Watermarks calculated on UV plane */ if (plane_state->is_y_plane)return 0 ;0 , sizeof (*wm));if (plane_state->planar_linked_plane) {const struct drm_framebuffer *fb = plane_state->hw.fb;1 );0 );if (ret)return ret;1 );if (ret)return ret;else if (intel_wm_plane_visible(crtc_state, plane_state)) {0 );if (ret)return ret;return 0 ;static int const struct intel_crtc_state *crtc_state)struct intel_display *display = to_intel_display(crtc_state);struct intel_atomic_state *state =const struct intel_cdclk_state *cdclk_state;if (IS_ERR(cdclk_state)) {return 1 ;return min(1 , DIV_ROUND_UP(crtc_state->pixel_rate,2 * intel_cdclk_logical(cdclk_state)));static int const struct intel_crtc_state *crtc_state)struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);const struct intel_crtc_scaler_state *scaler_state =int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,int num_scaler_users = hweight32(scaler_state->scaler_users);int chroma_downscaling_factor =2 : 1 ;0 ;if (!crtc_state->dsc.compression_enable ||return dsc_prefill_latency;15 * linetime * chroma_downscaling_factor, 10 );for (int i = 0 ; i < num_scaler_users; i++) {1000 , mul_u32_u32(scaler_state->scalers[i].hscale, 1000 ) >> 16 );1000 , mul_u32_u32(scaler_state->scalers[i].vscale, 1000 ) >> 16 );1000000 );return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, dsc_prefill_latency);static int const struct intel_crtc_state *crtc_state)const struct intel_crtc_scaler_state *scaler_state =int num_scaler_users = hweight32(scaler_state->scaler_users);int scaler_prefill_latency = 0 ;int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,if (!num_scaler_users)return scaler_prefill_latency;4 * linetime;if (num_scaler_users > 1 ) {1000 , mul_u32_u32(scaler_state->scalers[0 ].hscale, 1000 ) >> 16 );1000 , mul_u32_u32(scaler_state->scalers[0 ].vscale, 1000 ) >> 16 );int chroma_downscaling_factor =2 : 1 ;int latency;4 * linetime * hscale_k * vscale_k *1000000 );return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, scaler_prefill_latency);static bool const struct intel_crtc_state *crtc_state,int wm0_lines, int latency)const struct drm_display_mode *adjusted_mode =return crtc_state->framestart_delay +static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);enum plane_id plane_id;int wm0_lines = 0 ;const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];/* FIXME what about !skl_wm_has_lines() platforms? */ int , wm0_lines, wm->wm[0 ].lines);return wm0_lines;static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state,int wm0_lines)struct intel_display *display = to_intel_display(crtc_state);int level;for (level = display->wm.num_levels - 1 ; level >= 0 ; level--) {int latency;/* FIXME should we care about the latency w/a's? */ if (latency == 0 )continue ;/* FIXME is it correct to use 0 latency for wm0 here? */ if (level == 0 )0 ;if (!skl_is_vblank_too_short(crtc_state, wm0_lines, latency))return level;return -EINVAL;static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)struct intel_display *display = to_intel_display(crtc_state);struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);int wm0_lines, level;if (!crtc_state->hw.active)return 0 ;if (level < 0 )return level;/* * PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_ * * based on whether we ' re limited by the vblank duration . 1 ;for (level++; level < display->wm.num_levels; level++) {enum plane_id plane_id;struct skl_plane_wm *wm =/* * FIXME just clear enable or flag the entire * thing as bad via min_ddb_alloc = U16_MAX ? false ;false ;if (DISPLAY_VER(display) >= 12 &&enum plane_id plane_id;struct skl_plane_wm *wm =false ;false ;return 0 ;static int skl_build_pipe_wm(struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_display *display = to_intel_display(crtc);struct intel_crtc_state *crtc_state =const struct intel_plane_state *plane_state;struct intel_plane *plane;int ret, i;/* * FIXME should perhaps check { old , new } _ plane_crtc - > hw . crtc * instead but we don ' t populate that correctly for NV12 Y * planes so for now hack this . if (plane->pipe != crtc->pipe)continue ;if (DISPLAY_VER(display) >= 11 )else if (ret)return ret;return skl_wm_check_vblank(crtc_state);static bool skl_wm_level_equals(const struct skl_wm_level *l1,const struct skl_wm_level *l2)return l1->enable == l2->enable &&static bool skl_plane_wm_equals(struct intel_display *display,const struct skl_plane_wm *wm1,const struct skl_plane_wm *wm2)int level;for (level = 0 ; level < display->wm.num_levels; level++) {/* * We don ' t check uv_wm as the hardware doesn ' t actually * use it . It only gets used for calculating the required * ddb allocation . if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]))return false ;return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm) &&static bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,const struct skl_ddb_entry *b)return a->start < b->end && b->start < a->end;static void skl_ddb_entry_union(struct skl_ddb_entry *a,const struct skl_ddb_entry *b)if (a->end && b->end) {else if (b->end) {bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,const struct skl_ddb_entry *entries,int num_entries, int ignore_idx)int i;for (i = 0 ; i < num_entries; i++) {if (i != ignore_idx &&return true ;return false ;static int struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_display *display = to_intel_display(state);const struct intel_crtc_state *old_crtc_state =struct intel_crtc_state *new_crtc_state =struct intel_plane *plane;struct intel_plane_state *plane_state;enum plane_id plane_id = plane->id;if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb[plane_id],continue ;if (new_crtc_state->do_async_flip) {"[PLANE:%d:%s] Can't change DDB during async flip\n" ,return -EINVAL;if (IS_ERR(plane_state))return PTR_ERR(plane_state);0 ;false ;return 0 ;static u8 intel_dbuf_enabled_slices(const struct intel_dbuf_state *dbuf_state)struct intel_display *display = to_intel_display(dbuf_state->base.state->base.dev);enum pipe pipe;/* * FIXME : For now we always enable slice S1 as per * the Bspec display initialization sequence . return enabled_slices;static int struct intel_atomic_state *state)struct intel_display *display = to_intel_display(state);const struct intel_dbuf_state *old_dbuf_state;struct intel_dbuf_state *new_dbuf_state = NULL;struct intel_crtc_state *new_crtc_state;struct intel_crtc *crtc;int ret, i;if (IS_ERR(new_dbuf_state))return PTR_ERR(new_dbuf_state);break ;if (!new_dbuf_state)return 0 ;if (old_dbuf_state->active_pipes != new_dbuf_state->active_pipes) {if (ret)return ret;if (HAS_MBUS_JOINING(display)) {if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {if (ret)return ret;enum pipe pipe = crtc->pipe;if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe])continue ;if (ret)return ret;if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices ||if (ret)return ret;"Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n" ,enum pipe pipe = crtc->pipe;if (old_dbuf_state->weight[pipe] == new_dbuf_state->weight[pipe])continue ;if (ret)return ret;if (ret)return ret;if (ret)return ret;if (ret)return ret;return 0 ;static char enast(bool enable)return enable ? '*' : ' ' ;static noinline_for_stack void struct intel_display *display,struct intel_plane *plane,const struct skl_plane_wm *old_wm,const struct skl_plane_wm *new_wm)"[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm" " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n" ,0 ].enable), enast(old_wm->wm[1 ].enable),2 ].enable), enast(old_wm->wm[3 ].enable),4 ].enable), enast(old_wm->wm[5 ].enable),6 ].enable), enast(old_wm->wm[7 ].enable),0 ].enable), enast(new_wm->wm[1 ].enable),2 ].enable), enast(new_wm->wm[3 ].enable),4 ].enable), enast(new_wm->wm[5 ].enable),6 ].enable), enast(new_wm->wm[7 ].enable),"[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d" " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n" ,0 ].ignore_lines), old_wm->wm[0 ].lines,1 ].ignore_lines), old_wm->wm[1 ].lines,2 ].ignore_lines), old_wm->wm[2 ].lines,3 ].ignore_lines), old_wm->wm[3 ].lines,4 ].ignore_lines), old_wm->wm[4 ].lines,5 ].ignore_lines), old_wm->wm[5 ].lines,6 ].ignore_lines), old_wm->wm[6 ].lines,7 ].ignore_lines), old_wm->wm[7 ].lines,0 ].ignore_lines), new_wm->wm[0 ].lines,1 ].ignore_lines), new_wm->wm[1 ].lines,2 ].ignore_lines), new_wm->wm[2 ].lines,3 ].ignore_lines), new_wm->wm[3 ].lines,4 ].ignore_lines), new_wm->wm[4 ].lines,5 ].ignore_lines), new_wm->wm[5 ].lines,6 ].ignore_lines), new_wm->wm[6 ].lines,7 ].ignore_lines), new_wm->wm[7 ].lines,"[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d" " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n" ,0 ].blocks, old_wm->wm[1 ].blocks,2 ].blocks, old_wm->wm[3 ].blocks,4 ].blocks, old_wm->wm[5 ].blocks,6 ].blocks, old_wm->wm[7 ].blocks,0 ].blocks, new_wm->wm[1 ].blocks,2 ].blocks, new_wm->wm[3 ].blocks,4 ].blocks, new_wm->wm[5 ].blocks,6 ].blocks, new_wm->wm[7 ].blocks,"[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d" " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n" ,0 ].min_ddb_alloc, old_wm->wm[1 ].min_ddb_alloc,2 ].min_ddb_alloc, old_wm->wm[3 ].min_ddb_alloc,4 ].min_ddb_alloc, old_wm->wm[5 ].min_ddb_alloc,6 ].min_ddb_alloc, old_wm->wm[7 ].min_ddb_alloc,0 ].min_ddb_alloc, new_wm->wm[1 ].min_ddb_alloc,2 ].min_ddb_alloc, new_wm->wm[3 ].min_ddb_alloc,4 ].min_ddb_alloc, new_wm->wm[5 ].min_ddb_alloc,6 ].min_ddb_alloc, new_wm->wm[7 ].min_ddb_alloc,static void struct intel_atomic_state *state)struct intel_display *display = to_intel_display(state);const struct intel_crtc_state *old_crtc_state;const struct intel_crtc_state *new_crtc_state;struct intel_plane *plane;struct intel_crtc *crtc;int i;if (!drm_debug_enabled(DRM_UT_KMS))return ;const struct skl_pipe_wm *old_pipe_wm, *new_pipe_wm;enum plane_id plane_id = plane->id;const struct skl_ddb_entry *old, *new ;new = &new_crtc_state->wm.skl.plane_ddb[plane_id];if (skl_ddb_entry_equal(old, new ))continue ;"[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n" ,new ->start, new ->end,new ));enum plane_id plane_id = plane->id;const struct skl_plane_wm *old_wm, *new_wm;if (skl_plane_wm_equals(display, old_wm, new_wm))continue ;static bool skl_plane_selected_wm_equals(struct intel_plane *plane,const struct skl_pipe_wm *old_pipe_wm,const struct skl_pipe_wm *new_pipe_wm)struct intel_display *display = to_intel_display(plane);int level;for (level = 0 ; level < display->wm.num_levels; level++) {/* * We don ' t check uv_wm as the hardware doesn ' t actually * use it . It only gets used for calculating the required * ddb allocation . if (!skl_wm_level_equals(skl_plane_wm_level(old_pipe_wm, plane->id, level),return false ;if (HAS_HW_SAGV_WM(display)) {const struct skl_plane_wm *old_wm = &old_pipe_wm->planes[plane->id];const struct skl_plane_wm *new_wm = &new_pipe_wm->planes[plane->id];if (!skl_wm_level_equals(&old_wm->sagv.wm0, &new_wm->sagv.wm0) ||return false ;return skl_wm_level_equals(skl_plane_trans_wm(old_pipe_wm, plane->id),/* * To make sure the cursor watermark registers are always consistent * with our computed state the following scenario needs special * treatment : * * 1 . enable cursor * 2 . move cursor entirely offscreen * 3 . disable cursor * * Step 2 . does call . disable_plane ( ) but does not zero the watermarks * ( since we consider an offscreen cursor still active for the purposes * of watermarks ) . Step 3 . would not normally call . disable_plane ( ) * because the actual plane visibility isn ' t changing , and we don ' t * deallocate the cursor ddb until the pipe gets disabled . So we must * force step 3 . to call . disable_plane ( ) to update the watermark * registers properly . * * Other planes do not suffer from this issues as their watermarks are * calculated based on the actual plane visibility . The only time this * can trigger for the other planes is during the initial readout as the * default value of the watermarks registers is not zero . static int skl_wm_add_affected_planes(struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_display *display = to_intel_display(state);const struct intel_crtc_state *old_crtc_state =struct intel_crtc_state *new_crtc_state =struct intel_plane *plane;struct intel_plane_state *plane_state;enum plane_id plane_id = plane->id;/* * Force a full wm update for every plane on modeset . * Required because the reset value of the wm registers * is non - zero , whereas we want all disabled planes to * have zero watermarks . So if we turn off the relevant * power well the hardware state will go out of sync * with the software state . if (!intel_crtc_needs_modeset(new_crtc_state) &&continue ;if (new_crtc_state->do_async_flip) {"[PLANE:%d:%s] Can't change watermarks during async flip\n" ,return -EINVAL;if (IS_ERR(plane_state))return PTR_ERR(plane_state);0 ;false ;return 0 ;static int pkgc_max_linetime(struct intel_atomic_state *state)struct intel_display *display = to_intel_display(state);const struct intel_crtc_state *crtc_state;struct intel_crtc *crtc;int i, max_linetime;/* * Apparenty the hardware uses WM_LINETIME internally for * this stuff , compute everything based on that . 8 );0 ;if (display->pkgc.disable[crtc->pipe])return 0 ;return max_linetime;void struct intel_atomic_state *state)struct intel_display *display = to_intel_display(state);int max_linetime, latency, added_wake_time = 0 ;if (DISPLAY_VER(display) < 20 )return ;1 );/* FIXME runtime changes to enable_flipq are racy */ if (display->params.enable_flipq)/* * Wa_22020432604 * " PKG_C_LATENCY Added Wake Time field is not working " if (latency && IS_DISPLAY_VER(display, 20 , 30 )) {0 ;if (max_linetime == 0 || latency == 0 ) {0 ;else {/* * Wa_22020299601 * " Increase the latency programmed in PKG_C_LATENCY Pkg C Latency to be a * multiple of the pipeline time from WM_LINETIME " static int struct intel_atomic_state *state)struct intel_display *display = to_intel_display(state);struct intel_crtc *crtc;struct intel_crtc_state __maybe_unused *new_crtc_state;int ret, i;if (ret)return ret;if (ret)return ret;/* * skl_compute_ddb ( ) will have adjusted the final watermarks * based on how much ddb is available . Now we can actually * check if the final watermarks changed . struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;/* * We store use_sagv_wm in the crtc state rather than relying on * that bw state since we have no convenient way to get at the * latter from the plane commit hooks ( especially in the legacy * cursor case ) . * * drm_atomic_check_only ( ) gets upset if we pull more crtcs * into the state , so we have to calculate this based on the * individual intel_crtc_can_enable_sagv ( ) rather than * the overall intel_bw_can_enable_sagv ( ) . Otherwise the * crtcs not included in the commit would not switch to the * SAGV watermarks when we are about to enable SAGV , and that * would lead to underruns . This does mean extra power draw * when only a subset of the crtcs are blocking SAGV as the * other crtcs can ' t be allowed to use the more optimal * normal ( ie . non - SAGV ) watermarks . 12 &&if (ret)return ret;return 0 ;static void skl_wm_level_from_reg_val(struct intel_display *display,struct skl_wm_level *level)30 ?0 ;static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,struct skl_pipe_wm *out)struct intel_display *display = to_intel_display(crtc);enum pipe pipe = crtc->pipe;enum plane_id plane_id;int level;struct skl_plane_wm *wm = &out->planes[plane_id];for (level = 0 ; level < display->wm.num_levels; level++) {if (plane_id != PLANE_CURSOR)else if (plane_id != PLANE_CURSOR)else if (HAS_HW_SAGV_WM(display)) {if (plane_id != PLANE_CURSOR)else if (plane_id != PLANE_CURSOR)else else if (DISPLAY_VER(display) >= 12 ) {0 ];static void skl_wm_get_hw_state(struct intel_display *display)struct intel_dbuf_state *dbuf_state =struct intel_crtc *crtc;if (HAS_MBUS_JOINING(display))0 ;struct intel_crtc_state *crtc_state =enum pipe pipe = crtc->pipe;unsigned int mbus_offset;enum plane_id plane_id;0 ,sizeof (crtc_state->wm.skl.optimal));if (crtc_state->hw.active) {0 , sizeof (dbuf_state->ddb[pipe]));struct skl_ddb_entry *ddb =struct skl_ddb_entry *ddb_y =if (!crtc_state->hw.active)continue ;/* * Used for checking overlaps , so we need absolute * offsets instead of MBUS relative offsets . /* The slices actually used by the planes on the pipe */ "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x, mbus joined: %s\n" ,bool skl_watermark_ipc_enabled(struct intel_display *display)return display->wm.ipc_enabled;void skl_watermark_ipc_update(struct intel_display *display)if (!HAS_IPC(display))return ;0 );static bool skl_watermark_ipc_can_enable(struct intel_display *display)/* Display WA #0477 WaDisableIPC: skl */ if (display->platform.skylake)return false ;/* Display WA #1141: SKL:all KBL:all CFL */ if (display->platform.kabylake ||const struct dram_info *dram_info = intel_dram_info(display->drm);return dram_info->symmetric_memory;return true ;void skl_watermark_ipc_init(struct intel_display *display)if (!HAS_IPC(display))return ;static void struct intel_display *display,int num_levels, int read_latency)const struct dram_info *dram_info = intel_dram_info(display->drm);int i, level;/* * If a level n ( n > 1 ) has a 0 us latency , all levels m ( m > = n ) * need to be disabled . We make sure to sanitize the values out * of the punit to satisfy this requirement . for (level = 1 ; level < num_levels; level++) {if (wm[level] == 0 ) {for (i = level + 1 ; i < num_levels; i++)0 ;break ;/* * WaWmMemoryReadLatency * * punit doesn ' t take into account the read latency so we need * to add proper adjustment to each valid level we retrieve * from the punit when level 0 response data is 0 us . if (wm[0 ] == 0 ) {for (level = 0 ; level < num_levels; level++)/* * WA Level - 0 adjustment for 16 GB DIMMs : SKL + * If we could not get dimm info enable this WA to prevent from * any underrun . If not able to get Dimm info assume 16 GB dimm * to avoid any underrun . if (!display->platform.dg2 && dram_info->wm_lv_0_adjust_needed)0 ] += 1 ;static void mtl_read_wm_latency(struct intel_display *display, u16 wm[])int num_levels = display->wm.num_levels;0 ] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);1 ] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);2 ] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);3 ] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);4 ] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);5 ] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);6 );static void skl_read_wm_latency(struct intel_display *display, u16 wm[])int num_levels = display->wm.num_levels;int read_latency = DISPLAY_VER(display) >= 12 ? 3 : 2 ;int mult = display->platform.dg2 ? 2 : 1 ;int ret;/* read the first set of memory latencies[0:3] */ 0 ; /* data0 to be programmed to 0 for first set */ if (ret) {"SKL Mailbox read error = %d\n" , ret);return ;0 ] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult;1 ] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult;2 ] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult;3 ] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult;/* read the second set of memory latencies[4:7] */ 1 ; /* data0 to be programmed to 1 for second set */ if (ret) {"SKL Mailbox read error = %d\n" , ret);return ;4 ] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult;5 ] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult;6 ] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult;7 ] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult;static void skl_setup_wm_latency(struct intel_display *display)if (HAS_HW_SAGV_WM(display))6 ;else 8 ;if (DISPLAY_VER(display) >= 14 )else "Gen9 Plane" , display->wm.skl_latency);static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj)struct intel_dbuf_state *dbuf_state;sizeof (*dbuf_state), GFP_KERNEL);if (!dbuf_state)return NULL;return &dbuf_state->base;static void intel_dbuf_destroy_state(struct intel_global_obj *obj,struct intel_global_state *state)static const struct intel_global_state_funcs intel_dbuf_funcs = {struct intel_dbuf_state *struct intel_atomic_state *state)struct intel_display *display = to_intel_display(state);struct intel_global_state *dbuf_state;if (IS_ERR(dbuf_state))return ERR_CAST(dbuf_state);return to_intel_dbuf_state(dbuf_state);int intel_dbuf_init(struct intel_display *display)struct intel_dbuf_state *dbuf_state;sizeof (*dbuf_state), GFP_KERNEL);if (!dbuf_state)return -ENOMEM;return 0 ;static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)switch (pipe) {case PIPE_A:case PIPE_D:break ;case PIPE_B:case PIPE_C:break ;default : /* to suppress compiler warning */ return false ;return is_power_of_2(active_pipes);static u32 pipe_mbus_dbox_ctl(const struct intel_crtc *crtc,const struct intel_dbuf_state *dbuf_state)struct intel_display *display = to_intel_display(crtc);0 ;if (DISPLAY_VER(display) >= 14 )2 );if (DISPLAY_VER(display) >= 12 ) {16 );1 );if (DISPLAY_VER(display) >= 14 )12 ) : MBUS_DBOX_A_CREDIT(8 );else if (display->platform.alderlake_p)/* Wa_22010947358:adl-p */ 6 ) : MBUS_DBOX_A_CREDIT(4 );else 2 );if (DISPLAY_VER(display) >= 14 ) {0 xA);else if (display->platform.alderlake_p) {2 );8 );else if (DISPLAY_VER(display) >= 12 ) {2 );12 );else {1 );8 );if (DISPLAY_VERx100(display) == 1400 ) {if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe, dbuf_state->active_pipes))else return val;static void pipe_mbus_dbox_ctl_update(struct intel_display *display,const struct intel_dbuf_state *dbuf_state)struct intel_crtc *crtc;static void intel_mbus_dbox_update(struct intel_atomic_state *state)struct intel_display *display = to_intel_display(state);const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;if (DISPLAY_VER(display) < 11 )return ;if (!new_dbuf_state ||return ;int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,int ratio)struct intel_dbuf_state *dbuf_state;if (IS_ERR(dbuf_state))return PTR_ERR(dbuf_state);return intel_atomic_lock_global_state(&dbuf_state->base);void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,int ratio, bool joined_mbus)enum dbuf_slice slice;if (!HAS_MBUS_JOINING(display))return ;if (DISPLAY_VER(display) >= 20 )1 ));if (joined_mbus)2 ;"Updating dbuf ratio to %d (mbus joined: %s)\n" ,1 ));static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state)struct intel_display *display = to_intel_display(state);const struct intel_dbuf_state *old_dbuf_state =const struct intel_dbuf_state *new_dbuf_state =int mdclk_cdclk_ratio;if (intel_cdclk_is_decreasing_later(state)) {/* cdclk/mdclk will be changed later by intel_set_cdclk_post_plane_update() */ else {/* cdclk/mdclk already changed by intel_set_cdclk_pre_plane_update() */ static enum pipe intel_mbus_joined_pipe(struct intel_atomic_state *state,const struct intel_dbuf_state *dbuf_state)struct intel_display *display = to_intel_display(state);enum pipe pipe = ffs(dbuf_state->active_pipes) - 1 ;const struct intel_crtc_state *new_crtc_state;struct intel_crtc *crtc;if (new_crtc_state && !intel_crtc_needs_modeset(new_crtc_state))return pipe;else return INVALID_PIPE;static void mbus_ctl_join_update(struct intel_display *display,const struct intel_dbuf_state *dbuf_state,enum pipe pipe)if (dbuf_state->joined_mbus)else if (pipe != INVALID_PIPE)else static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state,enum pipe pipe)struct intel_display *display = to_intel_display(state);const struct intel_dbuf_state *old_dbuf_state =const struct intel_dbuf_state *new_dbuf_state ="Changing mbus joined: %s -> %s (pipe: %c)\n" ,'*' );void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state)const struct intel_dbuf_state *new_dbuf_state =const struct intel_dbuf_state *old_dbuf_state =if (!new_dbuf_state)return ;if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus) {enum pipe pipe = intel_mbus_joined_pipe(state, new_dbuf_state);void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state)struct intel_display *display = to_intel_display(state);const struct intel_dbuf_state *new_dbuf_state =const struct intel_dbuf_state *old_dbuf_state =if (!new_dbuf_state)return ;if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus) {enum pipe pipe = intel_mbus_joined_pipe(state, old_dbuf_state);if (pipe != INVALID_PIPE) {struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);else if (old_dbuf_state->joined_mbus == new_dbuf_state->joined_mbus &&void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)struct intel_display *display = to_intel_display(state);const struct intel_dbuf_state *new_dbuf_state =const struct intel_dbuf_state *old_dbuf_state =if (!new_dbuf_state)return ;if (old_slices == new_slices)return ;void intel_dbuf_post_plane_update(struct intel_atomic_state *state)struct intel_display *display = to_intel_display(state);const struct intel_dbuf_state *new_dbuf_state =const struct intel_dbuf_state *old_dbuf_state =if (!new_dbuf_state)return ;if (old_slices == new_slices)return ;int intel_dbuf_num_enabled_slices(const struct intel_dbuf_state *dbuf_state)return hweight8(dbuf_state->enabled_slices);int intel_dbuf_num_active_pipes(const struct intel_dbuf_state *dbuf_state)return hweight8(dbuf_state->active_pipes);bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state)struct intel_display *display = to_intel_display(state);const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;if (new_dbuf_state &&return true ;if (DISPLAY_VER(display) < 30 ) {if (new_dbuf_state &&return true ;return false ;static void skl_mbus_sanitize(struct intel_display *display)struct intel_dbuf_state *dbuf_state =if (!HAS_MBUS_JOINING(display))return ;if (!dbuf_state->joined_mbus ||return ;"Disabling redundant MBUS joining (active pipes 0x%x)\n" ,false ;static bool skl_dbuf_is_misconfigured(struct intel_display *display)const struct intel_dbuf_state *dbuf_state =struct skl_ddb_entry entries[I915_MAX_PIPES] = {};struct intel_crtc *crtc;const struct intel_crtc_state *crtc_state =const struct intel_crtc_state *crtc_state =if (dbuf_state->slices[crtc->pipe] & ~slices)return true ;if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.ddb, entries,return true ;return false ;static void skl_dbuf_sanitize(struct intel_display *display)struct intel_crtc *crtc;/* * On TGL / RKL ( at least ) the BIOS likes to assign the planes * to the wrong DBUF slices . This will cause an infinite loop * in skl_commit_modeset_enables ( ) as it can ' t find a way to * transition between the old bogus DBUF layout to the new * proper DBUF layout without DBUF allocation overlaps between * the planes ( which cannot be allowed or else the hardware * may hang ) . If we detect a bogus DBUF layout just turn off * all the planes so that skl_commit_modeset_enables ( ) can * simply ignore them . if (!skl_dbuf_is_misconfigured(display))return ;"BIOS has misprogrammed the DBUF, disabling all planes\n" );struct intel_plane *plane = to_intel_plane(crtc->base.primary);const struct intel_plane_state *plane_state =struct intel_crtc_state *crtc_state =if (plane_state->uapi.visible)0 );0 , sizeof (crtc_state->wm.skl.ddb));static void skl_wm_sanitize(struct intel_display *display)void skl_wm_crtc_disable_noatomic(struct intel_crtc *crtc)struct intel_display *display = to_intel_display(crtc);struct intel_crtc_state *crtc_state =struct intel_dbuf_state *dbuf_state =enum pipe pipe = crtc->pipe;if (DISPLAY_VER(display) < 9 )return ;0 ;0 ;0 , sizeof (dbuf_state->ddb[pipe]));0 , sizeof (crtc_state->wm.skl.ddb));void skl_wm_plane_disable_noatomic(struct intel_crtc *crtc,struct intel_plane *plane)struct intel_display *display = to_intel_display(crtc);struct intel_crtc_state *crtc_state =if (DISPLAY_VER(display) < 9 )return ;0 , 0 );0 , 0 );0 ;0 ;0 ,sizeof (crtc_state->wm.skl.raw.planes[plane->id]));0 ,sizeof (crtc_state->wm.skl.optimal.planes[plane->id]));void intel_wm_state_verify(struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_display *display = to_intel_display(state);const struct intel_crtc_state *new_crtc_state =struct skl_hw_state {struct skl_ddb_entry ddb[I915_MAX_PLANES];struct skl_ddb_entry ddb_y[I915_MAX_PLANES];struct skl_pipe_wm wm;const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;struct intel_plane *plane;int level;if (DISPLAY_VER(display) < 9 || !new_crtc_state->hw.active)return ;sizeof (*hw), GFP_KERNEL);if (!hw)return ;if (DISPLAY_VER(display) >= 11 &&"mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n" ,const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;const struct skl_wm_level *hw_wm_level, *sw_wm_level;/* Watermarks */ for (level = 0 ; level < display->wm.num_levels; level++) {if (skl_wm_level_equals(hw_wm_level, sw_wm_level))continue ;"[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" ,if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {"[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" ,if (HAS_HW_SAGV_WM(display) &&"[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" ,if (HAS_HW_SAGV_WM(display) &&"[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" ,/* DDB */ if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {"[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n" ,static const struct intel_wm_funcs skl_wm_funcs = {void skl_wm_init(struct intel_display *display)static int skl_watermark_ipc_status_show(struct seq_file *m, void *data)struct intel_display *display = m->private ;"Isochronous Priority Control: %s\n" ,return 0 ;static int skl_watermark_ipc_status_open(struct inode *inode, struct file *file)struct intel_display *display = inode->i_private;return single_open(file, skl_watermark_ipc_status_show, display);static ssize_t skl_watermark_ipc_status_write(struct file *file,const char __user *ubuf,struct seq_file *m = file->private_data;struct intel_display *display = m->private ;bool enable;int ret;if (ret < 0 )return ret;if (!skl_watermark_ipc_enabled(display) && enable)"Enabling IPC: WM will be proper only after next commit\n" );return len;static const struct file_operations skl_watermark_ipc_status_fops = {static int intel_sagv_status_show(struct seq_file *m, void *unused)struct intel_display *display = m->private ;static const char * const sagv_status[] = {"unknown" ,"disabled" ,"enabled" ,"not controlled" ,"SAGV available: %s\n" , str_yes_no(intel_has_sagv(display)));"SAGV modparam: %s\n" ,"SAGV status: %s\n" , sagv_status[display->sagv.status]);"SAGV block time: %d usec\n" , display->sagv.block_time_us);return 0 ;void skl_watermark_debugfs_register(struct intel_display *display)struct drm_minor *minor = display->drm->primary;if (HAS_IPC(display))"i915_ipc_status" , 0644 , minor->debugfs_root,if (HAS_SAGV(display))"i915_sagv_status" , 0444 , minor->debugfs_root,unsigned int skl_watermark_max_latency(struct intel_display *display, int initial_wm_level)int level;for (level = display->wm.num_levels - 1 ; level >= initial_wm_level; level--) {unsigned int latency = skl_wm_latency(display, level, NULL);if (latency)return latency;return 0 ;
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