/* * Copyright © 2008 - 2015 Intel Corporation * * Permission is hereby granted , free of charge , to any person obtaining a * copy of this software and associated documentation files ( the " Software " ) , * to deal in the Software without restriction , including without limitation * the rights to use , copy , modify , merge , publish , distribute , sublicense , * and / or sell copies of the Software , and to permit persons to whom the * Software is furnished to do so , subject to the following conditions : * * The above copyright notice and this permission notice ( including the next * paragraph ) shall be included in all copies or substantial portions of the * Software . * * THE SOFTWARE IS PROVIDED " AS IS " , WITHOUT WARRANTY OF ANY KIND , EXPRESS OR * IMPLIED , INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY , * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT . IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM , DAMAGES OR OTHER * LIABILITY , WHETHER IN AN ACTION OF CONTRACT , TORT OR OTHERWISE , ARISING * FROM , OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE . #include <linux/debugfs.h>#include <drm/display/drm_dp_helper.h>#include <drm/drm_print.h>#include "i915_utils.h" #include "intel_display_core.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dp_link_training.h" #include "intel_encoder.h" #include "intel_hotplug.h" #include "intel_panel.h" #define LT_MSG_PREFIX "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] " #define LT_MSG_ARGS(_intel_dp, _dp_phy) (_intel_dp)->attached_connector->base.base.id, \#define lt_dbg(_intel_dp, _dp_phy, _format, ...) \## __VA_ARGS__)#define lt_err(_intel_dp, _dp_phy, _format, ...) do { \if (intel_digital_port_connected(&dp_to_dig_port(_intel_dp)->base)) \## __VA_ARGS__); \else \"Sink disconnected: " _format, ## __VA_ARGS__); \while (0 )#define MAX_SEQ_TRAIN_FAILURES 2 static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp)0 , sizeof (intel_dp->lttpr_common_caps));static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp)0 ;static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,enum drm_dp_phy dp_phy)return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1];static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,const u8 dpcd[DP_RECEIVER_CAP_SIZE],enum drm_dp_phy dp_phy)if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0 ) {"failed to read the PHY caps\n" );return ;"PHY capabilities: %*ph\n" ,int )sizeof (intel_dp->lttpr_phy_caps[0 ]),static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp,const u8 dpcd[DP_RECEIVER_CAP_SIZE])int ret;if (ret < 0 )goto reset_caps;"LTTPR common capabilities: %*ph\n" ,int )sizeof (intel_dp->lttpr_common_caps),/* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */ if (intel_dp->lttpr_common_caps[0 ] < 0 x14)goto reset_caps;return true ;return false ;static bool struct intel_dp *intel_dp, bool enable)return true ;bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp)return intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE -/* * Read the LTTPR common capabilities and switch the LTTPR PHYs to * non - transparent mode if this is supported . Preserve the * transparent / non - transparent mode on an active link . * * Return the number of detected LTTPRs in non - transparent mode or 0 if the * LTTPRs are in transparent mode or the detection failed . static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])int lttpr_count;int ret;if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd))return 0 ;/* * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are * detected as this breaks link training at least on the Dell WD19TB * dock . if (lttpr_count == 0 )return 0 ;/* * Don ' t change the mode on an active link , to prevent a loss of link * synchronization . See DP Standard v2 . 0 3 . 6 . 7 . about the LTTPR * resetting its internal state when the mode is changed from * non - transparent to transparent . if (intel_dp->link.active) {if (lttpr_count < 0 || intel_dp_lttpr_transparent_mode_enabled(intel_dp))goto out_reset_lttpr_count;return lttpr_count;if (ret) {"Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n" );true );goto out_reset_lttpr_count;false );return lttpr_count;return 0 ;static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])int lttpr_count;int i;for (i = 0 ; i < lttpr_count; i++) {return lttpr_count;int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE])struct intel_display *display = to_intel_display(intel_dp);if (intel_dp_is_edp(intel_dp))return 0 ;/* * Detecting LTTPRs must be avoided on platforms with an AUX timeout * period < 3 . 2 ms . ( see DP Standard v2 . 0 , 2 . 11 . 2 , 3 . 6 . 6 . 1 ) . if (DISPLAY_VER(display) >= 10 && !display->platform.geminilake)if (drm_dp_dpcd_probe(&intel_dp->aux,return -EIO;if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))return -EIO;return 0 ;/** * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps , init the LTTPR link training mode * @ intel_dp : Intel DP struct * * Read the LTTPR common and DPRX capabilities and switch to non - transparent * link training mode if any is detected and read the PHY capabilities for all * detected LTTPRs . In case of an LTTPR detection error or if the number of * LTTPRs is more than is supported ( 8 ) , fall back to the no - LTTPR , * transparent mode link training mode . * * Returns : * > 0 if LTTPRs were detected and the non - transparent LT mode was set . The * DPRX capabilities are read out . * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a * detection failure and the transparent LT mode was set . The DPRX * capabilities are read out . * < 0 Reading out the DPRX capabilities failed . int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)struct intel_display *display = to_intel_display(intel_dp);int lttpr_count = 0 ;/* * Detecting LTTPRs must be avoided on platforms with an AUX timeout * period < 3 . 2 ms . ( see DP Standard v2 . 0 , 2 . 11 . 2 , 3 . 6 . 6 . 1 ) . if (!intel_dp_is_edp(intel_dp) &&10 && !display->platform.geminilake)) {int err = intel_dp_read_dprx_caps(intel_dp, dpcd);if (err != 0 )return err;/* * The DPTX shall read the DPRX caps after LTTPR detection , so re - read * it here . if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {return -EIO;return lttpr_count;static u8 dp_voltage_max(u8 preemph)switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {case DP_TRAIN_PRE_EMPH_LEVEL_0:return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;case DP_TRAIN_PRE_EMPH_LEVEL_1:return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;case DP_TRAIN_PRE_EMPH_LEVEL_2:return DP_TRAIN_VOLTAGE_SWING_LEVEL_1;case DP_TRAIN_PRE_EMPH_LEVEL_3:default :return DP_TRAIN_VOLTAGE_SWING_LEVEL_0;static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp,enum drm_dp_phy dp_phy)const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps))return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;else return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp,enum drm_dp_phy dp_phy)const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps))return DP_TRAIN_PRE_EMPH_LEVEL_3;else return DP_TRAIN_PRE_EMPH_LEVEL_2;static bool struct intel_dp *intel_dp,enum drm_dp_phy dp_phy)struct intel_display *display = to_intel_display(intel_dp);int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);0 && dp_phy != DP_PHY_DPRX);return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1 );static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,enum drm_dp_phy dp_phy)struct intel_display *display = to_intel_display(intel_dp);/* * Get voltage_max from the DPTX_PHY ( source or LTTPR ) upstream from * the DPRX_PHY we train . if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))else 1 );return voltage_max;static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,enum drm_dp_phy dp_phy)struct intel_display *display = to_intel_display(intel_dp);/* * Get preemph_max from the DPTX_PHY ( source or LTTPR ) upstream from * the DPRX_PHY we train . if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))else 1 );return preemph_max;static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,enum drm_dp_phy dp_phy)struct intel_display *display = to_intel_display(intel_dp);return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) ||10 || display->platform.broxton;/* 128b/132b */ static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,enum drm_dp_phy dp_phy,const u8 link_status[DP_LINK_STATUS_SIZE],int lane)0 ;if (has_per_lane_signal_levels(intel_dp, dp_phy)) {1 );else {for (lane = 0 ; lane < crtc_state->lane_count; lane++)return tx_ffe;/* 8b/10b */ static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,enum drm_dp_phy dp_phy,const u8 link_status[DP_LINK_STATUS_SIZE],int lane)0 ;0 ;if (has_per_lane_signal_levels(intel_dp, dp_phy)) {1 );else {for (lane = 0 ; lane < crtc_state->lane_count; lane++) {if (p >= preemph_max)if (v >= voltage_max)return v | p;static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,enum drm_dp_phy dp_phy,const u8 link_status[DP_LINK_STATUS_SIZE],int lane)if (intel_dp_is_uhbr(crtc_state))return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state,else return intel_dp_get_lane_adjust_vswing_preemph(intel_dp, crtc_state,#define TRAIN_REQ_FMT "%d/%d/%d/%d" #define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \HIFT)#define TRAIN_REQ_VSWING_ARGS(link_status) \0 ), \1 ), \2 ), \3 )#define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \IS_SHIFT)#define TRAIN_REQ_PREEMPH_ARGS(link_status) \0 ), \1 ), \2 ), \3 )#define _TRAIN_REQ_TX_FFE_ARGS(link_status, lane) \#define TRAIN_REQ_TX_FFE_ARGS(link_status) \0 ), \1 ), \2 ), \3 )void struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,enum drm_dp_phy dp_phy,const u8 link_status[DP_LINK_STATUS_SIZE])int lane;if (intel_dp_is_uhbr(crtc_state)) {"128b/132b, lanes: %d, " "TX FFE request: " TRAIN_REQ_FMT "\n" ,else {"8b/10b, lanes: %d, " "vswing request: " TRAIN_REQ_FMT ", " "pre-emphasis request: " TRAIN_REQ_FMT "\n" ,for (lane = 0 ; lane < 4 ; lane++)static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp,enum drm_dp_phy dp_phy)return dp_phy == DP_PHY_DPRX ?static bool struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,enum drm_dp_phy dp_phy,int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);sizeof (intel_dp->train_set) + 1 ];int len;0 ] = dp_train_pat;/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 1 , intel_dp->train_set, crtc_state->lane_count);1 ;return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;static char dp_training_pattern_name(u8 train_pat)switch (train_pat) {case DP_TRAINING_PATTERN_1:case DP_TRAINING_PATTERN_2:case DP_TRAINING_PATTERN_3:return '0' + train_pat;case DP_TRAINING_PATTERN_4:return '4' ;default :return '?' ;void struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,enum drm_dp_phy dp_phy,if (train_pat != DP_TRAINING_PATTERN_DISABLE)"Using DP training pattern TPS%c\n" ,#define TRAIN_SET_FMT "%d%s/%d%s/%d%s/%d%s" #define _TRAIN_SET_VSWING_ARGS(train_set) \"(max)" : "" #define TRAIN_SET_VSWING_ARGS(train_set) \0 ]), \1 ]), \2 ]), \3 ])#define _TRAIN_SET_PREEMPH_ARGS(train_set) \"(max)" : "" #define TRAIN_SET_PREEMPH_ARGS(train_set) \0 ]), \1 ]), \2 ]), \3 ])#define _TRAIN_SET_TX_FFE_ARGS(train_set) \"" #define TRAIN_SET_TX_FFE_ARGS(train_set) \0 ]), \1 ]), \2 ]), \3 ])void intel_dp_set_signal_levels(struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,enum drm_dp_phy dp_phy)struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;if (intel_dp_is_uhbr(crtc_state)) {"128b/132b, lanes: %d, " "TX FFE presets: " TRAIN_SET_FMT "\n" ,else {"8b/10b, lanes: %d, " "vswing levels: " TRAIN_SET_FMT ", " "pre-emphasis levels: " TRAIN_SET_FMT "\n" ,if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))static bool struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,enum drm_dp_phy dp_phy,0 , sizeof (intel_dp->train_set));return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);static bool struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,enum drm_dp_phy dp_phy)int reg = dp_phy == DP_PHY_DPRX ?int ret;return ret == crtc_state->lane_count;/* 128b/132b */ static bool intel_dp_lane_max_tx_ffe_reached(u8 train_set_lane)return (train_set_lane & DP_TX_FFE_PRESET_VALUE_MASK) ==/* * 8 b / 10 b * * FIXME : The DP spec is very confusing here , also the Link CTS spec seems to * have self contradicting tests around this area . * * In lieu of better ideas let ' s just stop when we ' ve reached the max supported * vswing with its max pre - emphasis , which is either 2 + 1 or 3 + 0 depending on * whether vswing level 3 is supported or not . static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane)if ((train_set_lane & DP_TRAIN_MAX_SWING_REACHED) == 0 )return false ;if (v + p != 3 )return false ;return true ;static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state)int lane;for (lane = 0 ; lane < crtc_state->lane_count; lane++) {if (intel_dp_is_uhbr(crtc_state)) {if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane))return false ;else {if (!intel_dp_lane_max_vswing_reached(train_set_lane))return false ;return true ;void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr)2 ];0 ] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0 ;1 ] = drm_dp_is_uhbr_rate(link_rate) ?2 );static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state)/* * Currently , we set the MSA ignore bit based on vrr . in_range . * We can ' t really read that out during driver load since we don ' t have * the connector information read in yet . So if we do end up doing a * modeset during initial_commit ( ) we ' ll clear the MSA ignore bit . * GOP likely wouldn ' t have set this bit so after the initial commit , * if there are no modesets and we enable VRR mode seamlessly * ( without a full modeset ) , the MSA ignore bit might never get set . * * # TODO : Implement readout of vrr . in_range . * We need fastset support for setting the MSA ignore bit in DPCD , * especially on the first real commit when clearing the inherited flag . void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,int link_bw, int rate_select, int lane_count,bool enhanced_framing)if (enhanced_framing)if (link_bw) {/* DP and eDP v1.3 and earlier link bw set method. */ else {/* * eDP v1 . 4 and later link rate set method . * * eDP v1 . 4 x sinks shall ignore DP_LINK_RATE_SET if * DP_LINK_BW_SET is set . Avoid writing DP_LINK_BW_SET . * * eDP v1 . 5 sinks allow choosing either , and the last choice * shall be active . static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,,/* * Prepare link training by configuring the link parameters . On DDI platforms * also enable the port here . static bool struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state)if (intel_dp->prepare_link_retrain)/* * WaEdpLinkRateDataReload * * Parade PS8461E MUX ( used on various TGL + laptops ) needs * to snoop the link rates reported by the sink when we * use LINK_RATE_SET in order to operate in jitter cleaning * mode ( as opposed to redriver mode ) . Unfortunately it * loses track of the snooped link rates when powered down , * so we need to make it re - snoop often . Without this high * link rates are not stable . if (!link_bw) {"Reloading eDP link rates\n" );sizeof (sink_rates));if (link_bw)"Using LINK_BW_SET value %02x\n" ,else "Using LINK_RATE_SET value %02x\n" ,/* * Spec DP2 . 1 Section 3 . 5 . 2 . 16 * Prior to LT DPTX should set 128 b / 132 b DP Channel coding and then set link rate return true ;static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state,const u8 old_link_status[DP_LINK_STATUS_SIZE],const u8 new_link_status[DP_LINK_STATUS_SIZE])int lane;for (lane = 0 ; lane < crtc_state->lane_count; lane++) {new ;if (intel_dp_is_uhbr(crtc_state)) {new = drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane);else {new = drm_dp_get_adjust_request_voltage(new_link_status, lane) |if (old != new )return true ;return false ;void struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,const u8 link_status[DP_LINK_STATUS_SIZE])"ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n" ,0 ], link_status[1 ], link_status[2 ],3 ], link_status[4 ], link_status[5 ]);/* * Perform the link training clock recovery phase on the given DP PHY using * training pattern 1 . static bool struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,enum drm_dp_phy dp_phy)int voltage_tries, cr_tries, max_cr_tries;bool max_vswing_reached = false ;int delay_us;/* clock recovery */ if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,"Failed to enable link training\n" );return false ;/* * The DP 1 . 4 spec defines the max clock recovery retries value * as 10 but for pre - DP 1 . 4 devices we set a very tolerant * retry limit of 80 ( 4 voltage levels x 4 preemphasis levels x * x 5 identical voltage retries ) . Since the previous specs didn ' t * define a limit and created the possibility of an infinite loop * we want to prevent any sync from triggering that corner case . if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)10 ;else 80 ;1 ;for (cr_tries = 0 ; cr_tries < max_cr_tries; ++cr_tries) {if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,0 ) {"Failed to get link status\n" );return false ;if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {"Clock recovery OK\n" );return true ;if (voltage_tries == 5 ) {"Same voltage tried 5 times\n" );return false ;if (max_vswing_reached) {"Max Voltage Swing reached\n" );return false ;/* Update training set as requested by target */ if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {"Failed to update link training\n" );return false ;if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status))else 1 ;sizeof (link_status));if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))true ;"Failed clock recovery %d times, giving up!\n" ,return false ;/* * Pick Training Pattern Sequence ( TPS ) for channel equalization . 128 b / 132 b TPS2 * for UHBR + , TPS4 for HBR3 or for 1 . 4 devices that support it , TPS3 for HBR2 or * 1 . 2 devices that support it , TPS2 otherwise . static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,enum drm_dp_phy dp_phy)struct intel_display *display = to_intel_display(intel_dp);bool source_tps3, sink_tps3, source_tps4, sink_tps4;/* UHBR+ use separate 128b/132b TPS2 */ if (intel_dp_is_uhbr(crtc_state))return DP_TRAINING_PATTERN_2;/* * TPS4 support is mandatory for all downstream devices that * support HBR3 . There are no known eDP panels that support * TPS4 as of Feb 2018 as per VESA eDP_v1 . 4 b_E1 specification . * LTTPRs must support TPS4 . if (source_tps4 && sink_tps4) {return DP_TRAINING_PATTERN_4;else if (crtc_state->port_clock == 810000 ) {if (!source_tps4)"8.1 Gbps link rate without source TPS4 support\n" );if (!sink_tps4)"8.1 Gbps link rate without sink TPS4 support\n" );/* * TPS3 support is mandatory for downstream devices that * support HBR2 . However , not all sinks follow the spec . if (source_tps3 && sink_tps3) {return DP_TRAINING_PATTERN_3;else if (crtc_state->port_clock >= 540000 ) {if (!source_tps3)">=5.4/6.48 Gbps link rate without source TPS3 support\n" );if (!sink_tps3)">=5.4/6.48 Gbps link rate without sink TPS3 support\n" );return DP_TRAINING_PATTERN_2;/* * Perform the link training channel equalization phase on the given DP PHY * using one of training pattern 2 , 3 or 4 depending on the source and * sink capabilities . static bool struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,enum drm_dp_phy dp_phy)int tries;bool channel_eq = false ;int delay_us;/* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ if (training_pattern != DP_TRAINING_PATTERN_4)/* channel equalization */ if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,"Failed to start channel equalization\n" );return false ;for (tries = 0 ; tries < 5 ; tries++) {if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,0 ) {"Failed to get link status\n" );break ;/* Make sure clock is still ok */ if (!drm_dp_clock_recovery_ok(link_status,"Clock recovery check failed, cannot continue channel equalization\n" );break ;if (drm_dp_channel_eq_ok(link_status,true ;"Channel EQ done. DP Training successful\n" );break ;/* Update training set as requested by target */ if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {"Failed to update link training\n" );break ;/* Try 5 times, else fail and try at lower BW */ if (tries == 5 ) {"Channel equalization failed 5 times\n" );return channel_eq;static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp,enum drm_dp_phy dp_phy)int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1 ) == 1 ;static int struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state)int ret;if (ret != 1 ) {"Failed to read sink status\n" );return ret < 0 ? ret : -EIO;return sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION ? 1 : 0 ;/** * intel_dp_stop_link_train - stop link training * @ intel_dp : DP struct * @ crtc_state : state for CRTC attached to the encoder * * Stop the link training of the @ intel_dp port , disabling the training * pattern in the sink ' s DPCD , and disabling the test pattern symbol * generation on the port . * * What symbols are output on the port after this point is * platform specific : On DDI / VLV / CHV platforms it will be the idle pattern * with the pipe being disabled , on older platforms it ' s HW specific if / how an * idle pattern is generated , as the pipe is already enabled here for those . * * This function must be called after intel_dp_start_link_train ( ) . void intel_dp_stop_link_train(struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state)struct intel_display *display = to_intel_display(intel_dp);struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;true ;if (intel_dp_is_uhbr(crtc_state) &&0 , 500 )) {"128b/132b intra-hop not clearing\n" );if (!display->hotplug.ignore_long_hpd &&int delay_ms = intel_dp->link.seq_train_failures ? 0 : 2000 ;static bool struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,enum drm_dp_phy dp_phy)bool ret = false ;if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy))goto out;if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy))goto out;true ;"Link Training %s at link rate = %d, lane count = %d\n" ,"passed" : "failed" ,return ret;static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,int link_rate,/* FIXME figure out what we actually want here */ const struct drm_display_mode *fixed_mode =int mode_rate, max_rate;18 );if (mode_rate > max_rate)return false ;return true ;static bool reduce_link_params_in_bw_order(struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,int *new_link_rate, int *new_lane_count)int link_rate;int lane_count;int i;t);for (i--; i >= 0 ; i--) {if ((intel_dp->link.force_rate &&continue ;break ;if (i < 0 )return false ;return true ;static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate)int rate_index;int new_rate;if (intel_dp->link.force_rate)return -1 ;if (rate_index <= 0 )return -1 ;1 );/* TODO: Make switching from UHBR to non-UHBR rates work. */ if (drm_dp_is_uhbr_rate(current_rate) != drm_dp_is_uhbr_rate(new_rate))return -1 ;return new_rate;static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count)if (intel_dp->link.force_lane_count)return -1 ;if (current_lane_count == 1 )return -1 ;return current_lane_count >> 1 ;static bool reduce_link_params_in_rate_lane_order(struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,int *new_link_rate, int *new_lane_count)int link_rate;int lane_count;if (link_rate < 0 ) {if (lane_count < 0 )return false ;return true ;static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state,int *new_link_rate, int *new_lane_count)/* TODO: Use the same fallback logic on SST as on MST. */ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))return reduce_link_params_in_bw_order(intel_dp, crtc_state,else return reduce_link_params_in_rate_lane_order(intel_dp, crtc_state,static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state)int new_link_rate;int new_lane_count;if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {"Retrying Link training for eDP with max parameters\n" );true ;return 0 ;if (!reduce_link_params(intel_dp, crtc_state, &new_link_rate, &new_lane_count))return -1 ;if (intel_dp_is_edp(intel_dp) &&) {"Retrying Link training for eDP with same parameters\n" );return 0 ;"Reducing link parameters from %dx%d to %dx%d\n" ,return 0 ;static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state,struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state)struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) {"Link Training failed on disconnected sink.\n" );return true ;if (intel_dp->hobl_active) {"Link Training failed with HOBL active, not enabling it from now on\n" );true ;else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) {return false ;/* Schedule a Hotplug Uevent to userspace to start modeset */ return true ;/* Perform the link training on all LTTPRs and the DPRX on a link. */ static bool struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,int lttpr_count)bool ret = true ;int i;for (i = lttpr_count - 1 ; i >= 0 ; i--) {enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i);if (!ret)break ;if (ret)if (intel_dp->set_idle_link_train)return ret;/* * 128 b / 132 b DP LANEx_EQ_DONE Sequence ( DP 2 . 0 E11 3 . 5 . 2 . 16 . 1 ) static bool struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state)int delay_us;int try , max_tries = 20 ;unsigned long deadline;bool timeout = false ;/* * Reset signal levels . Start transmitting 128 b / 132 b TPS1 . * * Put DPRX and LTTPRs ( if any ) into intra - hop AUX mode by writing TPS1 * in DP_TRAINING_PATTERN_SET . if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX,"Failed to start 128b/132b TPS1\n" );return false ;/* Read the initial TX FFE settings. */ if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0 ) {"Failed to read TX FFE presets\n" );return false ;/* Update signal levels and training set as requested. */ if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {"Failed to set initial TX FFE settings\n" );return false ;/* Start transmitting 128b/132b TPS2. */ if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX,"Failed to start 128b/132b TPS2\n" );return false ;/* Time budget for the LANEx_EQ_DONE Sequence */ 450 );for (try = 0 ; try < max_tries; try ++) {if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0 ) {"Failed to read link status\n" );return false ;if (drm_dp_128b132b_link_training_failed(link_status)) {"Downstream link training failure\n" );return false ;if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) {"Lane channel eq done\n" );break ;if (timeout) {"Lane channel eq timeout\n" );return false ;if (time_after(jiffies, deadline))true ; /* try one last time after deadline */ /* * During LT , Tx shall read AUX_RD_INTERVAL just before writing the new FFE * presets . /* Update signal levels and training set as requested. */ if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {"Failed to update TX FFE settings\n" );return false ;if (try == max_tries) {"Max loop count reached\n" );return false ;for (;;) {if (time_after(jiffies, deadline))true ; /* try one last time after deadline */ if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0 ) {"Failed to read link status\n" );return false ;if (drm_dp_128b132b_link_training_failed(link_status)) {"Downstream link training failure\n" );return false ;if (drm_dp_128b132b_eq_interlane_align_done(link_status)) {"Interlane align done\n" );break ;if (timeout) {"Interlane align timeout\n" );return false ;2000 , 3000 );return true ;/* * 128 b / 132 b DP LANEx_CDS_DONE Sequence ( DP 2 . 0 E11 3 . 5 . 2 . 16 . 2 ) static bool struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,int lttpr_count)unsigned long deadline;if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TRAINING_PATTERN_SET,1 ) {"Failed to start 128b/132b TPS2 CDS\n" );return false ;/* Time budget for the LANEx_CDS_DONE Sequence */ 1 ) * 20 );for (;;) {bool timeout = false ;if (time_after(jiffies, deadline))true ; /* try one last time after deadline */ 2000 , 3000 );if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0 ) {"Failed to read link status\n" );return false ;if (drm_dp_128b132b_eq_interlane_align_done(link_status) &&"CDS interlane align done\n" );break ;if (drm_dp_128b132b_link_training_failed(link_status)) {"Downstream link training failure\n" );return false ;if (timeout) {"CDS timeout\n" );return false ;return true ;/* * 128 b / 132 b link training sequence . ( DP 2 . 0 E11 SCR on link training . ) static bool struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state,int lttpr_count)bool passed = false ;if (wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0 , 500 )) {"128b/132b intra-hop not clear\n" );goto out;if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) &&true ;"128b/132b Link Training %s at link rate = %d, lane count = %d\n" ,"passed" : "failed" ,/* * Ensure that the training pattern does get set to TPS2 even in case * of a failure , as is the case at the end of a passing link training * and what is expected by the transcoder . Leaving TPS1 set ( and * disabling the link train mode in DP_TP_CTL later from TPS1 directly ) * would result in a stuck transcoder HW state and flip - done timeouts * later in the modeset sequence . if (!passed)return passed;/** * intel_dp_start_link_train - start link training * @ state : Atomic state * @ intel_dp : DP struct * @ crtc_state : state for CRTC attached to the encoder * * Start the link training of the @ intel_dp port , scheduling a fallback * retraining with reduced link rate / lane parameters if the link training * fails . * After calling this function intel_dp_stop_link_train ( ) must be called . void intel_dp_start_link_train(struct intel_atomic_state *state,struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state)struct intel_display *display = to_intel_display(state);struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);struct intel_encoder *encoder = &dig_port->base;bool passed;/* * Reinit the LTTPRs here to ensure that they are switched to * non - transparent mode . During an earlier LTTPR detection this * could ' ve been prevented by an active link . int lttpr_count;if (lttpr_count < 0 )/* Still continue with enabling the port and link training. */ 0 ;if (intel_dp_is_uhbr(crtc_state))else if (intel_dp->link.force_train_failure) {"Forcing link training failure\n" );else if (passed) {0 ;return ;/* * Ignore the link failure in CI * * In fixed environments like CI , sometimes unexpected long HPDs are * generated by the displays . If ignore_long_hpd flag is set , such long * HPDs are ignored . And probably as a consequence of these ignored * long HPDs , subsequent link trainings are failed resulting into CI * execution failures . * * For test cases which rely on the link training or processing of HPDs * ignore_long_hpd flag can unset from the testcase . if (display->hotplug.ignore_long_hpd) {"Ignore the link failure\n" );return ;if (intel_dp->link.seq_train_failures < MAX_SEQ_TRAIN_FAILURES)return ;if (intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state))return ;true ;if (!passed)"Can't reduce link training parameters after failure\n" );else "Can't reduce link training parameters after forced failure\n" );void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,const struct intel_crtc_state *crtc_state)/* * VIDEO_DIP_CTL register bit 31 should be set to ' 0 ' to not * disable SDP CRC . This is applicable for Display version 13 . * Default value of bit 31 is ' 0 ' hence discarding the write * TODO : Corrective actions on SDP corruption yet to be defined if (!intel_dp_is_uhbr(crtc_state))return ;/* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ "DP2.0 SDP CRC16 for 128b/132b enabled\n" );static int i915_dp_force_link_rate_show(struct seq_file *m, void *data)struct intel_connector *connector = to_intel_connector(m->private );struct intel_display *display = to_intel_display(connector);struct intel_dp *intel_dp = intel_attached_dp(connector);int current_rate = -1 ;int force_rate;int err;int i;if (err)return err;if (intel_dp->link.active)"%sauto%s" ,0 ? "[" : "" ,0 ? "]" : "" );for (i = 0 ; i < intel_dp->num_source_rates; i++)" %s%d%s%s" ,"[" : "" ,"*" : "" ,"]" : "" );'\n' );return 0 ;static int parse_link_rate(struct intel_dp *intel_dp, const char __user *ubuf, size_t len)char *kbuf;const char *p;int rate;int ret = 0 ;if (IS_ERR(kbuf))return PTR_ERR(kbuf);if (!strcmp(p, "auto" )) {0 ;else {0 , &rate);if (ret < 0 )goto out_free;if (intel_dp_rate_index(intel_dp->source_rates,0 )return ret < 0 ? ret : rate;static ssize_t i915_dp_force_link_rate_write(struct file *file,const char __user *ubuf,struct seq_file *m = file->private_data;struct intel_connector *connector = to_intel_connector(m->private );struct intel_display *display = to_intel_display(connector);struct intel_dp *intel_dp = intel_attached_dp(connector);int rate;int err;if (rate < 0 )return rate;if (err)return err;return len;static int i915_dp_force_lane_count_show(struct seq_file *m, void *data)struct intel_connector *connector = to_intel_connector(m->private );struct intel_display *display = to_intel_display(connector);struct intel_dp *intel_dp = intel_attached_dp(connector);int current_lane_count = -1 ;int force_lane_count;int err;int i;if (err)return err;if (intel_dp->link.active)"%sauto%s" ,0 ? "[" : "" ,0 ? "]" : "" );for (i = 1 ; i <= 4 ; i <<= 1 )" %s%d%s%s" ,"[" : "" ,"*" : "" ,"]" : "" );'\n' );return 0 ;static int parse_lane_count(const char __user *ubuf, size_t len)char *kbuf;const char *p;int lane_count;int ret = 0 ;if (IS_ERR(kbuf))return PTR_ERR(kbuf);if (!strcmp(p, "auto" )) {0 ;else {0 , &lane_count);if (ret < 0 )goto out_free;switch (lane_count) {case 1 :case 2 :case 4 :break ;default :return ret < 0 ? ret : lane_count;static ssize_t i915_dp_force_lane_count_write(struct file *file,const char __user *ubuf,struct seq_file *m = file->private_data;struct intel_connector *connector = to_intel_connector(m->private );struct intel_display *display = to_intel_display(connector);struct intel_dp *intel_dp = intel_attached_dp(connector);int lane_count;int err;if (lane_count < 0 )return lane_count;if (err)return err;return len;static int i915_dp_max_link_rate_show(void *data, u64 *val)struct intel_connector *connector = to_intel_connector(data);struct intel_display *display = to_intel_display(connector);struct intel_dp *intel_dp = intel_attached_dp(connector);int err;if (err)return err;return 0 ;ULL, "%llu\n" );static int i915_dp_max_lane_count_show(void *data, u64 *val)struct intel_connector *connector = to_intel_connector(data);struct intel_display *display = to_intel_display(connector);struct intel_dp *intel_dp = intel_attached_dp(connector);int err;if (err)return err;return 0 ;, NULL, "%llu\n" );static int i915_dp_force_link_training_failure_show(void *data, u64 *val)struct intel_connector *connector = to_intel_connector(data);struct intel_display *display = to_intel_display(connector);struct intel_dp *intel_dp = intel_attached_dp(connector);int err;if (err)return err;return 0 ;static int i915_dp_force_link_training_failure_write(void *data, u64 val)struct intel_connector *connector = to_intel_connector(data);struct intel_display *display = to_intel_display(connector);struct intel_dp *intel_dp = intel_attached_dp(connector);int err;if (val > 2 )return -EINVAL;if (err)return err;return 0 ;"%llu\n" );static int i915_dp_force_link_retrain_show(void *data, u64 *val)struct intel_connector *connector = to_intel_connector(data);struct intel_display *display = to_intel_display(connector);struct intel_dp *intel_dp = intel_attached_dp(connector);int err;if (err)return err;return 0 ;static int i915_dp_force_link_retrain_write(void *data, u64 val)struct intel_connector *connector = to_intel_connector(data);struct intel_display *display = to_intel_display(connector);struct intel_dp *intel_dp = intel_attached_dp(connector);int err;if (err)return err;return 0 ;"%llu\n" );static int i915_dp_link_retrain_disabled_show(struct seq_file *m, void *data)struct intel_connector *connector = to_intel_connector(m->private );struct intel_display *display = to_intel_display(connector);struct intel_dp *intel_dp = intel_attached_dp(connector);int err;if (err)return err;"%s\n" , str_yes_no(intel_dp->link.retrain_disabled));return 0 ;void intel_dp_link_training_debugfs_add(struct intel_connector *connector)struct dentry *root = connector->base.debugfs_entry;if (connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort &&return ;"i915_dp_force_link_rate" , 0644 , root,"i915_dp_force_lane_count" , 0644 , root,"i915_dp_max_link_rate" , 0444 , root,"i915_dp_max_lane_count" , 0444 , root,"i915_dp_force_link_training_failure" , 0644 , root,"i915_dp_force_link_retrain" , 0644 , root,"i915_dp_link_retrain_disabled" , 0444 , root,
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