// SPDX-License-Identifier: MIT /* * Copyright © 2023 Intel Corporation #include "i915_drv.h" #include "i915_reg.h" #include "i9xx_wm.h" #include "i9xx_wm_regs.h" #include "intel_atomic.h" #include "intel_bo.h" #include "intel_de.h" #include "intel_display.h" #include "intel_display_regs.h" #include "intel_display_trace.h" #include "intel_fb.h" #include "intel_mchbar_regs.h" #include "intel_wm.h" #include "skl_watermark.h" #include "vlv_sideband.h" struct intel_watermark_params {/* used in computing the new watermarks state */ struct intel_wm_config {unsigned int num_pipes_active;bool sprites_enabled;bool sprites_scaled;struct cxsr_latency {bool is_desktop : 1 ;bool is_ddr3 : 1 ;static const struct cxsr_latency cxsr_latency_table[] = {1 , 0 , 800 , 400 , 3382 , 33382 , 3983 , 33983 }, /* DDR2-400 SC */ 1 , 0 , 800 , 667 , 3354 , 33354 , 3807 , 33807 }, /* DDR2-667 SC */ 1 , 0 , 800 , 800 , 3347 , 33347 , 3763 , 33763 }, /* DDR2-800 SC */ 1 , 1 , 800 , 667 , 6420 , 36420 , 6873 , 36873 }, /* DDR3-667 SC */ 1 , 1 , 800 , 800 , 5902 , 35902 , 6318 , 36318 }, /* DDR3-800 SC */ 1 , 0 , 667 , 400 , 3400 , 33400 , 4021 , 34021 }, /* DDR2-400 SC */ 1 , 0 , 667 , 667 , 3372 , 33372 , 3845 , 33845 }, /* DDR2-667 SC */ 1 , 0 , 667 , 800 , 3386 , 33386 , 3822 , 33822 }, /* DDR2-800 SC */ 1 , 1 , 667 , 667 , 6438 , 36438 , 6911 , 36911 }, /* DDR3-667 SC */ 1 , 1 , 667 , 800 , 5941 , 35941 , 6377 , 36377 }, /* DDR3-800 SC */ 1 , 0 , 400 , 400 , 3472 , 33472 , 4173 , 34173 }, /* DDR2-400 SC */ 1 , 0 , 400 , 667 , 3443 , 33443 , 3996 , 33996 }, /* DDR2-667 SC */ 1 , 0 , 400 , 800 , 3430 , 33430 , 3946 , 33946 }, /* DDR2-800 SC */ 1 , 1 , 400 , 667 , 6509 , 36509 , 7062 , 37062 }, /* DDR3-667 SC */ 1 , 1 , 400 , 800 , 5985 , 35985 , 6501 , 36501 }, /* DDR3-800 SC */ 0 , 0 , 800 , 400 , 3438 , 33438 , 4065 , 34065 }, /* DDR2-400 SC */ 0 , 0 , 800 , 667 , 3410 , 33410 , 3889 , 33889 }, /* DDR2-667 SC */ 0 , 0 , 800 , 800 , 3403 , 33403 , 3845 , 33845 }, /* DDR2-800 SC */ 0 , 1 , 800 , 667 , 6476 , 36476 , 6955 , 36955 }, /* DDR3-667 SC */ 0 , 1 , 800 , 800 , 5958 , 35958 , 6400 , 36400 }, /* DDR3-800 SC */ 0 , 0 , 667 , 400 , 3456 , 33456 , 4103 , 34106 }, /* DDR2-400 SC */ 0 , 0 , 667 , 667 , 3428 , 33428 , 3927 , 33927 }, /* DDR2-667 SC */ 0 , 0 , 667 , 800 , 3443 , 33443 , 3905 , 33905 }, /* DDR2-800 SC */ 0 , 1 , 667 , 667 , 6494 , 36494 , 6993 , 36993 }, /* DDR3-667 SC */ 0 , 1 , 667 , 800 , 5998 , 35998 , 6460 , 36460 }, /* DDR3-800 SC */ 0 , 0 , 400 , 400 , 3528 , 33528 , 4255 , 34255 }, /* DDR2-400 SC */ 0 , 0 , 400 , 667 , 3500 , 33500 , 4079 , 34079 }, /* DDR2-667 SC */ 0 , 0 , 400 , 800 , 3487 , 33487 , 4029 , 34029 }, /* DDR2-800 SC */ 0 , 1 , 400 , 667 , 6566 , 36566 , 7145 , 37145 }, /* DDR3-667 SC */ 0 , 1 , 400 , 800 , 6042 , 36042 , 6584 , 36584 }, /* DDR3-800 SC */ static const struct cxsr_latency *pnv_get_cxsr_latency(struct intel_display *display)struct drm_i915_private *i915 = to_i915(display->drm);int i;for (i = 0 ; i < ARRAY_SIZE(cxsr_latency_table); i++) {const struct cxsr_latency *latency = &cxsr_latency_table[i];bool is_desktop = !display->platform.mobile;if (is_desktop == latency->is_desktop &&1000 ) == latency->fsb_freq &&1000 ) == latency->mem_freq)return latency;"Could not find CxSR latency for DDR%s, FSB %u kHz, MEM %u kHz\n" ,"3" : "2" , i915->fsb_freq, i915->mem_freq);return NULL;static void chv_set_memory_dvfs(struct intel_display *display, bool enable)if (enable)else if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2) &0 , 3 ))"timed out waiting for Punit DDR DVFS request\n" );static void chv_set_memory_pm5(struct intel_display *display, bool enable)if (enable)else #define FW_WM(value, plane) \## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)static bool _intel_set_memory_cxsr(struct intel_display *display, bool enable)bool was_enabled;if (display->platform.valleyview || display->platform.cherryview) {0 );else if (display->platform.g4x || display->platform.i965gm) {0 );else if (display->platform.pineview) {if (enable)else else if (display->platform.i945g || display->platform.i945gm) {else if (display->platform.i915gm) {/* * FIXME can ' t find a bit like this for 915 G , and * yet it does have the related watermark in * FW_BLC_SELF . What ' s going on ? else {return false ;"memory self-refresh is %s (was %s)\n" ,return was_enabled;/** * intel_set_memory_cxsr - Configure CxSR state * @ display : display device * @ enable : Allow vs . disallow CxSR * * Allow or disallow the system to enter a special CxSR * ( C - state self refresh ) state . What typically happens in CxSR mode * is that several display FIFOs may get combined into a single larger * FIFO for a particular plane ( so called max FIFO mode ) to allow the * system to defer memory fetches longer , and the memory will enter * self refresh . * * Note that enabling CxSR does not guarantee that the system enter * this special mode , nor does it guarantee that the system stays * in that mode once entered . So this just allows / disallows the system * to autonomously utilize the CxSR mode . Other factors such as core * C - states will affect when / if the system actually enters / exits the * CxSR mode . * * Note that on VLV / CHV this actually only controls the max FIFO mode , * and the system is free to enter / exit memory self refresh at any time * even when the use of CxSR has been disallowed . * * While the system is actually in the CxSR / max FIFO mode , some plane * control registers will not get latched on vblank . Thus in order to * guarantee the system will respond to changes in the plane registers * we must always disallow CxSR prior to making changes to those registers . * Unfortunately the system will re - evaluate the CxSR conditions at * frame start which happens after vblank start ( which is when the plane * registers would get latched ) , so we can ' t proceed with the plane update * during the same frame where we disallowed CxSR . * * Certain platforms also have a deeper HPLL SR mode . Fortunately the * HPLL SR mode depends on CxSR itself , so we don ' t have to hand hold * the hardware w . r . t . HPLL SR when writing to plane registers . * Disallowing just CxSR is sufficient . bool intel_set_memory_cxsr(struct intel_display *display, bool enable)bool ret;if (display->platform.valleyview || display->platform.cherryview)else if (display->platform.g4x)return ret;/* * Latency for FIFO fetches is dependent on several factors : * - memory configuration ( speed , channels ) * - chipset * - current MCH state * It can be fairly high in some situations , so here we assume a fairly * pessimal value . It ' s a tradeoff between extra memory fetches ( if we * set this value too high , the FIFO will fetch frequently to stay full ) * and power consumption ( set it too low to save power and we might see * FIFO underruns and display " flicker " ) . * * A value of 5 us seems to be a good balance ; safe for very low end * platforms but not overly aggressive on lower latency configs . static const int pessimal_latency_ns = 5000 ;#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \0 xff) | ((((dsparb2) >> (hi_shift)) & 0 x1) << 8 ))static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)struct intel_display *display = to_intel_display(crtc_state);struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;enum pipe pipe = crtc->pipe;int sprite0_start, sprite1_start;switch (pipe) {case PIPE_A:0 , 0 );8 , 4 );break ;case PIPE_B:16 , 8 );24 , 12 );break ;case PIPE_C:0 , 16 );8 , 20 );break ;default :return ;511 - sprite1_start;63 ;static int i9xx_get_fifo_size(struct intel_display *display,enum i9xx_plane_id i9xx_plane)int size;0 x7f;if (i9xx_plane == PLANE_B)0 x7f) - size;"FIFO size - (0x%08x) %c: %d\n" ,return size;static int i830_get_fifo_size(struct intel_display *display,enum i9xx_plane_id i9xx_plane)int size;0 x1ff;if (i9xx_plane == PLANE_B)0 x1ff) - size;1 ; /* Convert to cachelines */ "FIFO size - (0x%08x) %c: %d\n" ,return size;static int i845_get_fifo_size(struct intel_display *display,enum i9xx_plane_id i9xx_plane)int size;0 x7f;2 ; /* Convert to cachelines */ "FIFO size - (0x%08x) %c: %d\n" ,return size;/* Pineview has different values for various configs */ static const struct intel_watermark_params pnv_display_wm = {static const struct intel_watermark_params pnv_display_hplloff_wm = {static const struct intel_watermark_params pnv_cursor_wm = {static const struct intel_watermark_params pnv_cursor_hplloff_wm = {static const struct intel_watermark_params i965_cursor_wm_info = {2 ,static const struct intel_watermark_params i945_wm_info = {1 ,2 ,static const struct intel_watermark_params i915_wm_info = {1 ,2 ,static const struct intel_watermark_params i830_a_wm_info = {1 ,2 ,static const struct intel_watermark_params i830_bc_wm_info = {2 ,1 ,2 ,static const struct intel_watermark_params i845_wm_info = {1 ,2 ,/** * intel_wm_method1 - Method 1 / " small buffer " watermark formula * @ pixel_rate : Pipe pixel rate in kHz * @ cpp : Plane bytes per pixel * @ latency : Memory wakeup latency in 0 . 1 us units * * Compute the watermark using the method 1 or " small buffer " * formula . The caller may additionally add extra cachelines * to account for TLB misses and clock crossings . * * This method is concerned with the short term drain rate * of the FIFO , ie . it does not account for blanking periods * which would effectively reduce the average drain rate across * a longer period . The name " small " refers to the fact the * FIFO is relatively small compared to the amount of data * fetched . * * The FIFO level vs . time graph might look something like : * * | \ | \ * | \ | \ * _ _ - - - _ _ - - - _ _ ( - plane active , _ blanking ) * - > time * * or perhaps like this : * * | \ | \ | \ | \ * _ _ - - - - _ _ - - - - _ _ ( - plane active , _ blanking ) * - > time * * Returns : * The watermark in bytes static unsigned int intel_wm_method1(unsigned int pixel_rate,unsigned int cpp,unsigned int latency)10000 );return ret;/** * intel_wm_method2 - Method 2 / " large buffer " watermark formula * @ pixel_rate : Pipe pixel rate in kHz * @ htotal : Pipe horizontal total * @ width : Plane width in pixels * @ cpp : Plane bytes per pixel * @ latency : Memory wakeup latency in 0 . 1 us units * * Compute the watermark using the method 2 or " large buffer " * formula . The caller may additionally add extra cachelines * to account for TLB misses and clock crossings . * * This method is concerned with the long term drain rate * of the FIFO , ie . it does account for blanking periods * which effectively reduce the average drain rate across * a longer period . The name " large " refers to the fact the * FIFO is relatively large compared to the amount of data * fetched . * * The FIFO level vs . time graph might look something like : * * | \ _ _ _ | \ _ _ _ * | \ _ _ _ | \ _ _ _ * | \ | \ * _ _ - - _ _ - - _ _ - - _ _ - - _ _ - - _ _ - - _ _ ( - plane active , _ blanking ) * - > time * * Returns : * The watermark in bytes static unsigned int intel_wm_method2(unsigned int pixel_rate,unsigned int htotal,unsigned int width,unsigned int cpp,unsigned int latency)unsigned int ret;/* * FIXME remove once all users are computing * watermarks in the correct place . if (WARN_ON_ONCE(htotal == 0 ))1 ;10000 );1 ) * width * cpp;return ret;/** * intel_calculate_wm - calculate watermark level * @ display : display device * @ pixel_rate : pixel clock * @ wm : chip FIFO params * @ fifo_size : size of the FIFO buffer * @ cpp : bytes per pixel * @ latency_ns : memory latency for the platform * * Calculate the watermark level ( the level at which the display plane will * start fetching from memory again ) . Each chip has a different display * FIFO size and allocation , so the caller needs to figure that out and pass * in the correct intel_watermark_params structure . * * As the pixel clock runs , the FIFO will be drained at a rate that depends * on the pixel size . When it reaches the watermark level , it ' ll start * fetching FIFO line sized based chunks from memory until the FIFO fills * past the watermark point . If the FIFO drains completely , a FIFO underrun * will occur , and a display engine hang could result . static unsigned int intel_calculate_wm(struct intel_display *display,int pixel_rate,const struct intel_watermark_params *wm,int fifo_size, int cpp,unsigned int latency_ns)int entries, wm_size;/* * Note : we need to make sure we don ' t overflow for various clock & * latency values . * clocks go from a few thousand to several hundred thousand . * latency is usually a few thousand 100 );"FIFO entries required for mode: %d\n" , entries);"FIFO watermark level: %d\n" , wm_size);/* Don't promote wm_size to unsigned... */ if (wm_size > wm->max_wm)if (wm_size <= 0 )/* * Bspec seems to indicate that the value shouldn ' t be lower than * ' burst size + 1 ' . Certainly 830 is quite unhappy with low values . * Lets go for 8 which is the burst size since certain platforms * already use a hardcoded 8 ( which is what the spec says should be * done ) . if (wm_size <= 8 )8 ;return wm_size;static bool is_disabling(int old, int new , int threshold)return old >= threshold && new < threshold;static bool is_enabling(int old, int new , int threshold)return old < threshold && new >= threshold;static bool intel_crtc_active(struct intel_crtc *crtc)/* Be paranoid as we can arrive here with only partial * state retrieved from the hardware during setup . * * We can ditch the adjusted_mode . crtc_clock check as soon * as Haswell has gained clock readout / fastboot support . * * We can ditch the crtc - > primary - > state - > fb check as soon as we can * properly reconstruct framebuffers . * * FIXME : The intel_crtc - > active here should be switched to * crtc - > state - > active once we have proper CRTC states wired up * for atomic . return crtc->active && crtc->base.primary->state->fb &&static struct intel_crtc *single_enabled_crtc(struct intel_display *display)struct intel_crtc *crtc, *enabled = NULL;if (intel_crtc_active(crtc)) {if (enabled)return NULL;return enabled;static void pnv_update_wm(struct intel_display *display)struct intel_crtc *crtc;const struct cxsr_latency *latency;unsigned int wm;if (!latency) {"Unknown FSB/MEM, disabling CxSR\n" );false );return ;if (crtc) {const struct drm_framebuffer *fb =int pixel_rate = crtc->config->pixel_rate;int cpp = fb->format->cpp[0 ];/* Display SR */ "DSPFW1 register is %x\n" , reg);/* cursor SR */ 4 , latency->cursor_sr);/* Display HPLL off SR */ /* cursor HPLL off SR */ 4 , latency->cursor_hpll_disable);"DSPFW3 register is %x\n" , reg);true );else {false );static bool i9xx_wm_need_update(const struct intel_plane_state *old_plane_state,const struct intel_plane_state *new_plane_state)/* Update watermarks on tiling or size changes. */ if (old_plane_state->uapi.visible != new_plane_state->uapi.visible)return true ;if (!old_plane_state->hw.fb || !new_plane_state->hw.fb)return false ;if (old_plane_state->hw.fb->modifier != new_plane_state->hw.fb->modifier ||return true ;return false ;static void i9xx_wm_compute(struct intel_crtc_state *new_crtc_state,const struct intel_plane_state *old_plane_state,const struct intel_plane_state *new_plane_state)bool turn_off, turn_on, visible, was_visible, mode_changed;if (!was_visible && !visible)return ;/* FIXME nuke when all wm code is atomic */ if (turn_on) {true ;else if (turn_off) {true ;else if (i9xx_wm_need_update(old_plane_state, new_plane_state)) {/* FIXME bollocks */ true ;true ;static int i9xx_compute_watermarks(struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_crtc_state *new_crtc_state =const struct intel_plane_state *old_plane_state;const struct intel_plane_state *new_plane_state;struct intel_plane *plane;int i;if (plane->pipe != crtc->pipe)continue ;return 0 ;/* * Documentation says : * " If the line size is small , the TLB fetches can get in the way of the * data fetches , causing some lag in the pixel data return which is not * accounted for in the above formulas . The following adjustment only * needs to be applied if eight whole lines fit in the buffer at once . * The WM is adjusted upwards by the difference between the FIFO size * and the size of 8 whole lines . This adjustment is always performed * in the actual pixel depth regardless of whether FBC is enabled or not . " static unsigned int g4x_tlb_miss_wa(int fifo_size, int width, int cpp)int tlb_miss = fifo_size * 64 - width * cpp * 8 ;return max(0 , tlb_miss);static void g4x_write_wm_values(struct intel_display *display,const struct g4x_wm_values *wm)enum pipe pipe;0 ) |0 ) |#define FW_WM_VLV(value, plane) \## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)static void vlv_write_wm_values(struct intel_display *display,const struct vlv_wm_values *wm)enum pipe pipe;1 )) |0 )) |/* * Zero the ( unused ) WM1 watermarks , and also clear all the * high order bits so that there are no out of bounds values * present in the registers during the reprogramming . 0 );0 );0 );0 );0 );if (display->platform.cherryview) {9 , SR_HI) |8 , SPRITEF_HI) |8 , SPRITEE_HI) |8 , PLANEC_HI) |8 , SPRITED_HI) |8 , SPRITEC_HI) |8 , PLANEB_HI) |8 , SPRITEB_HI) |8 , SPRITEA_HI) |8 , PLANEA_HI));else {9 , SR_HI) |8 , SPRITED_HI) |8 , SPRITEC_HI) |8 , PLANEB_HI) |8 , SPRITEB_HI) |8 , SPRITEA_HI) |8 , PLANEA_HI));#undef FW_WM_VLVstatic void g4x_setup_wm_latency(struct intel_display *display)/* all latencies in usec */ 5 ;12 ;35 ;1 ;static int g4x_plane_fifo_size(enum plane_id plane_id, int level)/* * DSPCNTR [ 13 ] supposedly controls whether the * primary plane can use the FIFO space otherwise * reserved for the sprite plane . It ' s not 100 % clear * what the actual FIFO size is , but it looks like we * can happily set both primary and sprite watermarks * up to 127 cachelines . So that would seem to mean * that either DSPCNTR [ 13 ] doesn ' t do anything , or that * the total FIFO is > = 256 cachelines in size . Either * way , we don ' t seem to have to worry about this * repartitioning as the maximum watermark value the * register can hold for each plane is lower than the * minimum FIFO size . switch (plane_id) {case PLANE_CURSOR:return 63 ;case PLANE_PRIMARY:return level == G4X_WM_LEVEL_NORMAL ? 127 : 511 ;case PLANE_SPRITE0:return level == G4X_WM_LEVEL_NORMAL ? 127 : 0 ;default :return 0 ;static int g4x_fbc_fifo_size(int level)switch (level) {case G4X_WM_LEVEL_SR:return 7 ;case G4X_WM_LEVEL_HPLL:return 15 ;default :return 0 ;static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,const struct intel_plane_state *plane_state,int level)struct intel_display *display = to_intel_display(plane_state);struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);const struct drm_display_mode *pipe_mode =unsigned int latency = display->wm.pri_latency[level] * 10 ;unsigned int pixel_rate, htotal, cpp, width, wm;if (latency == 0 )return USHRT_MAX;if (!intel_wm_plane_visible(crtc_state, plane_state))return 0 ;0 ];/* * WaUse32BppForSRWM : ctg , elk * * The spec fails to list this restriction for the * HPLL watermark , which seems a little strange . * Let ' s use 32 bpp for the HPLL watermark as well . if (plane->id == PLANE_PRIMARY &&4 u);16 ;if (plane->id == PLANE_CURSOR) {else if (plane->id == PLANE_PRIMARY &&else {unsigned int small, large;64 ) + 2 ;return min_t(unsigned int , wm, USHRT_MAX);static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,int level, enum plane_id plane_id, u16 value)struct intel_display *display = to_intel_display(crtc_state);bool dirty = false ;for (; level < display->wm.num_levels; level++) {struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];return dirty;static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,int level, u16 value)struct intel_display *display = to_intel_display(crtc_state);bool dirty = false ;/* NORMAL level doesn't have an FBC watermark */ for (; level < display->wm.num_levels; level++) {struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];return dirty;static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,const struct intel_plane_state *plane_state,static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,const struct intel_plane_state *plane_state)struct intel_display *display = to_intel_display(crtc_state);struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);enum plane_id plane_id = plane->id;bool dirty = false ;int level;if (!intel_wm_plane_visible(crtc_state, plane_state)) {0 , plane_id, 0 );if (plane_id == PLANE_PRIMARY)0 , 0 );goto out;for (level = 0 ; level < display->wm.num_levels; level++) {struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];int wm, max_wm;if (wm > max_wm)break ;if (plane_id != PLANE_PRIMARY ||continue ;/* * FBC wm is not mandatory as we * can always just disable its use . if (wm > max_wm)/* mark watermarks as invalid */ if (plane_id == PLANE_PRIMARY)if (dirty) {"%s watermarks: normal=%d, SR=%d, HPLL=%d\n" ,if (plane_id == PLANE_PRIMARY)"FBC watermarks: SR=%d, HPLL=%d\n" ,return dirty;static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,enum plane_id plane_id, int level)const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,int level)struct intel_display *display = to_intel_display(crtc_state);if (level >= display->wm.num_levels)return false ;return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&/* mark all levels starting from 'level' as invalid */ static void g4x_invalidate_wms(struct intel_crtc *crtc,struct g4x_wm_state *wm_state, int level)if (level <= G4X_WM_LEVEL_NORMAL) {enum plane_id plane_id;if (level <= G4X_WM_LEVEL_SR) {false ;if (level <= G4X_WM_LEVEL_HPLL) {false ;static bool g4x_compute_fbc_en(const struct g4x_wm_state *wm_state,int level)if (level < G4X_WM_LEVEL_SR)return false ;if (level >= G4X_WM_LEVEL_SR &&return false ;if (level >= G4X_WM_LEVEL_HPLL &&return false ;return true ;static int _g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;const struct g4x_pipe_wm *raw;enum plane_id plane_id;int level;if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))goto out;if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))goto out;if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))goto out;if (level == G4X_WM_LEVEL_NORMAL)return -EINVAL;/* invalidate the higher levels */ /* * Determine if the FBC watermark ( s ) can be used . IF * this isn ' t the case we prefer to disable the FBC * watermark ( s ) rather than disable the SR / HPLL * level ( s ) entirely . ' level - 1 ' is the highest valid * level here . 1 );return 0 ;static int g4x_compute_pipe_wm(struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_crtc_state *crtc_state =const struct intel_plane_state *old_plane_state;const struct intel_plane_state *new_plane_state;struct intel_plane *plane;unsigned int dirty = 0 ;int i;if (new_plane_state->hw.crtc != &crtc->base &&continue ;if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))if (!dirty)return 0 ;return _g4x_compute_pipe_wm(crtc_state);static int g4x_compute_intermediate_wm(struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_display *display = to_intel_display(state);struct intel_crtc_state *new_crtc_state =const struct intel_crtc_state *old_crtc_state =struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;enum plane_id plane_id;if (!new_crtc_state->hw.active ||false ;false ;goto out;1 ) &&2 ) &&/* * If our intermediate WM are identical to the final WM , then we can * omit the post - vblank programming ; only update if it ' s different . if (memcmp(intermediate, optimal, sizeof (*intermediate)) != 0 )true ;return 0 ;static int g4x_compute_watermarks(struct intel_atomic_state *state,struct intel_crtc *crtc)int ret;if (ret)return ret;if (ret)return ret;return 0 ;static void g4x_merge_wm(struct intel_display *display,struct g4x_wm_values *wm)struct intel_crtc *crtc;int num_active_pipes = 0 ;true ;true ;true ;const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;if (!crtc->active)continue ;if (!wm_state->cxsr)false ;if (!wm_state->hpll_en)false ;if (!wm_state->fbc_en)false ;if (num_active_pipes != 1 ) {false ;false ;false ;const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;enum pipe pipe = crtc->pipe;if (crtc->active && wm->cxsr)if (crtc->active && wm->hpll_en)static void g4x_program_watermarks(struct intel_display *display)struct g4x_wm_values *old_wm = &display->wm.g4x;struct g4x_wm_values new_wm = {};if (memcmp(old_wm, &new_wm, sizeof (new_wm)) == 0 )return ;if (is_disabling(old_wm->cxsr, new_wm.cxsr, true ))false );if (is_enabling(old_wm->cxsr, new_wm.cxsr, true ))true );static void g4x_initial_watermarks(struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_display *display = to_intel_display(crtc);const struct intel_crtc_state *crtc_state =static void g4x_optimize_watermarks(struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_display *display = to_intel_display(crtc);const struct intel_crtc_state *crtc_state =if (!crtc_state->wm.need_postvbl_update)return ;/* latency must be in 0.1us units. */ static unsigned int vlv_wm_method2(unsigned int pixel_rate,unsigned int htotal,unsigned int width,unsigned int cpp,unsigned int latency)unsigned int ret;64 );return ret;static void vlv_setup_wm_latency(struct intel_display *display)/* all latencies in usec */ 3 ;1 ;if (display->platform.cherryview) {12 ;33 ;1 ;static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,const struct intel_plane_state *plane_state,int level)struct intel_display *display = to_intel_display(plane_state);struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);const struct drm_display_mode *pipe_mode =unsigned int pixel_rate, htotal, cpp, width, wm;if (display->wm.pri_latency[level] == 0 )return USHRT_MAX;if (!intel_wm_plane_visible(crtc_state, plane_state))return 0 ;0 ];16 ;if (plane->id == PLANE_CURSOR) {/* * FIXME the formula gives values that are * too big for the cursor FIFO , and hence we * would never be able to use cursors . For * now just hardcode the watermark . 63 ;else {10 );return min_t(unsigned int , wm, USHRT_MAX);static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)return (active_planes & (BIT(PLANE_SPRITE0) |static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)struct intel_display *display = to_intel_display(crtc_state);struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);const struct g4x_pipe_wm *raw =struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;int num_active_planes = hweight8(active_planes);const int fifo_size = 511 ;int fifo_extra, fifo_left = fifo_size;int sprite0_fifo_extra = 0 ;unsigned int total_rate;enum plane_id plane_id;/* * When enabling sprite0 after sprite1 has already been enabled * we tend to get an underrun unless sprite0 already has some * FIFO space allocated . Hence we always allocate at least one * cacheline for sprite0 whenever sprite1 is enabled . * * All other plane enable sequences appear immune to this problem . if (vlv_need_sprite0_fifo_workaround(active_planes))1 ;if (total_rate > fifo_size)return -EINVAL;if (total_rate == 0 )1 ;unsigned int rate;if ((active_planes & BIT(plane_id)) == 0 ) {0 ;continue ;63 ;1 );/* spread the remainder evenly */ int plane_extra;if (fifo_left == 0 )break ;if ((active_planes & BIT(plane_id)) == 0 )continue ;0 && fifo_left != 0 );/* give it all to the first plane if none are active */ if (active_planes == 0 ) {return 0 ;/* mark all levels starting from 'level' as invalid */ static void vlv_invalidate_wms(struct intel_crtc *crtc,struct vlv_wm_state *wm_state, int level)struct intel_display *display = to_intel_display(crtc);for (; level < display->wm.num_levels; level++) {enum plane_id plane_id;static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)if (wm > fifo_size)return USHRT_MAX;else return fifo_size - wm;/* * Starting from ' level ' set all higher * levels to ' value ' in the " raw " watermarks . static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,int level, enum plane_id plane_id, u16 value)struct intel_display *display = to_intel_display(crtc_state);bool dirty = false ;for (; level < display->wm.num_levels; level++) {struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];return dirty;static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,const struct intel_plane_state *plane_state)struct intel_display *display = to_intel_display(crtc_state);struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);enum plane_id plane_id = plane->id;int level;bool dirty = false ;if (!intel_wm_plane_visible(crtc_state, plane_state)) {0 , plane_id, 0 );goto out;for (level = 0 ; level < display->wm.num_levels; level++) {struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];int wm = vlv_compute_wm_level(crtc_state, plane_state, level);int max_wm = plane_id == PLANE_CURSOR ? 63 : 511 ;if (wm > max_wm)break ;/* mark all higher levels as invalid */ if (dirty)"%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n" ,return dirty;static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,enum plane_id plane_id, int level)const struct g4x_pipe_wm *raw =const struct vlv_fifo_state *fifo_state =return raw->plane[plane_id] <= fifo_state->plane[plane_id];static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&static int _vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)struct intel_display *display = to_intel_display(crtc_state);struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;const struct vlv_fifo_state *fifo_state =int num_active_planes = hweight8(active_planes);enum plane_id plane_id;int level;/* initially allow all levels */ /* * Note that enabling cxsr with no primary / sprite planes * enabled can wedge the pipe . Hence we only allow cxsr * with exactly one enabled primary / sprite plane . 1 ;for (level = 0 ; level < wm_state->num_levels; level++) {const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];const int sr_fifo_size = INTEL_NUM_PIPES(display) * 512 - 1 ;if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))break ;63 );if (level == 0 )return -EINVAL;/* limit to only levels we can actually handle */ /* invalidate the higher levels */ return 0 ;static int vlv_compute_pipe_wm(struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_crtc_state *crtc_state =const struct intel_plane_state *old_plane_state;const struct intel_plane_state *new_plane_state;struct intel_plane *plane;unsigned int dirty = 0 ;int i;if (new_plane_state->hw.crtc != &crtc->base &&continue ;if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))/* * DSPARB registers may have been reset due to the * power well being turned off . Make sure we restore * them to a consistent state even if no primary / sprite * planes are initially active . We also force a FIFO * recomputation so that we are sure to sanitize the * FIFO setting we took over from the BIOS even if there * are no active planes on the crtc . if (intel_crtc_needs_modeset(crtc_state))0 ;if (!dirty)return 0 ;/* cursor changes don't warrant a FIFO recompute */ if (dirty & ~BIT(PLANE_CURSOR)) {const struct intel_crtc_state *old_crtc_state =const struct vlv_fifo_state *old_fifo_state =const struct vlv_fifo_state *new_fifo_state =int ret;if (ret)return ret;if (intel_crtc_needs_modeset(crtc_state) ||sizeof (*new_fifo_state)) != 0 )true ;return _vlv_compute_pipe_wm(crtc_state);#define VLV_FIFO(plane, value) \## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)static void vlv_atomic_update_fifo(struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_display *display = to_intel_display(crtc);struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);struct intel_uncore *uncore = &dev_priv->uncore;const struct intel_crtc_state *crtc_state =const struct vlv_fifo_state *fifo_state =int sprite0_start, sprite1_start, fifo_size;if (!crtc_state->fifo_changed)return ;63 );511 );/* * uncore . lock serves a double purpose here . It allows us to * use the less expensive I915_ { READ , WRITE } _ FW ( ) functions , and * it protects the DSPARB registers from getting clobbered by * parallel updates from multiple pipes . * * intel_pipe_update_start ( ) has already disabled interrupts * for us , so a plain spin_lock ( ) is sufficient here . switch (crtc->pipe) {case PIPE_A:0 xff) |0 xff));0 x1) |0 x1));8 ) |8 ));break ;case PIPE_B:0 xff) |0 xff));0 xff) |0 xff));8 ) |8 ));break ;case PIPE_C:0 xff) |0 xff));0 xff) |0 xff));8 ) |8 ));break ;default :break ;#undef VLV_FIFOstatic int vlv_compute_intermediate_wm(struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_crtc_state *new_crtc_state =const struct intel_crtc_state *old_crtc_state =struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;int level;if (!new_crtc_state->hw.active ||false ;goto out;for (level = 0 ; level < intermediate->num_levels; level++) {enum plane_id plane_id;/* * If our intermediate WM are identical to the final WM , then we can * omit the post - vblank programming ; only update if it ' s different . if (memcmp(intermediate, optimal, sizeof (*intermediate)) != 0 )true ;return 0 ;static int vlv_compute_watermarks(struct intel_atomic_state *state,struct intel_crtc *crtc)int ret;if (ret)return ret;if (ret)return ret;return 0 ;static void vlv_merge_wm(struct intel_display *display,struct vlv_wm_values *wm)struct intel_crtc *crtc;int num_active_pipes = 0 ;1 ;true ;const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;if (!crtc->active)continue ;if (!wm_state->cxsr)false ;int , wm->level, wm_state->num_levels - 1 );if (num_active_pipes != 1 )false ;if (num_active_pipes > 1 )const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;enum pipe pipe = crtc->pipe;if (crtc->active && wm->cxsr)2 ;2 ;2 ;2 ;static void vlv_program_watermarks(struct intel_display *display)struct vlv_wm_values *old_wm = &display->wm.vlv;struct vlv_wm_values new_wm = {};if (memcmp(old_wm, &new_wm, sizeof (new_wm)) == 0 )return ;if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))false );if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))false );if (is_disabling(old_wm->cxsr, new_wm.cxsr, true ))false );if (is_enabling(old_wm->cxsr, new_wm.cxsr, true ))true );if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))true );if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))true );static void vlv_initial_watermarks(struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_display *display = to_intel_display(crtc);const struct intel_crtc_state *crtc_state =static void vlv_optimize_watermarks(struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_display *display = to_intel_display(crtc);const struct intel_crtc_state *crtc_state =if (!crtc_state->wm.need_postvbl_update)return ;static void i965_update_wm(struct intel_display *display)struct intel_crtc *crtc;int srwm = 1 ;int cursor_sr = 16 ;bool cxsr_enabled;/* Calc sr entries for one plane configs */ if (crtc) {/* self-refresh has much higher latency */ static const int sr_latency_ns = 12000 ;const struct drm_display_mode *pipe_mode =const struct drm_framebuffer *fb =int pixel_rate = crtc->config->pixel_rate;int htotal = pipe_mode->crtc_htotal;int width = drm_rect_width(&crtc->base.primary->state->src) >> 16 ;int cpp = fb->format->cpp[0 ];int entries;100 );if (srwm < 0 )1 ;0 x1ff;"self-refresh entries: %d, wm: %d\n" ,4 ,100 );if (cursor_sr > i965_cursor_wm_info.max_wm)"self-refresh watermark: display plane %d " "cursor %d\n" , srwm, cursor_sr);true ;else {false ;/* Turn off self refresh if both pipes are enabled */ false );"Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n" ,/* 965 has limitations... */ 8 , CURSORB) |8 , PLANEB) |8 , PLANEA));8 , CURSORA) |8 , PLANEC_OLD));/* update cursor SR watermark */ if (cxsr_enabled)true );#undef FW_WMstatic struct intel_crtc *intel_crtc_for_plane(struct intel_display *display,enum i9xx_plane_id i9xx_plane)struct intel_plane *plane;if (plane->id == PLANE_PRIMARY &&return intel_crtc_for_pipe(display, plane->pipe);return NULL;static void i9xx_update_wm(struct intel_display *display)const struct intel_watermark_params *wm_info;int cwm, srwm = 1 ;int fifo_size;int planea_wm, planeb_wm;struct intel_crtc *crtc;if (display->platform.i945gm)else if (DISPLAY_VER(display) != 2 )else if (DISPLAY_VER(display) == 2 )else if (intel_crtc_active(crtc)) {const struct drm_framebuffer *fb =int cpp;if (DISPLAY_VER(display) == 2 )4 ;else 0 ];else {if (planea_wm > (long )wm_info->max_wm)if (DISPLAY_VER(display) == 2 )if (DISPLAY_VER(display) == 2 )else if (intel_crtc_active(crtc)) {const struct drm_framebuffer *fb =int cpp;if (DISPLAY_VER(display) == 2 )4 ;else 0 ];else {if (planeb_wm > (long )wm_info->max_wm)"FIFO watermarks - A: %d, B: %d\n" , planea_wm, planeb_wm);if (display->platform.i915gm && crtc) {struct drm_gem_object *obj;/* self-refresh seems busted with untiled */ if (!intel_bo_is_tiled(obj))/* * Overlay gets an aggressive default since video jitter is bad . 2 ;/* Play safe and disable self-refresh before adjusting watermarks. */ false );/* Calc sr entries for one plane configs */ if (HAS_FW_BLC(display) && crtc) {/* self-refresh has much higher latency */ static const int sr_latency_ns = 6000 ;const struct drm_display_mode *pipe_mode =const struct drm_framebuffer *fb =int pixel_rate = crtc->config->pixel_rate;int htotal = pipe_mode->crtc_htotal;int width = drm_rect_width(&crtc->base.primary->state->src) >> 16 ;int cpp;int entries;if (display->platform.i915gm || display->platform.i945gm)4 ;else 0 ];100 );"self-refresh entries: %d\n" , entries);if (srwm < 0 )1 ;if (display->platform.i945g || display->platform.i945gm)0 xff));else 0 x3f);"Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n" ,0 x3f) << 16 ) | (planea_wm & 0 x3f);0 x1f);/* Set request length to 8 cachelines per fetch */ 1 << 24 ) | (1 << 8 );1 << 8 );if (crtc)true );static void i845_update_wm(struct intel_display *display)struct intel_crtc *crtc;int planea_wm;if (crtc == NULL)return ;4 , pessimal_latency_ns);0 xfff;3 <<8 ) | planea_wm;"Setting FIFO watermarks - A: %d\n" , planea_wm);/* latency must be in 0.1us units. */ static unsigned int ilk_wm_method1(unsigned int pixel_rate,unsigned int cpp,unsigned int latency)unsigned int ret;64 ) + 2 ;return ret;/* latency must be in 0.1us units. */ static unsigned int ilk_wm_method2(unsigned int pixel_rate,unsigned int htotal,unsigned int width,unsigned int cpp,unsigned int latency)unsigned int ret;64 ) + 2 ;return ret;static u32 ilk_wm_fbc(u32 pri_val, u32 horiz_pixels, u8 cpp)/* * Neither of these should be possible since this function shouldn ' t be * called if the CRTC is off or the plane is invisible . But let ' s be * extra paranoid to avoid a potential divide - by - zero if we screw up * elsewhere in the driver . if (WARN_ON(!cpp))return 0 ;if (WARN_ON(!horiz_pixels))return 0 ;return DIV_ROUND_UP(pri_val * 64 , horiz_pixels * cpp) + 2 ;struct ilk_wm_maximums {/* * For both WM_PIPE and WM_LP . * mem_value must be in 0 . 1 us units . static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,const struct intel_plane_state *plane_state,bool is_lp)int cpp;if (mem_value == 0 )return U32_MAX;if (!intel_wm_plane_visible(crtc_state, plane_state))return 0 ;0 ];if (!is_lp)return method1;16 ,return min(method1, method2);/* * For both WM_PIPE and WM_LP . * mem_value must be in 0 . 1 us units . static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,const struct intel_plane_state *plane_state,int cpp;if (mem_value == 0 )return U32_MAX;if (!intel_wm_plane_visible(crtc_state, plane_state))return 0 ;0 ];16 ,return min(method1, method2);/* * For both WM_PIPE and WM_LP . * mem_value must be in 0 . 1 us units . static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,const struct intel_plane_state *plane_state,int cpp;if (mem_value == 0 )return U32_MAX;if (!intel_wm_plane_visible(crtc_state, plane_state))return 0 ;0 ];return ilk_wm_method2(crtc_state->pixel_rate,16 ,/* Only for WM_LP. */ static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,const struct intel_plane_state *plane_state,int cpp;if (!intel_wm_plane_visible(crtc_state, plane_state))return 0 ;0 ];return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->uapi.src) >> 16 ,static unsigned int struct intel_display *display)if (DISPLAY_VER(display) >= 8 )return 3072 ;else if (DISPLAY_VER(display) >= 7 )return 768 ;else return 512 ;static unsigned int struct intel_display *display,int level, bool is_sprite)if (DISPLAY_VER(display) >= 8 )/* BDW primary/sprite plane watermarks */ return level == 0 ? 255 : 2047 ;else if (DISPLAY_VER(display) >= 7 )/* IVB/HSW primary/sprite plane watermarks */ return level == 0 ? 127 : 1023 ;else if (!is_sprite)/* ILK/SNB primary plane watermarks */ return level == 0 ? 127 : 511 ;else /* ILK/SNB sprite plane watermarks */ return level == 0 ? 63 : 255 ;static unsigned int struct intel_display *display, int level)if (DISPLAY_VER(display) >= 7 )return level == 0 ? 63 : 255 ;else return level == 0 ? 31 : 63 ;static unsigned int ilk_fbc_wm_reg_max(struct intel_display *display)if (DISPLAY_VER(display) >= 8 )return 31 ;else return 15 ;/* Calculate the maximum primary/sprite plane watermark */ static unsigned int ilk_plane_wm_max(struct intel_display *display,int level,const struct intel_wm_config *config,enum intel_ddb_partitioning ddb_partitioning,bool is_sprite)unsigned int fifo_size = ilk_display_fifo_size(display);/* if sprites aren't enabled, sprites get nothing */ if (is_sprite && !config->sprites_enabled)return 0 ;/* HSW allows LP1+ watermarks even with multiple pipes */ if (level == 0 || config->num_pipes_active > 1 ) {/* * For some reason the non self refresh * FIFO size is only half of the self * refresh FIFO size on ILK / SNB . if (DISPLAY_VER(display) < 7 )2 ;if (config->sprites_enabled) {/* level 0 is always calculated with 1:1 split */ if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {if (is_sprite)5 ;6 ;else {2 ;/* clamp to max that the registers can hold */ return min(fifo_size, ilk_plane_wm_reg_max(display, level, is_sprite));/* Calculate the maximum cursor plane watermark */ static unsigned int ilk_cursor_wm_max(struct intel_display *display,int level,const struct intel_wm_config *config)/* HSW LP1+ watermarks w/ multiple pipes */ if (level > 0 && config->num_pipes_active > 1 )return 64 ;/* otherwise just report max that registers can hold */ return ilk_cursor_wm_reg_max(display, level);static void ilk_compute_wm_maximums(struct intel_display *display,int level,const struct intel_wm_config *config,enum intel_ddb_partitioning ddb_partitioning,struct ilk_wm_maximums *max)false );true );static void ilk_compute_wm_reg_maximums(struct intel_display *display,int level,struct ilk_wm_maximums *max)false );true );static bool ilk_validate_wm_level(struct intel_display *display,int level,const struct ilk_wm_maximums *max,struct intel_wm_level *result)bool ret;/* already determined to be invalid? */ if (!result->enable)return false ;/* * HACK until we can pre - compute everything , * and thus fail gracefully if LP0 watermarks * are exceeded . . . if (level == 0 && !result->enable) {if (result->pri_val > max->pri)"Primary WM%d too large %u (max %u)\n" ,if (result->spr_val > max->spr)"Sprite WM%d too large %u (max %u)\n" ,if (result->cur_val > max->cur)"Cursor WM%d too large %u (max %u)\n" ,true ;return ret;static void ilk_compute_wm_level(struct intel_display *display,const struct intel_crtc *crtc,int level,struct intel_crtc_state *crtc_state,const struct intel_plane_state *pristate,const struct intel_plane_state *sprstate,const struct intel_plane_state *curstate,struct intel_wm_level *result)/* WM1+ latency values stored in 0.5us units */ if (level > 0 ) {5 ;5 ;5 ;if (pristate) {if (sprstate)if (curstate)true ;static void hsw_read_wm_latency(struct intel_display *display, u16 wm[])struct drm_i915_private *i915 = to_i915(display->drm);5 ;0 ] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);if (wm[0 ] == 0 )0 ] = REG_FIELD_GET64(SSKPD_OLD_WM0_MASK_HSW, sskpd);1 ] = REG_FIELD_GET64(SSKPD_WM1_MASK_HSW, sskpd);2 ] = REG_FIELD_GET64(SSKPD_WM2_MASK_HSW, sskpd);3 ] = REG_FIELD_GET64(SSKPD_WM3_MASK_HSW, sskpd);4 ] = REG_FIELD_GET64(SSKPD_WM4_MASK_HSW, sskpd);static void snb_read_wm_latency(struct intel_display *display, u16 wm[])struct drm_i915_private *i915 = to_i915(display->drm);4 ;0 ] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd);1 ] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd);2 ] = REG_FIELD_GET(SSKPD_WM2_MASK_SNB, sskpd);3 ] = REG_FIELD_GET(SSKPD_WM3_MASK_SNB, sskpd);static void ilk_read_wm_latency(struct intel_display *display, u16 wm[])struct drm_i915_private *i915 = to_i915(display->drm);3 ;/* ILK primary LP0 latency is 700 ns */ 0 ] = 7 ;1 ] = REG_FIELD_GET(MLTR_WM1_MASK, mltr);2 ] = REG_FIELD_GET(MLTR_WM2_MASK, mltr);static void intel_fixup_spr_wm_latency(struct intel_display *display, u16 wm[5 ])/* ILK sprite LP0 latency is 1300 ns */ if (DISPLAY_VER(display) == 5 )0 ] = 13 ;static void intel_fixup_cur_wm_latency(struct intel_display *display, u16 wm[5 ])/* ILK cursor LP0 latency is 1300 ns */ if (DISPLAY_VER(display) == 5 )0 ] = 13 ;static bool ilk_increase_wm_latency(struct intel_display *display, u16 wm[5 ], u16 min)int level;if (wm[0 ] >= min)return false ;0 ] = max(wm[0 ], min);for (level = 1 ; level < display->wm.num_levels; level++)5 ));return true ;static void snb_wm_latency_quirk(struct intel_display *display)bool changed;/* * The BIOS provided WM memory latency values are often * inadequate for high resolution displays . Adjust them . 12 );12 );12 );if (!changed)return ;"WM latency values increased to avoid potential underruns\n" );"Primary" , display->wm.pri_latency);"Sprite" , display->wm.spr_latency);"Cursor" , display->wm.cur_latency);static void snb_wm_lp3_irq_quirk(struct intel_display *display)/* * On some SNB machines ( Thinkpad X220 Tablet at least ) * LP3 usage can cause vblank interrupts to be lost . * The DEIIR bit will go high but it looks like the CPU * never gets interrupted . * * It ' s not clear whether other interrupt source could * be affected or if this is somehow limited to vblank * interrupts only . To play it safe we disable LP3 * watermarks entirely . if (display->wm.pri_latency[3 ] == 0 &&3 ] == 0 &&3 ] == 0 )return ;3 ] = 0 ;3 ] = 0 ;3 ] = 0 ;"LP3 watermarks disabled due to potential for lost interrupts\n" );"Primary" , display->wm.pri_latency);"Sprite" , display->wm.spr_latency);"Cursor" , display->wm.cur_latency);static void ilk_setup_wm_latency(struct intel_display *display)if (display->platform.broadwell || display->platform.haswell)else if (DISPLAY_VER(display) >= 6 )else sizeof (display->wm.pri_latency));sizeof (display->wm.pri_latency));"Primary" , display->wm.pri_latency);"Sprite" , display->wm.spr_latency);"Cursor" , display->wm.cur_latency);if (DISPLAY_VER(display) == 6 ) {static bool ilk_validate_pipe_wm(struct intel_display *display,struct intel_pipe_wm *pipe_wm)/* LP0 watermark maximums depend on this pipe alone */ const struct intel_wm_config config = {1 ,struct ilk_wm_maximums max;/* LP0 watermarks always use 1/2 DDB partitioning */ 0 , &config, INTEL_DDB_PART_1_2, &max);/* At least LP0 must be valid */ if (!ilk_validate_wm_level(display, 0 , &max, &pipe_wm->wm[0 ])) {"LP0 watermark invalid\n" );return false ;return true ;/* Compute new watermarks for the pipe */ static int ilk_compute_pipe_wm(struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_display *display = to_intel_display(state);struct intel_crtc_state *crtc_state =struct intel_pipe_wm *pipe_wm;struct intel_plane *plane;const struct intel_plane_state *plane_state;const struct intel_plane_state *pristate = NULL;const struct intel_plane_state *sprstate = NULL;const struct intel_plane_state *curstate = NULL;struct ilk_wm_maximums max;int level, usable_level;if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)else if (plane->base.type == DRM_PLANE_TYPE_OVERLAY)else if (plane->base.type == DRM_PLANE_TYPE_CURSOR)1 ;/* ILK/SNB: LP2+ watermarks only w/o sprites */ if (DISPLAY_VER(display) < 7 && pipe_wm->sprites_enabled)1 ;/* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ if (pipe_wm->sprites_scaled)0 ;0 , sizeof (pipe_wm->wm));0 , crtc_state,0 ]);if (!ilk_validate_pipe_wm(display, pipe_wm))return -EINVAL;1 , &max);for (level = 1 ; level <= usable_level; level++) {struct intel_wm_level *wm = &pipe_wm->wm[level];/* * Disable any watermark level that exceeds the * register maximums since such watermarks are * always invalid . if (!ilk_validate_wm_level(display, level, &max, wm)) {0 , sizeof (*wm));break ;return 0 ;/* * Build a set of ' intermediate ' watermark values that satisfy both the old * state and the new state . These can be programmed to the hardware * immediately . static int ilk_compute_intermediate_wm(struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_display *display = to_intel_display(crtc);struct intel_crtc_state *new_crtc_state =const struct intel_crtc_state *old_crtc_state =struct intel_pipe_wm *intermediate = &new_crtc_state->wm.ilk.intermediate;const struct intel_pipe_wm *optimal = &new_crtc_state->wm.ilk.optimal;const struct intel_pipe_wm *active = &old_crtc_state->wm.ilk.optimal;int level;/* * Start with the final , target watermarks , then combine with the * currently active watermarks to get values that are safe both before * and after the vblank . if (!new_crtc_state->hw.active ||return 0 ;for (level = 0 ; level < display->wm.num_levels; level++) {struct intel_wm_level *intermediate_wm = &intermediate->wm[level];const struct intel_wm_level *active_wm = &active->wm[level];/* * We need to make sure that these merged watermark values are * actually a valid configuration themselves . If they ' re not , * there ' s no safe way to transition from the old state to * the new state , so we need to fail the atomic transaction . if (!ilk_validate_pipe_wm(display, intermediate))return -EINVAL;/* * If our intermediate WM are identical to the final WM , then we can * omit the post - vblank programming ; only update if it ' s different . if (memcmp(intermediate, optimal, sizeof (*intermediate)) != 0 )true ;return 0 ;static int ilk_compute_watermarks(struct intel_atomic_state *state,struct intel_crtc *crtc)int ret;if (ret)return ret;if (ret)return ret;return 0 ;/* * Merge the watermarks from all active pipes for a specific level . static void ilk_merge_wm_level(struct intel_display *display,int level,struct intel_wm_level *ret_wm)const struct intel_crtc *crtc;true ;const struct intel_pipe_wm *active = &crtc->wm.active.ilk;const struct intel_wm_level *wm = &active->wm[level];if (!active->pipe_enabled)continue ;/* * The watermark values may have been used in the past , * so we must maintain them in the registers for some * time even if the level is now disabled . if (!wm->enable)false ;/* * Merge all low power watermarks for all active pipes . static void ilk_wm_merge(struct intel_display *display,const struct intel_wm_config *config,const struct ilk_wm_maximums *max,struct intel_pipe_wm *merged)int level, num_levels = display->wm.num_levels;int last_enabled_level = num_levels - 1 ;/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ if ((DISPLAY_VER(display) < 7 || display->platform.ivybridge) &&1 )0 ;/* ILK: FBC WM must be disabled always */ 6 ;/* merge each WM1+ level */ for (level = 1 ; level < num_levels; level++) {struct intel_wm_level *wm = &merged->wm[level];if (level > last_enabled_level)false ;else if (!ilk_validate_wm_level(display, level, max, wm))/* make sure all following levels get disabled */ 1 ;/* * The spec says it is preferred to disable * FBC WMs instead of disabling a WM level . if (wm->fbc_val > max->fbc) {if (wm->enable)false ;0 ;/* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ if (DISPLAY_VER(display) == 5 && HAS_FBC(display) &&for (level = 2 ; level < num_levels; level++) {struct intel_wm_level *wm = &merged->wm[level];false ;static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)/* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4 ].enable);/* The value we need to program into the WM_LPx latency field */ static unsigned int ilk_wm_lp_latency(struct intel_display *display,int level)if (display->platform.haswell || display->platform.broadwell)return 2 * level;else return display->wm.pri_latency[level];static void ilk_compute_wm_results(struct intel_display *display,const struct intel_pipe_wm *merged,enum intel_ddb_partitioning partitioning,struct ilk_wm_values *results)struct intel_crtc *crtc;int level, wm_lp;/* LP1+ register values */ for (wm_lp = 1 ; wm_lp <= 3 ; wm_lp++) {const struct intel_wm_level *r;/* * Maintain the watermark values even if the level is * disabled . Doing otherwise could cause underruns . 1 ] =if (r->enable)1 ] |= WM_LP_ENABLE;if (DISPLAY_VER(display) >= 8 )1 ] |= WM_LP_FBC_BDW(r->fbc_val);else 1 ] |= WM_LP_FBC_ILK(r->fbc_val);1 ] = WM_LP_SPRITE(r->spr_val);/* * Always set WM_LP_SPRITE_EN when spr_val ! = 0 , even if the * level is disabled . Doing otherwise could cause underruns . if (DISPLAY_VER(display) < 7 && r->spr_val) {1 );1 ] |= WM_LP_SPRITE_ENABLE;/* LP0 register values */ enum pipe pipe = crtc->pipe;const struct intel_pipe_wm *pipe_wm = &crtc->wm.active.ilk;const struct intel_wm_level *r = &pipe_wm->wm[0 ];if (drm_WARN_ON(display->drm, !r->enable))continue ;/* * Find the result with the highest level enabled . Check for enable_fbc_wm in * case both are at the same level . Prefer r1 in case they ' re the same . static struct intel_pipe_wm *struct intel_display *display,struct intel_pipe_wm *r1,struct intel_pipe_wm *r2)int level, level1 = 0 , level2 = 0 ;for (level = 1 ; level < display->wm.num_levels; level++) {if (r1->wm[level].enable)if (r2->wm[level].enable)if (level1 == level2) {if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)return r2;else return r1;else if (level1 > level2) {return r1;else {return r2;/* dirty bits used to track which watermarks need changes */ #define WM_DIRTY_PIPE(pipe) (1 << (pipe))#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1 ) | WM_DIRTY_LP(2 ) | WM_DIRTY_LP(3 ))#define WM_DIRTY_FBC (1 << 24 )#define WM_DIRTY_DDB (1 << 25 )static unsigned int ilk_compute_wm_dirty(struct intel_display *display,const struct ilk_wm_values *old,const struct ilk_wm_values *new )unsigned int dirty = 0 ;enum pipe pipe;int wm_lp;if (old->wm_pipe[pipe] != new ->wm_pipe[pipe]) {/* Must disable LP1+ watermarks too */ if (old->enable_fbc_wm != new ->enable_fbc_wm) {/* Must disable LP1+ watermarks too */ if (old->partitioning != new ->partitioning) {/* Must disable LP1+ watermarks too */ /* LP1+ watermarks already deemed dirty, no need to continue */ if (dirty & WM_DIRTY_LP_ALL)return dirty;/* Find the lowest numbered LP1+ watermark in need of an update... */ for (wm_lp = 1 ; wm_lp <= 3 ; wm_lp++) {if (old->wm_lp[wm_lp - 1 ] != new ->wm_lp[wm_lp - 1 ] ||1 ] != new ->wm_lp_spr[wm_lp - 1 ])break ;/* ...and mark it and all higher numbered LP1+ watermarks as dirty */ for (; wm_lp <= 3 ; wm_lp++)return dirty;static bool _ilk_disable_lp_wm(struct intel_display *display,unsigned int dirty)struct ilk_wm_values *previous = &display->wm.hw;bool changed = false ;if (dirty & WM_DIRTY_LP(3 ) && previous->wm_lp[2 ] & WM_LP_ENABLE) {2 ] &= ~WM_LP_ENABLE;2 ]);true ;if (dirty & WM_DIRTY_LP(2 ) && previous->wm_lp[1 ] & WM_LP_ENABLE) {1 ] &= ~WM_LP_ENABLE;1 ]);true ;if (dirty & WM_DIRTY_LP(1 ) && previous->wm_lp[0 ] & WM_LP_ENABLE) {0 ] &= ~WM_LP_ENABLE;0 ]);true ;/* * Don ' t touch WM_LP_SPRITE_ENABLE here . * Doing so could cause underruns . return changed;/* * The spec says we shouldn ' t write when we don ' t need , because every write * causes WMs to be re - evaluated , expending some power . static void ilk_write_wm_values(struct intel_display *display,struct ilk_wm_values *results)struct ilk_wm_values *previous = &display->wm.hw;unsigned int dirty;if (!dirty)return ;if (dirty & WM_DIRTY_PIPE(PIPE_A))0 ]);if (dirty & WM_DIRTY_PIPE(PIPE_B))1 ]);if (dirty & WM_DIRTY_PIPE(PIPE_C))2 ]);if (dirty & WM_DIRTY_DDB) {if (display->platform.haswell || display->platform.broadwell)0 :else 0 :if (dirty & WM_DIRTY_FBC)0 : DISP_FBC_WM_DIS);if (dirty & WM_DIRTY_LP(1 ) &&0 ] != results->wm_lp_spr[0 ])0 ]);if (DISPLAY_VER(display) >= 7 ) {if (dirty & WM_DIRTY_LP(2 ) && previous->wm_lp_spr[1 ] != results->wm_lp_spr[1 ])1 ]);if (dirty & WM_DIRTY_LP(3 ) && previous->wm_lp_spr[2 ] != results->wm_lp_spr[2 ])2 ]);if (dirty & WM_DIRTY_LP(1 ) && previous->wm_lp[0 ] != results->wm_lp[0 ])0 ]);if (dirty & WM_DIRTY_LP(2 ) && previous->wm_lp[1 ] != results->wm_lp[1 ])1 ]);if (dirty & WM_DIRTY_LP(3 ) && previous->wm_lp[2 ] != results->wm_lp[2 ])2 ]);bool ilk_disable_cxsr(struct intel_display *display)return _ilk_disable_lp_wm(display, WM_DIRTY_LP_ALL);static void ilk_compute_wm_config(struct intel_display *display,struct intel_wm_config *config)struct intel_crtc *crtc;/* Compute the currently _active_ config */ const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;if (!wm->pipe_enabled)continue ;static void ilk_program_watermarks(struct intel_display *display)struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;struct ilk_wm_maximums max;struct intel_wm_config config = {};struct ilk_wm_values results = {};enum intel_ddb_partitioning partitioning;1 , &config, INTEL_DDB_PART_1_2, &max);/* 5/6 split only in single pipe config on IVB+ */ if (DISPLAY_VER(display) >= 7 &&1 && config.sprites_enabled) {1 , &config, INTEL_DDB_PART_5_6, &max);else {static void ilk_initial_watermarks(struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_display *display = to_intel_display(crtc);const struct intel_crtc_state *crtc_state =static void ilk_optimize_watermarks(struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_display *display = to_intel_display(crtc);const struct intel_crtc_state *crtc_state =if (!crtc_state->wm.need_postvbl_update)return ;static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)struct intel_display *display = to_intel_display(crtc);struct ilk_wm_values *hw = &display->wm.hw;struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;enum pipe pipe = crtc->pipe;0 , sizeof (*active));if (active->pipe_enabled) {/* * For active pipes LP0 watermark is marked as * enabled , and LP1 + watermaks as disabled since * we can ' t really reverse compute them in case * multiple pipes are active . 0 ].enable = true ;0 ].pri_val = REG_FIELD_GET(WM0_PIPE_PRIMARY_MASK, tmp);0 ].spr_val = REG_FIELD_GET(WM0_PIPE_SPRITE_MASK, tmp);0 ].cur_val = REG_FIELD_GET(WM0_PIPE_CURSOR_MASK, tmp);else {int level;/* * For inactive pipes , all watermark levels * should be marked as enabled but zeroed , * which is what we ' d compute them to . for (level = 0 ; level < display->wm.num_levels; level++)true ;static int ilk_sanitize_watermarks_add_affected(struct drm_atomic_state *state)struct drm_plane *plane;struct intel_crtc *crtc;struct intel_crtc_state *crtc_state;if (IS_ERR(crtc_state))return PTR_ERR(crtc_state);if (crtc_state->hw.active) {/* * Preserve the inherited flag to avoid * taking the full modeset path . true ;struct drm_plane_state *plane_state;if (IS_ERR(plane_state))return PTR_ERR(plane_state);return 0 ;/* * Calculate what we think the watermarks should be for the state we ' ve read * out of the hardware and then immediately program those watermarks so that * we ensure the hardware settings match our internal state . * * We can calculate what we think WM ' s should be by creating a duplicate of the * current state ( which was constructed during hardware readout ) and running it * through the atomic check code to calculate new watermark values in the * state object . void ilk_wm_sanitize(struct intel_display *display)struct drm_atomic_state *state;struct intel_atomic_state *intel_state;struct intel_crtc *crtc;struct intel_crtc_state *crtc_state;struct drm_modeset_acquire_ctx ctx;int ret;int i;/* Only supported on platforms that use atomic watermark design */ if (!display->funcs.wm->optimize_watermarks)return ;if (drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 9 ))return ;if (drm_WARN_ON(display->drm, !state))return ;0 );true ;/* * Hardware readout is the only time we don ' t want to calculate * intermediate watermarks ( since we don ' t trust the current * watermarks ) . if (!HAS_GMCH(display))true ;if (ret)goto fail;if (ret)goto fail;/* Write calculated watermark values back */ true ;if (ret == -EDEADLK) {goto retry;/* * If we fail here , it means that the hardware appears to be * programmed in a way that shouldn ' t be possible , given our * understanding of watermark requirements . This might mean a * mistake in the hardware readout code or a mistake in the * watermark calculations for a given platform . Raise a WARN * so that this is noticeable . * * If this actually happens , we ' ll have to just leave the * BIOS - programmed watermarks untouched and hope for the best . "Could not determine valid watermarks for inherited state\n" );#define _FW_WM(value, plane) \## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)#define _FW_WM_VLV(value, plane) \## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)static void g4x_read_wm_values(struct intel_display *display,struct g4x_wm_values *wm)static void vlv_read_wm_values(struct intel_display *display,struct vlv_wm_values *wm)enum pipe pipe;0 )) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);1 )) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);if (display->platform.cherryview) {9 ;8 ;8 ;8 ;8 ;8 ;8 ;8 ;8 ;8 ;else {9 ;8 ;8 ;8 ;8 ;8 ;8 ;#undef _FW_WM#undef _FW_WM_VLVstatic void g4x_wm_get_hw_state(struct intel_display *display)struct g4x_wm_values *wm = &display->wm.g4x;struct intel_crtc *crtc;struct intel_crtc_state *crtc_state =struct g4x_wm_state *active = &crtc->wm.active.g4x;struct g4x_pipe_wm *raw;enum pipe pipe = crtc->pipe;enum plane_id plane_id;int level, max_level;if (wm->cxsr && wm->hpll_en)else if (wm->cxsr)else if (level > max_level)goto out;0 ;if (level > max_level)goto out;0 ;"Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n" ,"Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n" ,"Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n" ,"Initial SR=%s HPLL=%s FBC=%s\n" ,static void g4x_wm_sanitize(struct intel_display *display)struct intel_plane *plane;struct intel_crtc *crtc;struct intel_crtc *crtc =struct intel_crtc_state *crtc_state =struct intel_plane_state *plane_state =enum plane_id plane_id = plane->id;int level;if (plane_state->uapi.visible)continue ;for (level = 0 ; level < display->wm.num_levels; level++) {struct g4x_pipe_wm *raw =0 ;if (plane_id == PLANE_PRIMARY)0 ;struct intel_crtc_state *crtc_state =int ret;static void vlv_wm_get_hw_state(struct intel_display *display)struct vlv_wm_values *wm = &display->wm.vlv;struct intel_crtc *crtc;if (display->platform.cherryview) {if (val & DSP_MAXFIFO_PM5_ENABLE)/* * If DDR DVFS is disabled in the BIOS , Punit * will never ack the request . So if that happens * assume we don ' t have to enable / disable DDR DVFS * dynamically . To test that just set the REQ_ACK * bit to poke the Punit , but don ' t change the * HIGH / LOW bits so that we don ' t actually change * the current state . if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DDR_SETUP2) &0 , 3 )) {"Punit not acking DDR DVFS request, " "assuming DDR DVFS is disabled\n" );1 ;else {if ((val & FORCE_DDR_HIGH_FREQ) == 0 )struct intel_crtc_state *crtc_state =struct vlv_wm_state *active = &crtc->wm.active.vlv;const struct vlv_fifo_state *fifo_state =enum pipe pipe = crtc->pipe;enum plane_id plane_id;int level;1 ;for (level = 0 ; level < active->num_levels; level++) {struct g4x_pipe_wm *raw ="Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n" ,"Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n" ,static void vlv_wm_sanitize(struct intel_display *display)struct intel_plane *plane;struct intel_crtc *crtc;struct intel_crtc *crtc =struct intel_crtc_state *crtc_state =struct intel_plane_state *plane_state =enum plane_id plane_id = plane->id;int level;if (plane_state->uapi.visible)continue ;for (level = 0 ; level < display->wm.num_levels; level++) {struct g4x_pipe_wm *raw =0 ;struct intel_crtc_state *crtc_state =int ret;/* * FIXME should probably kill this and improve * the real watermark readout / sanitation instead static void ilk_init_lp_watermarks(struct intel_display *display)0 );0 );0 );/* * Don ' t touch WM_LP_SPRITE_ENABLE here . * Doing so could cause underruns . static void ilk_wm_get_hw_state(struct intel_display *display)struct ilk_wm_values *hw = &display->wm.hw;struct intel_crtc *crtc;0 ] = intel_de_read(display, WM1_LP_ILK);1 ] = intel_de_read(display, WM2_LP_ILK);2 ] = intel_de_read(display, WM3_LP_ILK);0 ] = intel_de_read(display, WM1S_LP_ILK);if (DISPLAY_VER(display) >= 7 ) {1 ] = intel_de_read(display, WM2S_LP_IVB);2 ] = intel_de_read(display, WM3S_LP_IVB);if (display->platform.haswell || display->platform.broadwell)else if (display->platform.ivybridge)static const struct intel_wm_funcs ilk_wm_funcs = {static const struct intel_wm_funcs vlv_wm_funcs = {static const struct intel_wm_funcs g4x_wm_funcs = {static const struct intel_wm_funcs pnv_wm_funcs = {static const struct intel_wm_funcs i965_wm_funcs = {static const struct intel_wm_funcs i9xx_wm_funcs = {static const struct intel_wm_funcs i845_wm_funcs = {static const struct intel_wm_funcs nop_funcs = {void i9xx_wm_init(struct intel_display *display)/* For FIFO watermark updates */ if (HAS_PCH_SPLIT(display)) {else if (display->platform.valleyview || display->platform.cherryview) {else if (display->platform.g4x) {else if (display->platform.pineview) {if (!pnv_get_cxsr_latency(display)) {"Unknown FSB/MEM, disabling CxSR\n" );/* Disable CxSR and never update its watermark again */ false );else {else if (DISPLAY_VER(display) == 4 ) {else if (DISPLAY_VER(display) == 3 ) {else if (DISPLAY_VER(display) == 2 ) {if (INTEL_NUM_PIPES(display) == 1 )else else {"unexpected fall-through in %s\n" , __func__);
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