/* * Copyright 2000 VA Linux Systems , Inc . , Sunnyvale , California . * All Rights Reserved . * * Permission is hereby granted , free of charge , to any person obtaining a * copy of this software and associated documentation files ( the " Software " ) , * to deal in the Software without restriction , including without limitation * the rights to use , copy , modify , merge , publish , distribute , sublicense , * and / or sell copies of the Software , and to permit persons to whom the * Software is furnished to do so , subject to the following conditions : * * The above copyright notice and this permission notice ( including the next * paragraph ) shall be included in all copies or substantial portions of the * Software . * * THE SOFTWARE IS PROVIDED " AS IS " , WITHOUT WARRANTY OF ANY KIND , EXPRESS OR * IMPLIED , INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY , * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT . IN NO EVENT SHALL * VA LINUX SYSTEMS AND / OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM , DAMAGES OR * OTHER LIABILITY , WHETHER IN AN ACTION OF CONTRACT , TORT OR OTHERWISE , * ARISING FROM , OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE . #include <drm/amdgpu_drm.h>#include <drm/clients/drm_client_setup.h>#include <drm/drm_drv.h>#include <drm/drm_fbdev_ttm.h>#include <drm/drm_gem.h>#include <drm/drm_managed.h>#include <drm/drm_pciids.h>#include <drm/drm_probe_helper.h>#include <drm/drm_vblank.h>#include <linux/cc_platform.h>#include <linux/dynamic_debug.h>#include <linux/module.h>#include <linux/mmu_notifier.h>#include <linux/pm_runtime.h>#include <linux/suspend.h>#include <linux/vga_switcheroo.h>#include "amdgpu.h" #include "amdgpu_amdkfd.h" #include "amdgpu_dma_buf.h" #include "amdgpu_drv.h" #include "amdgpu_fdinfo.h" #include "amdgpu_irq.h" #include "amdgpu_psp.h" #include "amdgpu_ras.h" #include "amdgpu_reset.h" #include "amdgpu_sched.h" #include "amdgpu_xgmi.h" #include "amdgpu_userq.h" #include "amdgpu_userq_fence.h" #include "../amdxcp/amdgpu_xcp_drv.h" /* * KMS wrapper . * - 3 . 0 . 0 - initial driver * - 3 . 1 . 0 - allow reading more status registers ( GRBM , SRBM , SDMA , CP ) * - 3 . 2 . 0 - GFX8 : Uses EOP_TC_WB_ACTION_EN , so UMDs don ' t have to do the same * at the end of IBs . * - 3 . 3 . 0 - Add VM support for UVD on supported hardware . * - 3 . 4 . 0 - Add AMDGPU_INFO_NUM_EVICTIONS . * - 3 . 5 . 0 - Add support for new UVD_NO_OP register . * - 3 . 6 . 0 - kmd involves use CONTEXT_CONTROL in ring buffer . * - 3 . 7 . 0 - Add support for VCE clock list packet * - 3 . 8 . 0 - Add support raster config init in the kernel * - 3 . 9 . 0 - Add support for memory query info about VRAM and GTT . * - 3 . 10 . 0 - Add support for new fences ioctl , new gem ioctl flags * - 3 . 11 . 0 - Add support for sensor query info ( clocks , temp , etc ) . * - 3 . 12 . 0 - Add query for double offchip LDS buffers * - 3 . 13 . 0 - Add PRT support * - 3 . 14 . 0 - Fix race in amdgpu_ctx_get_fence ( ) and note new functionality * - 3 . 15 . 0 - Export more gpu info for gfx9 * - 3 . 16 . 0 - Add reserved vmid support * - 3 . 17 . 0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS . * - 3 . 18 . 0 - Export gpu always on cu bitmap * - 3 . 19 . 0 - Add support for UVD MJPEG decode * - 3 . 20 . 0 - Add support for local BOs * - 3 . 21 . 0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl * - 3 . 22 . 0 - Add DRM_AMDGPU_SCHED ioctl * - 3 . 23 . 0 - Add query for VRAM lost counter * - 3 . 24 . 0 - Add high priority compute support for gfx9 * - 3 . 25 . 0 - Add support for sensor query info ( stable pstate sclk / mclk ) . * - 3 . 26 . 0 - GFX9 : Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE . * - 3 . 27 . 0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation . * - 3 . 28 . 0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES * - 3 . 29 . 0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID * - 3 . 30 . 0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE . * - 3 . 31 . 0 - Add support for per - flip tiling attribute changes with DC * - 3 . 32 . 0 - Add syncobj timeline support to AMDGPU_CS . * - 3 . 33 . 0 - Fixes for GDS ENOMEM failures in AMDGPU_CS . * - 3 . 34 . 0 - Non - DC can flip correctly between buffers with different pitches * - 3 . 35 . 0 - Add drm_amdgpu_info_device : : tcc_disabled_mask * - 3 . 36 . 0 - Allow reading more status registers on si / cik * - 3 . 37 . 0 - L2 is invalidated before SDMA IBs , needed for correctness * - 3 . 38 . 0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC * - 3 . 39 . 0 - DMABUF implicit sync does a full pipeline sync * - 3 . 40 . 0 - Add AMDGPU_IDS_FLAGS_TMZ * - 3 . 41 . 0 - Add video codec query * - 3 . 42 . 0 - Add 16 bpc fixed point display support * - 3 . 43 . 0 - Add device hot plug / unplug support * - 3 . 44 . 0 - DCN3 supports DCC independent block settings : ! 64 B & & 128 B , 64 B & &span> 128 B * - 3 . 45 . 0 - Add context ioctl stable pstate interface * - 3 . 46 . 0 - To enable hot plug amdgpu tests in libdrm * - 3 . 47 . 0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags * - 3 . 48 . 0 - Add IP discovery version info to HW INFO * - 3 . 49 . 0 - Add gang submit into CS IOCTL * - 3 . 50 . 0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock * 3 . 51 . 0 - Return the PCIe gen and lanes from the INFO ioctl * 3 . 52 . 0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD , add device_info fields : * tcp_cache_size , num_sqc_per_wgp , sqc_data_cache_size , sqc_inst_cache_size , * gl1c_cache_size , gl2c_cache_size , mall_size , enabled_rb_pipes_mask_hi * 3 . 53 . 0 - Support for GFX11 CP GFX shadowing * 3 . 54 . 0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support * - 3 . 55 . 0 - Add AMDGPU_INFO_GPUVM_FAULT query * - 3 . 56 . 0 - Update IB start address and size alignment for decode and encode * - 3 . 57 . 0 - Compute tunneling on GFX10 + * - 3 . 58 . 0 - Add GFX12 DCC support * - 3 . 59 . 0 - Cleared VRAM * - 3 . 60 . 0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE ( Vulkan requirement ) * - 3 . 61 . 0 - Contains fix for RV / PCO compute queues * - 3 . 62 . 0 - Add AMDGPU_IDS_FLAGS_MODE_PF , AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT * - 3 . 63 . 0 - GFX12 display DCC supports 256 B max compressed block size * - 3 . 64 . 0 - Userq IP support query #define KMS_DRIVER_MAJOR 3 #define KMS_DRIVER_MINOR 64 #define KMS_DRIVER_PATCHLEVEL 0 /* * amdgpu . debug module options . Are all disabled by default enum AMDGPU_DEBUG_MASK {0 ),1 ),2 ),3 ),4 ),5 ),6 ),7 ),8 ),9 )unsigned int amdgpu_vram_limit = UINT_MAX;int amdgpu_vis_vram_limit;int amdgpu_gart_size = -1 ; /* auto */ int amdgpu_gtt_size = -1 ; /* auto */ int amdgpu_moverate = -1 ; /* auto */ int amdgpu_audio = -1 ;int amdgpu_disp_priority;int amdgpu_hw_i2c;int amdgpu_pcie_gen2 = -1 ;int amdgpu_msi = -1 ;char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];int amdgpu_dpm = -1 ;int amdgpu_fw_load_type = -1 ;int amdgpu_aspm = -1 ;int amdgpu_runtime_pm = -1 ;0 xffffffff;int amdgpu_bapm = -1 ;int amdgpu_deep_color;int amdgpu_vm_size = -1 ;int amdgpu_vm_fragment_size = -1 ;int amdgpu_vm_block_size = -1 ;int amdgpu_vm_fault_stop;int amdgpu_vm_update_mode = -1 ;int amdgpu_exp_hw_support;int amdgpu_dc = -1 ;int amdgpu_sched_jobs = 32 ;int amdgpu_sched_hw_submission = 2 ;0 xffffffffffffffff;0 xffffffff;32 ;char *amdgpu_disable_cu;char *amdgpu_virtual_display;int amdgpu_enforce_isolation = -1 ;int amdgpu_modeset = -1 ;/* Specifies the default granularity for SVM, used in buffer * migration and restoration of backing memory when handling * recoverable page faults . * * The value is given as log ( numPages ( buffer ) ) ; for a 2 MiB * buffer it computes to be 9 9 ;/* * OverDrive ( bit 14 ) disabled by default * GFX DCS ( bit 19 ) disabled by default 0 xfff7bfff;int amdgpu_lbpw = -1 ;int amdgpu_compute_multipipe = -1 ;int amdgpu_gpu_recovery = -1 ; /* auto */ int amdgpu_emu_mode;int amdgpu_smu_pptable_id = -1 ;/* * FBC ( bit 0 ) disabled by default * MULTI_MON_PP_MCLK_SWITCH ( bit 1 ) enabled by default * - With this , for multiple monitors in sync ( e . g . with the same model ) , * mclk switching will be allowed . And the mclk will be not foced to the * highest . That helps saving some idle power . * DISABLE_FRACTIONAL_PWM ( bit 2 ) disabled by default * PSR ( bit 3 ) disabled by default * EDP NO POWER SEQUENCING ( bit 4 ) disabled by default 2 ;int amdgpu_async_gfx_ring = 1 ;int amdgpu_mcbp = -1 ;int amdgpu_discovery = -1 ;int amdgpu_mes;int amdgpu_mes_log_enable = 0 ;int amdgpu_mes_kiq;int amdgpu_uni_mes = 1 ;int amdgpu_noretry = -1 ;int amdgpu_force_asic_type = -1 ;int amdgpu_tmz = -1 ; /* auto */ int amdgpu_reset_method = -1 ; /* auto */ int amdgpu_num_kcq = -1 ;int amdgpu_smartshift_bias;int amdgpu_use_xgmi_p2p = 1 ;int amdgpu_vcnfw_log;int amdgpu_sg_display = -1 ; /* auto */ int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;int amdgpu_umsch_mm;int amdgpu_seamless = -1 ; /* auto */ int amdgpu_agp = -1 ; /* auto */ int amdgpu_wbrf = -1 ;int amdgpu_damage_clips = -1 ; /* auto */ int amdgpu_umsch_mm_fwlog;int amdgpu_rebar = -1 ; /* auto */ int amdgpu_user_queue = -1 ;0 ,"DRM_UT_CORE" ,"DRM_UT_DRIVER" ,"DRM_UT_KMS" ,"DRM_UT_PRIME" ,"DRM_UT_ATOMIC" ,"DRM_UT_VBL" ,"DRM_UT_STATE" ,"DRM_UT_LEASE" ,"DRM_UT_DP" ,"DRM_UT_DRMRES" );struct amdgpu_mgpu_info mgpu_info = {int amdgpu_ras_enable = -1 ;0 xffffffff;int amdgpu_bad_page_threshold = -1 ;struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {false ,0 x0, /* default to 0x0 (timeout disable) */ /** * DOC : vramlimit ( int ) * Restrict the total amount of VRAM in MiB for testing . The default is 0 ( Use full VRAM ) . "Restrict VRAM for testing, in megabytes" );int , 0600 );/** * DOC : vis_vramlimit ( int ) * Restrict the amount of CPU visible VRAM in MiB for testing . The default is 0 ( Use full CPU visible VRAM ) . "Restrict visible VRAM for testing, in megabytes" );int , 0444 );/** * DOC : gartsize ( uint ) * Restrict the size of GART ( for kernel use ) in Mib ( 32 , 64 , etc . ) for testing . * The default is - 1 ( The size depends on asic ) . "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)" );0600 );/** * DOC : gttsize ( int ) * Restrict the size of GTT domain ( for userspace use ) in MiB for testing . * The default is - 1 ( Use value specified by TTM ) . * This parameter is deprecated and will be removed in the future . "Size of the GTT userspace domain in megabytes (-1 = auto)" );int , 0600 );/** * DOC : moverate ( int ) * Set maximum buffer migration rate in MB / s . The default is - 1 ( 8 MB / s ) . "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)" );int , 0600 );/** * DOC : audio ( int ) * Set HDMI / DPAudio . Only affects non - DC display handling . The default is - 1 ( Enabled ) , set 0 to disabled it . "Audio enable (-1 = auto, 0 = disable, 1 = enable)" );int , 0444 );/** * DOC : disp_priority ( int ) * Set display Priority ( 1 = normal , 2 = high ) . Only affects non - DC display handling . The default is 0 ( auto ) . "Display Priority (0 = auto, 1 = normal, 2 = high)" );int , 0444 );/** * DOC : hw_i2c ( int ) * To enable hw i2c engine . Only affects non - DC display handling . The default is 0 ( Disabled ) . "hw i2c engine enable (0 = disable)" );int , 0444 );/** * DOC : pcie_gen2 ( int ) * To disable PCIE Gen2 / 3 mode ( 0 = disable , 1 = enable ) . The default is - 1 ( auto , enabled ) . "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)" );int , 0444 );/** * DOC : msi ( int ) * To disable Message Signaled Interrupts ( MSI ) functionality ( 1 = enable , 0 = disable ) . The default is - 1 ( auto , enabled ) . "MSI support (1 = enable, 0 = disable, -1 = auto)" );int , 0444 );/** * DOC : svm_default_granularity ( uint ) * Used in buffer migration and handling of recoverable page faults "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB" );0644 );/** * DOC : lockup_timeout ( string ) * Set GPU scheduler timeout value in ms . * * The format can be [ Non - Compute ] or [ GFX , Compute , SDMA , Video ] . That is there can be one or * multiple values specified . 0 and negative values are invalidated . They will be adjusted * to the default timeout . * * - With one value specified , the setting will apply to all non - compute jobs . * - With multiple values specified , the first one will be for GFX . * The second one is for Compute . The third and fourth ones are * for SDMA and Video . * * By default ( with no lockup_timeout settings ) , the timeout for all jobs is 10000 . "GPU lockup timeout in ms (default: 10000 for all jobs. " "0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]." );sizeof (amdgpu_lockup_timeout), 0444 );/** * DOC : dpm ( int ) * Override for dynamic power management setting * ( 0 = disable , 1 = enable ) * The default is - 1 ( auto ) . "DPM support (1 = enable, 0 = disable, -1 = auto)" );int , 0444 );/** * DOC : fw_load_type ( int ) * Set different firmware loading type for debugging , if supported . * Set to 0 to force direct loading if supported by the ASIC . Set * to - 1 to select the default loading mode for the ASIC , as defined * by the driver . The default is - 1 ( auto ) . "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)" );int , 0444 );/** * DOC : aspm ( int ) * To disable ASPM ( 1 = enable , 0 = disable ) . The default is - 1 ( auto , enabled ) . "ASPM support (1 = enable, 0 = disable, -1 = auto)" );int , 0444 );/** * DOC : runpm ( int ) * Override for runtime power management control for dGPUs . The amdgpu driver can dynamically power down * the dGPUs when they are idle if supported . The default is - 1 ( auto enable ) . * Setting the value to 0 disables this functionality . * Setting the value to - 2 is auto enabled with power down when displays are attached . "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)" );int , 0444 );/** * DOC : ip_block_mask ( uint ) * Override what IP blocks are enabled on the GPU . Each GPU is a collection of IP blocks ( gfx , display , video , etc . ) . * Use this parameter to disable specific blocks . Note that the IP blocks do not have a fixed index . Some asics may not have * some IPs or may include multiple instances of an IP so the ordering various from asic to asic . See the driver output in * the kernel log for the list of IPs on the asic . The default is 0 xffffffff ( enable all blocks on a device ) . "IP Block Mask (all blocks enabled (default))" );0444 );/** * DOC : bapm ( int ) * Bidirectional Application Power Management ( BAPM ) used to dynamically share TDP between CPU and GPU . Set value 0 to disable it . * The default - 1 ( auto , enabled ) "BAPM support (1 = enable, 0 = disable, -1 = auto)" );int , 0444 );/** * DOC : deep_color ( int ) * Set 1 to enable Deep Color support . Only affects non - DC display handling . The default is 0 ( disabled ) . "Deep Color support (1 = enable, 0 = disable (default))" );int , 0444 );/** * DOC : vm_size ( int ) * Override the size of the GPU ' s per client virtual address space in GiB . The default is - 1 ( automatic for each asic ) . "VM address space size in gigabytes (default 64GB)" );int , 0444 );/** * DOC : vm_fragment_size ( int ) * Override VM fragment size in bits ( 4 , 5 , etc . 4 = 64 K , 9 = 2 M ) . The default is - 1 ( automatic for each asic ) . "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)" );int , 0444 );/** * DOC : vm_block_size ( int ) * Override VM page table size in bits ( default depending on vm_size and hw setup ) . The default is - 1 ( automatic for each asic ) . "VM page table size in bits (default depending on vm_size)" );int , 0444 );/** * DOC : vm_fault_stop ( int ) * Stop on VM fault for debugging ( 0 = never , 1 = print first , 2 = always ) . The default is 0 ( No stop ) . "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)" );int , 0444 );/** * DOC : vm_update_mode ( int ) * Override VM update mode . VM updated by using CPU ( 0 = never , 1 = Graphics only , 2 = Compute only , 3 = Both ) . The default * is - 1 ( Only in large BAR ( LB ) systems Compute VM tables will be updated by CPU , otherwise 0 , never ) . "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both" );int , 0444 );/** * DOC : exp_hw_support ( int ) * Enable experimental hw support ( 1 = enable ) . The default is 0 ( disabled ) . "experimental hw support (1 = enable, 0 = disable (default))" );int , 0444 );/** * DOC : dc ( int ) * Disable / Enable Display Core driver for debugging ( 1 = enable , 0 = disable ) . The default is - 1 ( automatic for each asic ) . "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))" );int , 0444 );/** * DOC : sched_jobs ( int ) * Override the max number of jobs supported in the sw queue . The default is 32 . "the max number of jobs supported in the sw queue (default 32)" );int , 0444 );/** * DOC : sched_hw_submission ( int ) * Override the max number of HW submissions . The default is 2 . "the max number of HW submissions (default 2)" );int , 0444 );/** * DOC : ppfeaturemask ( hexint ) * Override power features enabled . See enum PP_FEATURE_MASK in drivers / gpu / drm / amd / include / amd_shared . h . * The default is the current set of stable power features . "all power features enabled (default))" );0444 );/** * DOC : forcelongtraining ( uint ) * Force long memory training in resume . * The default is zero , indicates short training in resume . "force memory long training" );0444 );/** * DOC : pcie_gen_cap ( uint ) * Override PCIE gen speed capabilities . See the CAIL flags in drivers / gpu / drm / amd / include / amd_pcie . h . * The default is 0 ( automatic for each asic ) . "PCIE Gen Caps (0: autodetect (default))" );0444 );/** * DOC : pcie_lane_cap ( uint ) * Override PCIE lanes capabilities . See the CAIL flags in drivers / gpu / drm / amd / include / amd_pcie . h . * The default is 0 ( automatic for each asic ) . "PCIE Lane Caps (0: autodetect (default))" );0444 );/** * DOC : cg_mask ( ullong ) * Override Clockgating features enabled on GPU ( 0 = disable clock gating ) . See the AMD_CG_SUPPORT flags in * drivers / gpu / drm / amd / include / amd_shared . h . The default is 0 xffffffffffffffff ( all enabled ) . "Clockgating flags mask (0 = disable clock gating)" );0444 );/** * DOC : pg_mask ( uint ) * Override Powergating features enabled on GPU ( 0 = disable power gating ) . See the AMD_PG_SUPPORT flags in * drivers / gpu / drm / amd / include / amd_shared . h . The default is 0 xffffffff ( all enabled ) . "Powergating flags mask (0 = disable power gating)" );0444 );/** * DOC : sdma_phase_quantum ( uint ) * Override SDMA context switch phase quantum ( x 1 K GPU clock cycles , 0 = no change ) . The default is 32 . "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))" );0444 );/** * DOC : disable_cu ( charp ) * Set to disable CUs ( It ' s set like se . sh . cu , . . . ) . The default is NULL . "Disable CUs (se.sh.cu,...)" );0444 );/** * DOC : virtual_display ( charp ) * Set to enable virtual display feature . This feature provides a virtual display hardware on headless boards * or in virtualized environments . It will be set like xxxx : xx : xx . x , x ; xxxx : xx : xx . x , x . It ' s the pci address of * the device , plus the number of crtcs to expose . E . g . , 0000 : 26 : 00 . 0 , 4 would enable 4 virtual crtcs on the pci * device at 26 : 00 . 0 . The default is NULL . "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)" );0444 );/** * DOC : lbpw ( int ) * Override Load Balancing Per Watt ( LBPW ) support ( 1 = enable , 0 = disable ) . The default is - 1 ( auto , enabled ) . "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)" );int , 0444 );"Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)" );int , 0444 );/** * DOC : gpu_recovery ( int ) * Set to enable GPU recovery mechanism ( 1 = enable , 0 = disable ) . The default is - 1 ( auto , disabled except SRIOV ) . "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)" );int , 0444 );/** * DOC : emu_mode ( int ) * Set value 1 to enable emulation mode . This is only needed when running on an emulator . The default is 0 ( disabled ) . "Emulation mode, (1 = enable, 0 = disable)" );int , 0444 );/** * DOC : ras_enable ( int ) * Enable RAS features on the GPU ( 0 = disable , 1 = enable , - 1 = auto ( default ) ) "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))" );int , 0444 );/** * DOC : ras_mask ( uint ) * Mask of RAS features to enable ( default 0 xffffffff ) , only valid when ras_enable = = 1 * See the flags in drivers / gpu / drm / amd / amdgpu / amdgpu_ras . h "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1" );0444 );/** * DOC : timeout_fatal_disable ( bool ) * Disable Watchdog timeout fatal error event "disable watchdog timeout fatal error (false = default)" );able, bool , 0644 );/** * DOC : timeout_period ( uint ) * Modify the watchdog timeout max_cycles as ( 1 < < period ) "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)" );0644 );/** * DOC : si_support ( int ) * Set SI support driver . This parameter works after set config CONFIG_DRM_AMDGPU_SI . For SI asic , when radeon driver is enabled , * set value 0 to use radeon driver , while set value 1 to use amdgpu driver . The default is using radeon driver when it available , * otherwise using amdgpu driver . #ifdef CONFIG_DRM_AMDGPU_SI#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)int amdgpu_si_support;"SI support (1 = enabled, 0 = disabled (default))" );#else int amdgpu_si_support = 1 ;"SI support (1 = enabled (default), 0 = disabled)" );#endif int , 0444 );#endif /** * DOC : cik_support ( int ) * Set CIK support driver . This parameter works after set config CONFIG_DRM_AMDGPU_CIK . For CIK asic , when radeon driver is enabled , * set value 0 to use radeon driver , while set value 1 to use amdgpu driver . The default is using radeon driver when it available , * otherwise using amdgpu driver . #ifdef CONFIG_DRM_AMDGPU_CIK#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)int amdgpu_cik_support;"CIK support (1 = enabled, 0 = disabled (default))" );#else int amdgpu_cik_support = 1 ;"CIK support (1 = enabled (default), 0 = disabled)" );#endif int , 0444 );#endif /** * DOC : smu_memory_pool_size ( uint ) * It is used to reserve gtt for smu debug usage , setting value 0 to disable it . The actual size is value * 256 MiB . * E . g . 0 x1 = 256 Mbyte , 0 x2 = 512 Mbyte , 0 x4 = 1 Gbyte , 0 x8 = 2 GByte . The default is 0 ( disabled ) . "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte" );0444 );/** * DOC : async_gfx_ring ( int ) * It is used to enable gfx rings that could be configured with different prioritites or equal priorities "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))" );int , 0444 );/** * DOC : mcbp ( int ) * It is used to enable mid command buffer preemption . ( 0 = disabled , 1 = enabled , - 1 auto ( default ) ) "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)" );int , 0444 );/** * DOC : discovery ( int ) * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM . * ( - 1 = auto ( default ) , 0 = disabled , 1 = enabled , 2 = use ip_discovery table from file ) "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM" );int , 0444 );/** * DOC : mes ( int ) * Enable Micro Engine Scheduler . This is a new hw scheduling engine for gfx , sdma , and compute . * ( 0 = disabled ( default ) , 1 = enabled ) "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)" );int , 0444 );/** * DOC : mes_log_enable ( int ) * Enable Micro Engine Scheduler log . This is used to enable / disable MES internal log . * ( 0 = disabled ( default ) , 1 = enabled ) "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)" );int , 0444 );/** * DOC : mes_kiq ( int ) * Enable Micro Engine Scheduler KIQ . This is a new engine pipe for kiq . * ( 0 = disabled ( default ) , 1 = enabled ) "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)" );int , 0444 );/** * DOC : uni_mes ( int ) * Enable Unified Micro Engine Scheduler . This is a new engine pipe for unified scheduler . * ( 0 = disabled ( default ) , 1 = enabled ) "Enable Unified Micro Engine Scheduler (0 = disabled, 1 = enabled(default)" );int , 0444 );/** * DOC : noretry ( int ) * Disable XNACK retry in the SQ by default on GFXv9 hardware . On ASICs that * do not support per - process XNACK this also disables retry page faults . * ( 0 = retry enabled , 1 = retry disabled , - 1 auto ( default ) ) "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))" );int , 0644 );/** * DOC : force_asic_type ( int ) * A non negative value used to specify the asic type for all supported GPUs . "A non negative value used to specify the asic type for all supported GPUs" );int , 0444 );/** * DOC : use_xgmi_p2p ( int ) * Enables / disables XGMI P2P interface ( 0 = disable , 1 = enable ) . "Enable XGMI P2P interface (0 = disable; 1 = enable (default))" );int , 0444 );#ifdef CONFIG_HSA_AMD/** * DOC : sched_policy ( int ) * Set scheduling policy . Default is HWS ( hardware scheduling ) with over - subscription . * Setting 1 disables over - subscription . Setting 2 disables HWS and statically * assigns queues to HQDs . int sched_policy = KFD_SCHED_POLICY_HWS;int , 0444 );"Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)" );/** * DOC : hws_max_conc_proc ( int ) * Maximum number of processes that HWS can schedule concurrently . The maximum is the * number of VMIDs assigned to the HWS , which is also the default . int hws_max_conc_proc = -1 ;int , 0444 );"Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))" );/** * DOC : cwsr_enable ( int ) * CWSR ( compute wave store and resume ) allows the GPU to preempt shader execution in * the middle of a compute wave . Default is 1 to enable this feature . Setting 0 * disables it . int cwsr_enable = 1 ;int , 0444 );"CWSR enable (0 = Off, 1 = On (Default))" );/** * DOC : max_num_of_queues_per_device ( int ) * Maximum number of queues per device . Valid setting is between 1 and 4096 . Default * is 4096 . int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;int , 0444 );"Maximum number of supported queues per device (1 = Minimum, 4096 = default)" );/** * DOC : send_sigterm ( int ) * Send sigterm to HSA process on unhandled exceptions . Default is not to send sigterm * but just print errors on dmesg . Setting 1 enables sending sigterm . int send_sigterm;int , 0444 );"Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)" );/** * DOC : halt_if_hws_hang ( int ) * Halt if HWS hang is detected . Default value , 0 , disables the halt on hang . * Setting 1 enables halt on hang . int halt_if_hws_hang;int , 0644 );"Halt if HWS hang is detected (0 = off (default), 1 = on)" );/** * DOC : hws_gws_support ( bool ) * Assume that HWS supports GWS barriers regardless of what firmware version * check says . Default value : false ( rely on MEC2 firmware version check ) . bool hws_gws_support;bool , 0444 );"Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)" );/** * DOC : queue_preemption_timeout_ms ( int ) * queue preemption timeout in ms ( 1 = Minimum , 9000 = default ) int queue_preemption_timeout_ms = 9000 ;int , 0644 );"queue preemption timeout in ms (1 = Minimum, 9000 = default)" );/** * DOC : debug_evictions ( bool ) * Enable extra debug messages to help determine the cause of evictions bool debug_evictions;bool , 0644 );"enable eviction debug messages (false = default)" );/** * DOC : no_system_mem_limit ( bool ) * Disable system memory limit , to support multiple process shared memory bool no_system_mem_limit;bool , 0644 );"disable system memory limit (false = default)" );/** * DOC : no_queue_eviction_on_vm_fault ( int ) * If set , process queues will not be evicted on gpuvm fault . This is to keep the wavefront context for debugging ( 0 = queue eviction , 1 = no queue eviction ) . The default is 0 ( queue eviction ) . int amdgpu_no_queue_eviction_on_vm_fault;"No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)" );_on_vm_fault, int , 0444 );#endif /** * DOC : mtype_local ( int ) int amdgpu_mtype_local;"MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)" );int , 0444 );/** * DOC : pcie_p2p ( bool ) * Enable PCIe P2P ( requires large - BAR ) . Default value : true ( on ) #ifdef CONFIG_HSA_AMD_P2Pbool pcie_p2p = true ;bool , 0444 );"Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))" );#endif /** * DOC : dcfeaturemask ( uint ) * Override display features enabled . See enum DC_FEATURE_MASK in drivers / gpu / drm / amd / include / amd_shared . h . * The default is the current set of stable display features . "all stable DC features enabled (default))" );0444 );/** * DOC : dcdebugmask ( uint ) * Override display features enabled . See enum DC_DEBUG_MASK in drivers / gpu / drm / amd / include / amd_shared . h . "all debug options disabled (default))" );0444 );"Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)" );0444 );/** * DOC : abmlevel ( uint ) * Override the default ABM ( Adaptive Backlight Management ) level used for DC * enabled hardware . Requires DMCU to be supported and loaded . * Valid levels are 0 - 4 . A value of 0 indicates that ABM should be disabled by * default . Values 1 - 4 control the maximum allowable brightness reduction via * the ABM algorithm , with 1 being the least reduction and 4 being the most * reduction . * * Defaults to - 1 , or auto . Userspace can only override this level after * boot if it ' s set to auto . int amdgpu_dm_abm_level = -1 ;"ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))" );int , 0444 );int amdgpu_backlight = -1 ;"Backlight control (0 = pwm, 1 = aux, -1 auto (default))" );0444 );/** * DOC : damageclips ( int ) * Enable or disable damage clips support . If damage clips support is disabled , * we will force full frame updates , irrespective of what user space sends to * us . * * Defaults to - 1 ( where it is enabled unless a PSR - SU display is detected ) . "Damage clips support (0 = disable, 1 = enable, -1 auto (default))" );int , 0444 );/** * DOC : tmz ( int ) * Trusted Memory Zone ( TMZ ) is a method to protect data being written * to or read from memory . * * The default value : 0 ( off ) . TODO : change to auto till it is completed . "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)" );int , 0444 );/** * DOC : freesync_video ( uint ) * Enable the optimization to adjust front porch timing to achieve seamless * mode change experience when setting a freesync supported mode for which full * modeset is not needed . * * The Display Core will add a set of modes derived from the base FreeSync * video mode into the corresponding connector ' s mode list based on commonly * used refresh rates and VRR range of the connected display , when users enable * this feature . From the userspace perspective , they can see a seamless mode * change experience when the change between different refresh rates under the * same resolution . Additionally , userspace applications such as Video playback * can read this modeset list and change the refresh rate based on the video * frame rate . Finally , the userspace can also derive an appropriate mode for a * particular refresh rate based on the FreeSync Mode and add it to the * connector ' s mode list . * * Note : This is an experimental feature . * * The default value : 0 ( off ) . "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)" );0444 );/** * DOC : reset_method ( int ) * GPU reset method ( - 1 = auto ( default ) , 0 = legacy , 1 = mode0 , 2 = mode1 , 3 = mode2 , 4 = baco ) "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)" );int , 0644 );/** * DOC : bad_page_threshold ( int ) Bad page threshold is specifies the * threshold value of faulty pages detected by RAS ECC , which may * result in the GPU entering bad status when the number of total * faulty pages by ECC exceeds the threshold value . "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determined by a formula, 0 < threshold < max records, user-defined threshold)" );int , 0444 );"number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)" );int , 0444 );/** * DOC : vcnfw_log ( int ) * Enable vcnfw log output for debugging , the default is disabled . "Enable vcnfw log(0 = disable (default value), 1 = enable)" );int , 0444 );/** * DOC : sg_display ( int ) * Disable S / G ( scatter / gather ) display ( i . e . , display from system memory ) . * This option is only relevant on APUs . Set this option to 0 to disable * S / G display if you experience flickering or other issues under memory * pressure and report the issue . "S/G Display (-1 = auto (default), 0 = disable)" );int , 0444 );/** * DOC : umsch_mm ( int ) * Enable Multi Media User Mode Scheduler . This is a HW scheduling engine for VCN and VPE . * ( 0 = disabled ( default ) , 1 = enabled ) "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)" );int , 0444 );/** * DOC : umsch_mm_fwlog ( int ) * Enable umschfw log output for debugging , the default is disabled . "Enable umschfw log(0 = disable (default value), 1 = enable)" );int , 0444 );/** * DOC : smu_pptable_id ( int ) * Used to override pptable id . id = 0 use VBIOS pptable . * id > 0 use the soft pptable with specicfied id . "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)" );int , 0444 );/** * DOC : partition_mode ( int ) * Used to override the default SPX mode . "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 0 = AMDGPU_SPX_PARTITION_MODE, \1 = AMDGPU_DPX_PARTITION_MODE, \2 = AMDGPU_TPX_PARTITION_MODE, \3 = AMDGPU_QPX_PARTITION_MODE, \4 = AMDGPU_CPX_PARTITION_MODE)"); 0444 );/** * DOC : enforce_isolation ( int ) * enforce process isolation between graphics and compute . * ( - 1 = auto , 0 = disable , 1 = enable , 2 = enable legacy mode , 3 = enable without cleaner shader ) int , 0444 );"enforce process isolation between graphics and compute. (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)" );/** * DOC : modeset ( int ) * Override nomodeset ( 1 = override , - 1 = auto ) . The default is - 1 ( auto ) . "Override nomodeset (1 = enable, -1 = auto)" );int , 0444 );/** * DOC : seamless ( int ) * Seamless boot will keep the image on the screen during the boot process . "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)" );int , 0444 );/** * DOC : debug_mask ( uint ) * Debug options for amdgpu , work as a binary mask with the following options : * * - 0 x1 : Debug VM handling * - 0 x2 : Enable simulating large - bar capability on non - large bar system . This * limits the VRAM size reported to ROCm applications to the visible * size , usually 256 MB . * - 0 x4 : Disable GPU soft recovery , always do a full reset * - 0 x8 : Use VRAM for firmware loading * - 0 x10 : Enable ACA based RAS logging * - 0 x20 : Enable experimental resets * - 0 x40 : Disable ring resets * - 0 x80 : Use VRAM for SMU pool "debug options for amdgpu, disabled by default" );0444 );/** * DOC : agp ( int ) * Enable the AGP aperture . This provides an aperture in the GPU ' s internal * address space for direct access to system memory . Note that these accesses * are non - snooped , so they are only used for access to uncached memory . "AGP (-1 = auto (default), 0 = disable, 1 = enable)" );int , 0444 );/** * DOC : wbrf ( int ) * Enable Wifi RFI interference mitigation feature . * Due to electrical and mechanical constraints there may be likely interference of * relatively high - powered harmonics of the ( G - ) DDR memory clocks with local radio * module frequency bands used by Wifi 6 / 6 e / 7 . To mitigate the possible RFI interference , * with this feature enabled , PMFW will use either “ shadowed P - State ” or “ P - State ” based * on active list of frequencies in - use ( to be avoided ) as part of initial setting or * P - state transition . However , there may be potential performance impact with this * feature enabled . * ( 0 = disabled , 1 = enabled , - 1 = auto ( default setting , will be enabled if supported ) ) "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)" );int , 0444 );/** * DOC : rebar ( int ) * Allow BAR resizing . Disable this to prevent the driver from attempting * to resize the BAR if the GPU supports it and there is available MMIO space . * Note that this just prevents the driver from resizing the BAR . The BIOS * may have already resized the BAR at boot time . "Resizable BAR (-1 = auto (default), 0 = disable, 1 = enable)" );int , 0444 );/** * DOC : user_queue ( int ) * Enable user queues on systems that support user queues . Possible values : * * - - 1 = auto ( ASIC specific default ) * - 0 = user queues disabled * - 1 = user queues enabled and kernel queues enabled ( if supported ) * - 2 = user queues enabled and kernel queues disabled "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)" );int , 0444 );/* These devices are not supported by amdgpu. * They are supported by the mach64 , r128 , radeon drivers static const u16 amdgpu_unsupported_pciidlist[] = {/* mach64 */ 0 x4354,0 x4358,0 x4554,0 x4742,0 x4744,0 x4749,0 x474C,0 x474D,0 x474E,0 x474F,0 x4750,0 x4751,0 x4752,0 x4753,0 x4754,0 x4755,0 x4756,0 x4757,0 x4758,0 x4759,0 x475A,0 x4C42,0 x4C44,0 x4C47,0 x4C49,0 x4C4D,0 x4C4E,0 x4C50,0 x4C51,0 x4C52,0 x4C53,0 x5654,0 x5655,0 x5656,/* r128 */ 0 x4c45,0 x4c46,0 x4d46,0 x4d4c,0 x5041,0 x5042,0 x5043,0 x5044,0 x5045,0 x5046,0 x5047,0 x5048,0 x5049,0 x504A,0 x504B,0 x504C,0 x504D,0 x504E,0 x504F,0 x5050,0 x5051,0 x5052,0 x5053,0 x5054,0 x5055,0 x5056,0 x5057,0 x5058,0 x5245,0 x5246,0 x5247,0 x524b,0 x524c,0 x534d,0 x5446,0 x544C,0 x5452,/* radeon */ 0 x3150,0 x3151,0 x3152,0 x3154,0 x3155,0 x3E50,0 x3E54,0 x4136,0 x4137,0 x4144,0 x4145,0 x4146,0 x4147,0 x4148,0 x4149,0 x414A,0 x414B,0 x4150,0 x4151,0 x4152,0 x4153,0 x4154,0 x4155,0 x4156,0 x4237,0 x4242,0 x4336,0 x4337,0 x4437,0 x4966,0 x4967,0 x4A48,0 x4A49,0 x4A4A,0 x4A4B,0 x4A4C,0 x4A4D,0 x4A4E,0 x4A4F,0 x4A50,0 x4A54,0 x4B48,0 x4B49,0 x4B4A,0 x4B4B,0 x4B4C,0 x4C57,0 x4C58,0 x4C59,0 x4C5A,0 x4C64,0 x4C66,0 x4C67,0 x4E44,0 x4E45,0 x4E46,0 x4E47,0 x4E48,0 x4E49,0 x4E4A,0 x4E4B,0 x4E50,0 x4E51,0 x4E52,0 x4E53,0 x4E54,0 x4E56,0 x5144,0 x5145,0 x5146,0 x5147,0 x5148,0 x514C,0 x514D,0 x5157,0 x5158,0 x5159,0 x515A,0 x515E,0 x5460,0 x5462,0 x5464,0 x5548,0 x5549,0 x554A,0 x554B,0 x554C,0 x554D,0 x554E,0 x554F,0 x5550,0 x5551,0 x5552,0 x5554,0 x564A,0 x564B,0 x564F,0 x5652,0 x5653,0 x5657,0 x5834,0 x5835,0 x5954,0 x5955,0 x5974,0 x5975,0 x5960,0 x5961,0 x5962,0 x5964,0 x5965,0 x5969,0 x5a41,0 x5a42,0 x5a61,0 x5a62,0 x5b60,0 x5b62,0 x5b63,0 x5b64,0 x5b65,0 x5c61,0 x5c63,0 x5d48,0 x5d49,0 x5d4a,0 x5d4c,0 x5d4d,0 x5d4e,0 x5d4f,0 x5d50,0 x5d52,0 x5d57,0 x5e48,0 x5e4a,0 x5e4b,0 x5e4c,0 x5e4d,0 x5e4f,0 x6700,0 x6701,0 x6702,0 x6703,0 x6704,0 x6705,0 x6706,0 x6707,0 x6708,0 x6709,0 x6718,0 x6719,0 x671c,0 x671d,0 x671f,0 x6720,0 x6721,0 x6722,0 x6723,0 x6724,0 x6725,0 x6726,0 x6727,0 x6728,0 x6729,0 x6738,0 x6739,0 x673e,0 x6740,0 x6741,0 x6742,0 x6743,0 x6744,0 x6745,0 x6746,0 x6747,0 x6748,0 x6749,0 x674A,0 x6750,0 x6751,0 x6758,0 x6759,0 x675B,0 x675D,0 x675F,0 x6760,0 x6761,0 x6762,0 x6763,0 x6764,0 x6765,0 x6766,0 x6767,0 x6768,0 x6770,0 x6771,0 x6772,0 x6778,0 x6779,0 x677B,0 x6840,0 x6841,0 x6842,0 x6843,0 x6849,0 x684C,0 x6850,0 x6858,0 x6859,0 x6880,0 x6888,0 x6889,0 x688A,0 x688C,0 x688D,0 x6898,0 x6899,0 x689b,0 x689c,0 x689d,0 x689e,0 x68a0,0 x68a1,0 x68a8,0 x68a9,0 x68b0,0 x68b8,0 x68b9,0 x68ba,0 x68be,0 x68bf,0 x68c0,0 x68c1,0 x68c7,0 x68c8,0 x68c9,0 x68d8,0 x68d9,0 x68da,0 x68de,0 x68e0,0 x68e1,0 x68e4,0 x68e5,0 x68e8,0 x68e9,0 x68f1,0 x68f2,0 x68f8,0 x68f9,0 x68fa,0 x68fe,0 x7100,0 x7101,0 x7102,0 x7103,0 x7104,0 x7105,0 x7106,0 x7108,0 x7109,0 x710A,0 x710B,0 x710C,0 x710E,0 x710F,0 x7140,0 x7141,0 x7142,0 x7143,0 x7144,0 x7145,0 x7146,0 x7147,0 x7149,0 x714A,0 x714B,0 x714C,0 x714D,0 x714E,0 x714F,0 x7151,0 x7152,0 x7153,0 x715E,0 x715F,0 x7180,0 x7181,0 x7183,0 x7186,0 x7187,0 x7188,0 x718A,0 x718B,0 x718C,0 x718D,0 x718F,0 x7193,0 x7196,0 x719B,0 x719F,0 x71C0,0 x71C1,0 x71C2,0 x71C3,0 x71C4,0 x71C5,0 x71C6,0 x71C7,0 x71CD,0 x71CE,0 x71D2,0 x71D4,0 x71D5,0 x71D6,0 x71DA,0 x71DE,0 x7200,0 x7210,0 x7211,0 x7240,0 x7243,0 x7244,0 x7245,0 x7246,0 x7247,0 x7248,0 x7249,0 x724A,0 x724B,0 x724C,0 x724D,0 x724E,0 x724F,0 x7280,0 x7281,0 x7283,0 x7284,0 x7287,0 x7288,0 x7289,0 x728B,0 x728C,0 x7290,0 x7291,0 x7293,0 x7297,0 x7834,0 x7835,0 x791e,0 x791f,0 x793f,0 x7941,0 x7942,0 x796c,0 x796d,0 x796e,0 x796f,0 x9400,0 x9401,0 x9402,0 x9403,0 x9405,0 x940A,0 x940B,0 x940F,0 x94A0,0 x94A1,0 x94A3,0 x94B1,0 x94B3,0 x94B4,0 x94B5,0 x94B9,0 x9440,0 x9441,0 x9442,0 x9443,0 x9444,0 x9446,0 x944A,0 x944B,0 x944C,0 x944E,0 x9450,0 x9452,0 x9456,0 x945A,0 x945B,0 x945E,0 x9460,0 x9462,0 x946A,0 x946B,0 x947A,0 x947B,0 x9480,0 x9487,0 x9488,0 x9489,0 x948A,0 x948F,0 x9490,0 x9491,0 x9495,0 x9498,0 x949C,0 x949E,0 x949F,0 x94C0,0 x94C1,0 x94C3,0 x94C4,0 x94C5,0 x94C6,0 x94C7,0 x94C8,0 x94C9,0 x94CB,0 x94CC,0 x94CD,0 x9500,0 x9501,0 x9504,0 x9505,0 x9506,0 x9507,0 x9508,0 x9509,0 x950F,0 x9511,0 x9515,0 x9517,0 x9519,0 x9540,0 x9541,0 x9542,0 x954E,0 x954F,0 x9552,0 x9553,0 x9555,0 x9557,0 x955f,0 x9580,0 x9581,0 x9583,0 x9586,0 x9587,0 x9588,0 x9589,0 x958A,0 x958B,0 x958C,0 x958D,0 x958E,0 x958F,0 x9590,0 x9591,0 x9593,0 x9595,0 x9596,0 x9597,0 x9598,0 x9599,0 x959B,0 x95C0,0 x95C2,0 x95C4,0 x95C5,0 x95C6,0 x95C7,0 x95C9,0 x95CC,0 x95CD,0 x95CE,0 x95CF,0 x9610,0 x9611,0 x9612,0 x9613,0 x9614,0 x9615,0 x9616,0 x9640,0 x9641,0 x9642,0 x9643,0 x9644,0 x9645,0 x9647,0 x9648,0 x9649,0 x964a,0 x964b,0 x964c,0 x964e,0 x964f,0 x9710,0 x9711,0 x9712,0 x9713,0 x9714,0 x9715,0 x9802,0 x9803,0 x9804,0 x9805,0 x9806,0 x9807,0 x9808,0 x9809,0 x980A,0 x9900,0 x9901,0 x9903,0 x9904,0 x9905,0 x9906,0 x9907,0 x9908,0 x9909,0 x990A,0 x990B,0 x990C,0 x990D,0 x990E,0 x990F,0 x9910,0 x9913,0 x9917,0 x9918,0 x9919,0 x9990,0 x9991,0 x9992,0 x9993,0 x9994,0 x9995,0 x9996,0 x9997,0 x9998,0 x9999,0 x999A,0 x999B,0 x999C,0 x999D,0 x99A0,0 x99A2,0 x99A4,/* radeon secondary ids */ 0 x3171,0 x3e70,0 x4164,0 x4165,0 x4166,0 x4168,0 x4170,0 x4171,0 x4172,0 x4173,0 x496e,0 x4a69,0 x4a6a,0 x4a6b,0 x4a70,0 x4a74,0 x4b69,0 x4b6b,0 x4b6c,0 x4c6e,0 x4e64,0 x4e65,0 x4e66,0 x4e67,0 x4e68,0 x4e69,0 x4e6a,0 x4e71,0 x4f73,0 x5569,0 x556b,0 x556d,0 x556f,0 x5571,0 x5854,0 x5874,0 x5940,0 x5941,0 x5b70,0 x5b72,0 x5b73,0 x5b74,0 x5b75,0 x5d44,0 x5d45,0 x5d6d,0 x5d6f,0 x5d72,0 x5d77,0 x5e6b,0 x5e6d,0 x7120,0 x7124,0 x7129,0 x712e,0 x712f,0 x7162,0 x7163,0 x7166,0 x7167,0 x7172,0 x7173,0 x71a0,0 x71a1,0 x71a3,0 x71a7,0 x71bb,0 x71e0,0 x71e1,0 x71e2,0 x71e6,0 x71e7,0 x71f2,0 x7269,0 x726b,0 x726e,0 x72a0,0 x72a8,0 x72b1,0 x72b3,0 x793f,static const struct pci_device_id pciidlist[] = {0 x1002, 0 x6780, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TAHITI},0 x1002, 0 x6784, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TAHITI},0 x1002, 0 x6788, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TAHITI},0 x1002, 0 x678A, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TAHITI},0 x1002, 0 x6790, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TAHITI},0 x1002, 0 x6791, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TAHITI},0 x1002, 0 x6792, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TAHITI},0 x1002, 0 x6798, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TAHITI},0 x1002, 0 x6799, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TAHITI},0 x1002, 0 x679A, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TAHITI},0 x1002, 0 x679B, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TAHITI},0 x1002, 0 x679E, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TAHITI},0 x1002, 0 x679F, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TAHITI},0 x1002, 0 x6800, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_PITCAIRN|AMD_IS_MOBILITY},0 x1002, 0 x6801, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_PITCAIRN|AMD_IS_MOBILITY},0 x1002, 0 x6802, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_PITCAIRN|AMD_IS_MOBILITY},0 x1002, 0 x6806, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_PITCAIRN},0 x1002, 0 x6808, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_PITCAIRN},0 x1002, 0 x6809, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_PITCAIRN},0 x1002, 0 x6810, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_PITCAIRN},0 x1002, 0 x6811, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_PITCAIRN},0 x1002, 0 x6816, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_PITCAIRN},0 x1002, 0 x6817, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_PITCAIRN},0 x1002, 0 x6818, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_PITCAIRN},0 x1002, 0 x6819, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_PITCAIRN},0 x1002, 0 x6600, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_OLAND|AMD_IS_MOBILITY},0 x1002, 0 x6601, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_OLAND|AMD_IS_MOBILITY},0 x1002, 0 x6602, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_OLAND|AMD_IS_MOBILITY},0 x1002, 0 x6603, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_OLAND|AMD_IS_MOBILITY},0 x1002, 0 x6604, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_OLAND|AMD_IS_MOBILITY},0 x1002, 0 x6605, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_OLAND|AMD_IS_MOBILITY},0 x1002, 0 x6606, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_OLAND|AMD_IS_MOBILITY},0 x1002, 0 x6607, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_OLAND|AMD_IS_MOBILITY},0 x1002, 0 x6608, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_OLAND},0 x1002, 0 x6610, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_OLAND},0 x1002, 0 x6611, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_OLAND},0 x1002, 0 x6613, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_OLAND},0 x1002, 0 x6617, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_OLAND|AMD_IS_MOBILITY},0 x1002, 0 x6620, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_OLAND|AMD_IS_MOBILITY},0 x1002, 0 x6621, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_OLAND|AMD_IS_MOBILITY},0 x1002, 0 x6623, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_OLAND|AMD_IS_MOBILITY},0 x1002, 0 x6631, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_OLAND},0 x1002, 0 x6820, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE|AMD_IS_MOBILITY},0 x1002, 0 x6821, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE|AMD_IS_MOBILITY},0 x1002, 0 x6822, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE|AMD_IS_MOBILITY},0 x1002, 0 x6823, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE|AMD_IS_MOBILITY},0 x1002, 0 x6824, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE|AMD_IS_MOBILITY},0 x1002, 0 x6825, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE|AMD_IS_MOBILITY},0 x1002, 0 x6826, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE|AMD_IS_MOBILITY},0 x1002, 0 x6827, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE|AMD_IS_MOBILITY},0 x1002, 0 x6828, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE},0 x1002, 0 x6829, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE},0 x1002, 0 x682A, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE|AMD_IS_MOBILITY},0 x1002, 0 x682B, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE|AMD_IS_MOBILITY},0 x1002, 0 x682C, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE},0 x1002, 0 x682D, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE|AMD_IS_MOBILITY},0 x1002, 0 x682F, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE|AMD_IS_MOBILITY},0 x1002, 0 x6830, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE|AMD_IS_MOBILITY},0 x1002, 0 x6831, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE|AMD_IS_MOBILITY},0 x1002, 0 x6835, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE},0 x1002, 0 x6837, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE},0 x1002, 0 x6838, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE},0 x1002, 0 x6839, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE},0 x1002, 0 x683B, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE},0 x1002, 0 x683D, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE},0 x1002, 0 x683F, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VERDE},0 x1002, 0 x6660, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_HAINAN|AMD_IS_MOBILITY},0 x1002, 0 x6663, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_HAINAN|AMD_IS_MOBILITY},0 x1002, 0 x6664, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_HAINAN|AMD_IS_MOBILITY},0 x1002, 0 x6665, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_HAINAN|AMD_IS_MOBILITY},0 x1002, 0 x6667, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_HAINAN|AMD_IS_MOBILITY},0 x1002, 0 x666F, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_HAINAN|AMD_IS_MOBILITY},/* Kaveri */ 0 x1002, 0 x1304, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x1305, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_APU},0 x1002, 0 x1306, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x1307, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_APU},0 x1002, 0 x1309, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x130A, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x130B, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x130C, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x130D, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x130E, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x130F, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_APU},0 x1002, 0 x1310, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_APU},0 x1002, 0 x1311, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_APU},0 x1002, 0 x1312, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_APU},0 x1002, 0 x1313, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_APU},0 x1002, 0 x1315, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_APU},0 x1002, 0 x1316, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_APU},0 x1002, 0 x1317, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x1318, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x131B, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_APU},0 x1002, 0 x131C, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_APU},0 x1002, 0 x131D, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KAVERI|AMD_IS_APU},/* Bonaire */ 0 x1002, 0 x6640, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_BONAIRE|AMD_IS_MOBILITY},0 x1002, 0 x6641, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_BONAIRE|AMD_IS_MOBILITY},0 x1002, 0 x6646, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_BONAIRE|AMD_IS_MOBILITY},0 x1002, 0 x6647, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_BONAIRE|AMD_IS_MOBILITY},0 x1002, 0 x6649, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_BONAIRE},0 x1002, 0 x6650, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_BONAIRE},0 x1002, 0 x6651, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_BONAIRE},0 x1002, 0 x6658, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_BONAIRE},0 x1002, 0 x665c, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_BONAIRE},0 x1002, 0 x665d, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_BONAIRE},0 x1002, 0 x665f, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_BONAIRE},/* Hawaii */ 0 x1002, 0 x67A0, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_HAWAII},0 x1002, 0 x67A1, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_HAWAII},0 x1002, 0 x67A2, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_HAWAII},0 x1002, 0 x67A8, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_HAWAII},0 x1002, 0 x67A9, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_HAWAII},0 x1002, 0 x67AA, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_HAWAII},0 x1002, 0 x67B0, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_HAWAII},0 x1002, 0 x67B1, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_HAWAII},0 x1002, 0 x67B8, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_HAWAII},0 x1002, 0 x67B9, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_HAWAII},0 x1002, 0 x67BA, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_HAWAII},0 x1002, 0 x67BE, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_HAWAII},/* Kabini */ 0 x1002, 0 x9830, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x9831, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KABINI|AMD_IS_APU},0 x1002, 0 x9832, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x9833, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KABINI|AMD_IS_APU},0 x1002, 0 x9834, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x9835, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KABINI|AMD_IS_APU},0 x1002, 0 x9836, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x9837, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KABINI|AMD_IS_APU},0 x1002, 0 x9838, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x9839, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x983a, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KABINI|AMD_IS_APU},0 x1002, 0 x983b, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x983c, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KABINI|AMD_IS_APU},0 x1002, 0 x983d, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KABINI|AMD_IS_APU},0 x1002, 0 x983e, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KABINI|AMD_IS_APU},0 x1002, 0 x983f, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_KABINI|AMD_IS_APU},/* mullins */ 0 x1002, 0 x9850, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x9851, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x9852, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x9853, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x9854, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x9855, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x9856, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x9857, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x9858, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x9859, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x985A, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x985B, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x985C, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x985D, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x985E, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},0 x1002, 0 x985F, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},/* topaz */ 0 x1002, 0 x6900, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TOPAZ},0 x1002, 0 x6901, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TOPAZ},0 x1002, 0 x6902, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TOPAZ},0 x1002, 0 x6903, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TOPAZ},0 x1002, 0 x6907, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TOPAZ},/* tonga */ 0 x1002, 0 x6920, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TONGA},0 x1002, 0 x6921, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TONGA},0 x1002, 0 x6928, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TONGA},0 x1002, 0 x6929, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TONGA},0 x1002, 0 x692B, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TONGA},0 x1002, 0 x692F, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TONGA},0 x1002, 0 x6930, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TONGA},0 x1002, 0 x6938, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TONGA},0 x1002, 0 x6939, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_TONGA},/* fiji */ 0 x1002, 0 x7300, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_FIJI},0 x1002, 0 x730F, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_FIJI},/* carrizo */ 0 x1002, 0 x9870, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_CARRIZO|AMD_IS_APU},0 x1002, 0 x9874, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_CARRIZO|AMD_IS_APU},0 x1002, 0 x9875, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_CARRIZO|AMD_IS_APU},0 x1002, 0 x9876, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_CARRIZO|AMD_IS_APU},0 x1002, 0 x9877, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_CARRIZO|AMD_IS_APU},/* stoney */ 0 x1002, 0 x98E4, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_STONEY|AMD_IS_APU},/* Polaris11 */ 0 x1002, 0 x67E0, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS11},0 x1002, 0 x67E3, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS11},0 x1002, 0 x67E8, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS11},0 x1002, 0 x67EB, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS11},0 x1002, 0 x67EF, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS11},0 x1002, 0 x67FF, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS11},0 x1002, 0 x67E1, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS11},0 x1002, 0 x67E7, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS11},0 x1002, 0 x67E9, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS11},/* Polaris10 */ 0 x1002, 0 x67C0, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS10},0 x1002, 0 x67C1, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS10},0 x1002, 0 x67C2, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS10},0 x1002, 0 x67C4, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS10},0 x1002, 0 x67C7, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS10},0 x1002, 0 x67D0, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS10},0 x1002, 0 x67DF, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS10},0 x1002, 0 x67C8, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS10},0 x1002, 0 x67C9, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS10},0 x1002, 0 x67CA, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS10},0 x1002, 0 x67CC, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS10},0 x1002, 0 x67CF, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS10},0 x1002, 0 x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS10},/* Polaris12 */ 0 x1002, 0 x6980, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS12},0 x1002, 0 x6981, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS12},0 x1002, 0 x6985, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS12},0 x1002, 0 x6986, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS12},0 x1002, 0 x6987, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS12},0 x1002, 0 x6995, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS12},0 x1002, 0 x6997, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS12},0 x1002, 0 x699F, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_POLARIS12},/* VEGAM */ 0 x1002, 0 x694C, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGAM},0 x1002, 0 x694E, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGAM},0 x1002, 0 x694F, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGAM},/* Vega 10 */ 0 x1002, 0 x6860, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA10},0 x1002, 0 x6861, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA10},0 x1002, 0 x6862, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA10},0 x1002, 0 x6863, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA10},0 x1002, 0 x6864, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA10},0 x1002, 0 x6867, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA10},0 x1002, 0 x6868, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA10},0 x1002, 0 x6869, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA10},0 x1002, 0 x686a, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA10},0 x1002, 0 x686b, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA10},0 x1002, 0 x686c, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA10},0 x1002, 0 x686d, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA10},0 x1002, 0 x686e, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA10},0 x1002, 0 x686f, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA10},0 x1002, 0 x687f, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA10},/* Vega 12 */ 0 x1002, 0 x69A0, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA12},0 x1002, 0 x69A1, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA12},0 x1002, 0 x69A2, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA12},0 x1002, 0 x69A3, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA12},0 x1002, 0 x69AF, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA12},/* Vega 20 */ 0 x1002, 0 x66A0, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA20},0 x1002, 0 x66A1, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA20},0 x1002, 0 x66A2, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA20},0 x1002, 0 x66A3, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA20},0 x1002, 0 x66A4, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA20},0 x1002, 0 x66A7, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA20},0 x1002, 0 x66AF, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_VEGA20},/* Raven */ 0 x1002, 0 x15dd, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_RAVEN|AMD_IS_APU},0 x1002, 0 x15d8, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_RAVEN|AMD_IS_APU},/* Arcturus */ 0 x1002, 0 x738C, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_ARCTURUS},0 x1002, 0 x7388, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_ARCTURUS},0 x1002, 0 x738E, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_ARCTURUS},0 x1002, 0 x7390, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_ARCTURUS},/* Navi10 */ 0 x1002, 0 x7310, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVI10},0 x1002, 0 x7312, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVI10},0 x1002, 0 x7318, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVI10},0 x1002, 0 x7319, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVI10},0 x1002, 0 x731A, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVI10},0 x1002, 0 x731B, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVI10},0 x1002, 0 x731E, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVI10},0 x1002, 0 x731F, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVI10},/* Navi14 */ 0 x1002, 0 x7340, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVI14},0 x1002, 0 x7341, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVI14},0 x1002, 0 x7347, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVI14},0 x1002, 0 x734F, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVI14},/* Renoir */ 0 x1002, 0 x15E7, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_RENOIR|AMD_IS_APU},0 x1002, 0 x1636, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_RENOIR|AMD_IS_APU},0 x1002, 0 x1638, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_RENOIR|AMD_IS_APU},0 x1002, 0 x164C, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_RENOIR|AMD_IS_APU},/* Navi12 */ 0 x1002, 0 x7360, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVI12},0 x1002, 0 x7362, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVI12},/* Sienna_Cichlid */ 0 x1002, 0 x73A0, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_SIENNA_CICHLID},0 x1002, 0 x73A1, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_SIENNA_CICHLID},0 x1002, 0 x73A2, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_SIENNA_CICHLID},0 x1002, 0 x73A3, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_SIENNA_CICHLID},0 x1002, 0 x73A5, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_SIENNA_CICHLID},0 x1002, 0 x73A8, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_SIENNA_CICHLID},0 x1002, 0 x73A9, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_SIENNA_CICHLID},0 x1002, 0 x73AB, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_SIENNA_CICHLID},0 x1002, 0 x73AC, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_SIENNA_CICHLID},0 x1002, 0 x73AD, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_SIENNA_CICHLID},0 x1002, 0 x73AE, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_SIENNA_CICHLID},0 x1002, 0 x73AF, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_SIENNA_CICHLID},0 x1002, 0 x73BF, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_SIENNA_CICHLID},/* Yellow Carp */ 0 x1002, 0 x164D, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_YELLOW_CARP|AMD_IS_APU},0 x1002, 0 x1681, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_YELLOW_CARP|AMD_IS_APU},/* Navy_Flounder */ 0 x1002, 0 x73C0, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVY_FLOUNDER},0 x1002, 0 x73C1, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVY_FLOUNDER},0 x1002, 0 x73C3, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVY_FLOUNDER},0 x1002, 0 x73DA, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVY_FLOUNDER},0 x1002, 0 x73DB, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVY_FLOUNDER},0 x1002, 0 x73DC, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVY_FLOUNDER},0 x1002, 0 x73DD, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVY_FLOUNDER},0 x1002, 0 x73DE, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVY_FLOUNDER},0 x1002, 0 x73DF, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_NAVY_FLOUNDER},/* DIMGREY_CAVEFISH */ 0 x1002, 0 x73E0, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_DIMGREY_CAVEFISH},0 x1002, 0 x73E1, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_DIMGREY_CAVEFISH},0 x1002, 0 x73E2, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_DIMGREY_CAVEFISH},0 x1002, 0 x73E3, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_DIMGREY_CAVEFISH},0 x1002, 0 x73E8, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_DIMGREY_CAVEFISH},0 x1002, 0 x73E9, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_DIMGREY_CAVEFISH},0 x1002, 0 x73EA, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_DIMGREY_CAVEFISH},0 x1002, 0 x73EB, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_DIMGREY_CAVEFISH},0 x1002, 0 x73EC, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_DIMGREY_CAVEFISH},0 x1002, 0 x73ED, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_DIMGREY_CAVEFISH},0 x1002, 0 x73EF, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_DIMGREY_CAVEFISH},0 x1002, 0 x73FF, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_DIMGREY_CAVEFISH},/* Aldebaran */ 0 x1002, 0 x7408, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_ALDEBARAN},0 x1002, 0 x740C, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_ALDEBARAN},0 x1002, 0 x740F, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_ALDEBARAN},0 x1002, 0 x7410, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_ALDEBARAN},/* CYAN_SKILLFISH */ 0 x1002, 0 x13DB, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_CYAN_SKILLFISH|AMD_IS_APU},0 x1002, 0 x13F9, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_CYAN_SKILLFISH|AMD_IS_APU},0 x1002, 0 x13FA, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_CYAN_SKILLFISH|AMD_IS_APU},0 x1002, 0 x13FB, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_CYAN_SKILLFISH|AMD_IS_APU},0 x1002, 0 x13FC, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_CYAN_SKILLFISH|AMD_IS_APU},0 x1002, 0 x13FE, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_CYAN_SKILLFISH|AMD_IS_APU},0 x1002, 0 x143F, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_CYAN_SKILLFISH|AMD_IS_APU},/* BEIGE_GOBY */ 0 x1002, 0 x7420, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_BEIGE_GOBY},0 x1002, 0 x7421, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_BEIGE_GOBY},0 x1002, 0 x7422, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_BEIGE_GOBY},0 x1002, 0 x7423, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_BEIGE_GOBY},0 x1002, 0 x7424, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_BEIGE_GOBY},0 x1002, 0 x743F, PCI_ANY_ID, PCI_ANY_ID, 0 , 0 , CHIP_BEIGE_GOBY},0 x1002, PCI_ANY_ID),class = PCI_CLASS_DISPLAY_VGA << 8 ,0 xffffff,0 x1002, PCI_ANY_ID),class = PCI_CLASS_DISPLAY_OTHER << 8 ,0 xffffff,0 x1002, PCI_ANY_ID),class = PCI_CLASS_ACCELERATOR_PROCESSING << 8 ,0 xffffff,0 , 0 , 0 }static const struct amdgpu_asic_type_quirk asic_type_quirks[] = {/* differentiate between P10 and P11 asics with the same DID */ 0 x67FF, 0 xE3, CHIP_POLARIS10},0 x67FF, 0 xE7, CHIP_POLARIS10},0 x67FF, 0 xF3, CHIP_POLARIS10},0 x67FF, 0 xF7, CHIP_POLARIS10},static const struct drm_driver amdgpu_kms_driver;static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)struct pci_dev *p = NULL;int i;/* 0 - GPU * 1 - audio * 2 - USB * 3 - UCSI for (i = 1 ; i < 4 ; i++) {if (p) {static void amdgpu_init_debug_options(struct amdgpu_device *adev)if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) {"debug: VM handling debug enabled\n" );true ;if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) {"debug: enabled simulating large-bar capability on non-large bar system\n" );true ;if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) {"debug: soft reset for GPU recovery disabled\n" );true ;if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) {"debug: place fw in vram for frontdoor loading\n" );true ;if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_RAS_ACA) {"debug: enable RAS ACA\n" );true ;if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) {"debug: enable experimental reset features\n" );true ;if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_RING_RESET) {"debug: ring reset disabled\n" );true ;if (amdgpu_debug_mask & AMDGPU_DEBUG_SMU_POOL) {"debug: use vram for smu pool\n" );if (amdgpu_debug_mask & AMDGPU_DEBUG_VM_USERPTR) {"debug: VM mode debug for userptr is enabled\n" );true ;if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_RAS_CE_LOG) {"debug: disable kernel logs of correctable errors\n" );true ;static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags)int i;for (i = 0 ; i < ARRAY_SIZE(asic_type_quirks); i++) {if (pdev->device == asic_type_quirks[i].device &&break ;return flags;static int amdgpu_pci_probe(struct pci_dev *pdev,const struct pci_device_id *ent)struct drm_device *ddev;struct amdgpu_device *adev;unsigned long flags = ent->driver_data;int ret, retry = 0 , i;bool supports_atomic = false ;if ((pdev->class >> 8 ) == PCI_CLASS_DISPLAY_VGA ||class >> 8 ) == PCI_CLASS_DISPLAY_OTHER) {if (drm_firmware_drivers_only() && amdgpu_modeset == -1 )return -EINVAL;/* skip devices which are owned by radeon */ for (i = 0 ; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {if (amdgpu_unsupported_pciidlist[i] == pdev->device)return -ENODEV;if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))0 ;if (amdgpu_virtual_display ||true ;if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {"This hardware requires experimental hardware support.\n" "See modparam exp_hw_support\n" );return -ENODEV;/* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, * however , SME requires an indirect IOMMU mapping because the encryption * bit is beyond the DMA mask of the chip . if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&"SME is not compatible with RAVEN\n" );return -ENOTSUPP;switch (flags & AMD_ASIC_MASK) {case CHIP_TAHITI:case CHIP_PITCAIRN:case CHIP_VERDE:case CHIP_OLAND:case CHIP_HAINAN:#ifdef CONFIG_DRM_AMDGPU_SIif (!amdgpu_si_support) {"SI support provided by radeon.\n" );"Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" return -ENODEV;break ;#else "amdgpu is built without SI support.\n" );return -ENODEV;#endif case CHIP_KAVERI:case CHIP_BONAIRE:case CHIP_HAWAII:case CHIP_KABINI:case CHIP_MULLINS:#ifdef CONFIG_DRM_AMDGPU_CIKif (!amdgpu_cik_support) {"CIK support provided by radeon.\n" );"Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" return -ENODEV;break ;#else "amdgpu is built without CIK support.\n" );return -ENODEV;#endif default :break ;if (IS_ERR(adev))return PTR_ERR(adev);if (!supports_atomic)if (ret)return ret;if (ret)goto err_pci;if (ret == -EAGAIN && ++retry <= 3 ) {"retry init %d\n" , retry);/* Don't request EX mode too frequently which is attacking */ 5000 );goto retry_init;else if (ret) {goto err_pci;if (ret)goto err_pci;if (ret)goto err_pci;/* * 1 . don ' t init fbdev on hw without DCE * 2 . don ' t init fbdev if there are no connectors if (adev->mode_info.mode_config_initialized &&const struct drm_format_info *format;/* select 8 bpp console on low vram cards */ if (adev->gmc.real_vram_size <= (32 *1024 *1024 ))else if (ret)"Creating debugfs files failed (%d).\n" , ret);if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {/* only need to skip on ATPX */ if (amdgpu_device_supports_px(adev))/* we want direct complete for BOCO */ if (amdgpu_device_supports_boco(adev))5000 );TRUE );/* * For runpm implemented via BACO , PMFW will handle the * timing for BACO in and out : * - put ASIC into BACO state only when both video and * audio functions are in D3 state . * - pull ASIC out of BACO state when either video or * audio function is in D0 state . * Also , at startup , PMFW assumes both functions are in * D0 state . * * So if snd driver was loaded prior to amdgpu driver * and audio function was put into D3 state , there will * be no PMFW - aware D - state transition ( D0 - > D3 ) on runpm * suspend . Thus the BACO will be not correctly kicked in . * * Via amdgpu_get_secondary_funcs ( ) , the audio dev is put * into D0 state . Then there will be a PMFW - aware D - state * transition ( D0 - > D3 ) on runpm suspend . if (amdgpu_device_supports_baco(adev) &&return 0 ;return ret;static void struct pci_dev *pdev)struct drm_device *dev = pci_get_drvdata(pdev);struct amdgpu_device *adev = drm_to_adev(dev);if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {/* * Flush any in flight DMA operations from device . * Clear the Bus Master Enable bit and then wait on the PCIe Device * StatusTransactions Pending bit . static void struct pci_dev *pdev)struct drm_device *dev = pci_get_drvdata(pdev);struct amdgpu_device *adev = drm_to_adev(dev);if (amdgpu_ras_intr_triggered())return ;/* device maybe not resumed here, return immediately in this case */ if (adev->in_s4 && adev->in_suspend)return ;/* if we are running in a VM, make sure the device * torn down properly on reboot / shutdown . * unfortunately we can ' t detect certain * hypervisors so just do this all the time . if (!amdgpu_passthrough(adev))static int amdgpu_pmops_prepare(struct device *dev)struct drm_device *drm_dev = dev_get_drvdata(dev);struct amdgpu_device *adev = drm_to_adev(drm_dev);/* device maybe not resumed here, return immediately in this case */ if (adev->in_s4 && adev->in_suspend)return 0 ;/* Return a positive number here so * DPM_FLAG_SMART_SUSPEND works properly if (amdgpu_device_supports_boco(adev) && pm_runtime_suspended(dev))return 1 ;/* if we will not support s3 or s2i for the device * then skip suspend if (!amdgpu_acpi_is_s0ix_active(adev) &&return 1 ;return amdgpu_device_prepare(drm_dev);static void amdgpu_pmops_complete(struct device *dev)static int amdgpu_pmops_suspend(struct device *dev)struct drm_device *drm_dev = dev_get_drvdata(dev);struct amdgpu_device *adev = drm_to_adev(drm_dev);if (amdgpu_acpi_is_s0ix_active(adev))true ;else if (amdgpu_acpi_is_s3_active(adev))true ;if (!adev->in_s0ix && !adev->in_s3) {#if IS_ENABLED(CONFIG_SUSPEND)/* don't allow going deep first time followed by s2idle the next time */ if (adev->last_suspend_state != PM_SUSPEND_ON &&"Unsupported suspend state %d\n" ,return -EINVAL;#endif return 0 ;#if IS_ENABLED(CONFIG_SUSPEND)/* cache the state last used for suspend */ #endif return amdgpu_device_suspend(drm_dev, true );static int amdgpu_pmops_suspend_noirq(struct device *dev)struct drm_device *drm_dev = dev_get_drvdata(dev);struct amdgpu_device *adev = drm_to_adev(drm_dev);if (amdgpu_acpi_should_gpu_reset(adev))return amdgpu_asic_reset(adev);return 0 ;static int amdgpu_pmops_resume(struct device *dev)struct drm_device *drm_dev = dev_get_drvdata(dev);struct amdgpu_device *adev = drm_to_adev(drm_dev);int r;if (!adev->in_s0ix && !adev->in_s3)return 0 ;/* Avoids registers access if device is physically gone */ if (!pci_device_is_present(adev->pdev))true ;true );if (amdgpu_acpi_is_s0ix_active(adev))false ;else false ;return r;static int amdgpu_pmops_freeze(struct device *dev)struct drm_device *drm_dev = dev_get_drvdata(dev);struct amdgpu_device *adev = drm_to_adev(drm_dev);int r;true );if (r)return r;if (amdgpu_acpi_should_gpu_reset(adev))return amdgpu_asic_reset(adev);return 0 ;static int amdgpu_pmops_thaw(struct device *dev)struct drm_device *drm_dev = dev_get_drvdata(dev);/* do not resume device if it's normal hibernation */ if (!pm_hibernate_is_recovering() && !pm_hibernation_mode_is_suspend())return 0 ;return amdgpu_device_resume(drm_dev, true );static int amdgpu_pmops_poweroff(struct device *dev)struct drm_device *drm_dev = dev_get_drvdata(dev);struct amdgpu_device *adev = drm_to_adev(drm_dev);/* device maybe not resumed here, return immediately in this case */ if (adev->in_s4 && adev->in_suspend)return 0 ;return amdgpu_device_suspend(drm_dev, true );static int amdgpu_pmops_restore(struct device *dev)struct drm_device *drm_dev = dev_get_drvdata(dev);return amdgpu_device_resume(drm_dev, true );static int amdgpu_runtime_idle_check_display(struct device *dev)struct pci_dev *pdev = to_pci_dev(dev);struct drm_device *drm_dev = pci_get_drvdata(pdev);struct amdgpu_device *adev = drm_to_adev(drm_dev);if (adev->mode_info.num_crtc) {struct drm_connector *list_connector;struct drm_connector_list_iter iter;int ret = 0 ;if (amdgpu_runtime_pm != -2 ) {/* XXX: Return busy if any displays are connected to avoid * possible display wakeups after runtime resume due to * hotplug events in case any displays were connected while * the GPU was in suspend . Remove this once that is fixed . if (list_connector->status == connector_status_connected) {break ;if (ret)return ret;if (adev->dc_enabled) {struct drm_crtc *crtc;if (crtc->state->active)if (ret < 0 )break ;else {if (list_connector->dpms == DRM_MODE_DPMS_ON) {break ;if (ret)return ret;return 0 ;static int amdgpu_runtime_idle_check_userq(struct device *dev)struct pci_dev *pdev = to_pci_dev(dev);struct drm_device *drm_dev = pci_get_drvdata(pdev);struct amdgpu_device *adev = drm_to_adev(drm_dev);struct amdgpu_usermode_queue *queue;struct amdgpu_userq_mgr *uqm, *tmp;int queue_id;int ret = 0 ;goto done;return ret;static int amdgpu_pmops_runtime_suspend(struct device *dev)struct pci_dev *pdev = to_pci_dev(dev);struct drm_device *drm_dev = pci_get_drvdata(pdev);struct amdgpu_device *adev = drm_to_adev(drm_dev);int ret, i;if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {return -EBUSY;if (ret)return ret;if (ret)return ret;/* wait for all rings to drain before suspending */ for (i = 0 ; i < AMDGPU_MAX_RINGS; i++) {struct amdgpu_ring *ring = adev->rings[i];if (ring && ring->sched.ready) {if (ret)return -EBUSY;true ;if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)/* * By setting mp1_state as PP_MP1_STATE_UNLOAD , MP1 will do some * proper cleanups and put itself into a state ready for PNP . That * can address some random resuming failure observed on BOCO capable * platforms . * TODO : this may be also needed for PX capable platform . if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)if (ret)return ret;false );if (ret) {false ;if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)return ret;if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) {/* Only need to handle PCI state in the driver for ATPX * PCI core handles it for _ PR3 . else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {/* nothing to do */ else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) ||"asic/device is runtime suspended\n" );return 0 ;static int amdgpu_pmops_runtime_resume(struct device *dev)struct pci_dev *pdev = to_pci_dev(dev);struct drm_device *drm_dev = pci_get_drvdata(pdev);struct amdgpu_device *adev = drm_to_adev(drm_dev);int ret;if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)return -EINVAL;/* Avoids registers access if device is physically gone */ if (!pci_device_is_present(adev->pdev))true ;if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) {/* Only need to handle PCI state in the driver for ATPX * PCI core handles it for _ PR3 . if (ret)return ret;else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {/* Only need to handle PCI state in the driver for ATPX * PCI core handles it for _ PR3 . else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) ||false );if (ret) {if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)return ret;if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)false ;return 0 ;static int amdgpu_pmops_runtime_idle(struct device *dev)struct drm_device *drm_dev = dev_get_drvdata(dev);struct amdgpu_device *adev = drm_to_adev(drm_dev);int ret;if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {return -EBUSY;if (ret)goto done;return ret;static int amdgpu_drm_release(struct inode *inode, struct file *filp)struct drm_file *file_priv = filp->private_data;struct amdgpu_fpriv *fpriv = file_priv->driver_priv;struct drm_device *dev = file_priv->minor->dev;int idx;if (fpriv && drm_dev_enter(dev, &idx)) {true ;return drm_release(inode, filp);long amdgpu_drm_ioctl(struct file *filp,unsigned int cmd, unsigned long arg)struct drm_file *file_priv = filp->private_data;struct drm_device *dev;long ret;if (ret < 0 )goto out;return ret;static const struct dev_pm_ops amdgpu_pm_ops = {static int amdgpu_flush(struct file *f, fl_owner_t id)struct drm_file *file_priv = f->private_data;struct amdgpu_fpriv *fpriv = file_priv->driver_priv;long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;return timeout >= 0 ? 0 : timeout;static const struct file_operations amdgpu_driver_kms_fops = {#ifdef CONFIG_COMPAT#endif #ifdef CONFIG_PROC_FS#endif int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)struct drm_file *file;if (!filp)return -EINVAL;if (filp->f_op != &amdgpu_driver_kms_fops)return -EINVAL;return 0 ;const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {ALLOW),,H|DRM_RENDER_ALLOW),/* KMS */ W),ENDER_ALLOW),,NDER_ALLOW),DER_ALLOW),R_ALLOW),DER_ALLOW),ALLOW),static const struct drm_driver amdgpu_kms_driver = {#ifdef CONFIG_PROC_FS#endif const struct drm_driver amdgpu_partition_driver = {static struct pci_error_handlers amdgpu_pci_err_handler = {static const struct attribute_group *amdgpu_sysfs_groups[] = {static struct pci_driver amdgpu_kms_pci_driver = {static int __init amdgpu_init(void )int r;if (r)goto error_sync;if (r)goto error_fence;"amdgpu kernel modesetting enabled.\n" );/* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) {"Overdrive is enabled, please disable it before " "reporting any bugs unrelated to overdrive.\n" );/* let modprobe override vga console setting */ return pci_register_driver(&amdgpu_kms_pci_driver);return r;static void __exit amdgpu_exit(void )"GPL and additional rights" );
Messung V0.5 in Prozent C=95 H=96 G=95
¤ Dauer der Verarbeitung: 0.95 Sekunden
(vorverarbeitet am 2026-10-03)
¤ *© Formatika GbR, Deutschland
