// SPDX-License-Identifier: GPL-2.0-only
/* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module * * This driver supports the memory controllers found on the Intel * processor family Sandy Bridge . * * Copyright ( c ) 2011 by : * Mauro Carvalho Chehab
#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/edac.h>
#include <linux/mmzone.h>
#include <linux/smp.h>
#include <linux/bitmap.h>
#include <linux/math64.h>
#include <linux/mod_devicetable.h>
#include <
asm /cpu_device_id.h>
#include <
asm /intel-family.h>
#include <
asm /processor.h>
#include <
asm /mce.h>
#include "edac_module.h"
/* Static vars */
static LIST_HEAD(sbridge_edac_list);
static char sb_msg[
256 ];
static char sb_msg_full[
512 ];
/* * Alter this version for the module when modifications are made
#define SBRIDGE_REVISION
" Ver: 1.1.2 "
#define EDAC_MOD_STR
"sb_edac"
/* * Debug macros
#define sbridge_printk(level, fmt, arg...) \
edac_printk(level,
"sbridge" , fmt,
## arg)
#define sbridge_mc_printk(mci, level, fmt, arg...) \
edac_mc_chipset_printk(mci, level,
"sbridge" , fmt,
## arg)
/* * Get a bit field at register value < v > , from bit < lo > to bit < hi >
#define GET_BITFIELD(v, lo, hi) \
(((v) & GENMASK_ULL(hi, lo)) >> (lo))
/* Devices 12 Function 6, Offsets 0x80 to 0xcc */
static const u32 sbridge_dram_rule[] = {
0 x80,
0 x88,
0 x90,
0 x98,
0 xa0,
0 xa8,
0 xb0,
0 xb8,
0 xc0,
0 xc8,
};
static const u32 ibridge_dram_rule[] = {
0 x60,
0 x68,
0 x70,
0 x78,
0 x80,
0 x88,
0 x90,
0 x98,
0 xa0,
0 xa8,
0 xb0,
0 xb8,
0 xc0,
0 xc8,
0 xd0,
0 xd8,
0 xe0,
0 xe8,
0 xf0,
0 xf8,
};
static const u32 knl_dram_rule[] = {
0 x60,
0 x68,
0 x70,
0 x78,
0 x80,
/* 0-4 */
0 x88,
0 x90,
0 x98,
0 xa0,
0 xa8,
/* 5-9 */
0 xb0,
0 xb8,
0 xc0,
0 xc8,
0 xd0,
/* 10-14 */
0 xd8,
0 xe0,
0 xe8,
0 xf0,
0 xf8,
/* 15-19 */
0 x100,
0 x108,
0 x110,
0 x118,
/* 20-23 */
};
#define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg,
0 ,
0 )
#define A7MODE(reg) GET_BITFIELD(reg,
26 ,
26 )
static char *show_dram_attr(u32 attr)
{
switch (attr) {
case 0 :
return "DRAM" ;
case 1 :
return "MMCFG" ;
case 2 :
return "NXM" ;
default :
return "unknown" ;
}
}
static const u32 sbridge_interleave_list[] = {
0 x84,
0 x8c,
0 x94,
0 x9c,
0 xa4,
0 xac,
0 xb4,
0 xbc,
0 xc4,
0 xcc,
};
static const u32 ibridge_interleave_list[] = {
0 x64,
0 x6c,
0 x74,
0 x7c,
0 x84,
0 x8c,
0 x94,
0 x9c,
0 xa4,
0 xac,
0 xb4,
0 xbc,
0 xc4,
0 xcc,
0 xd4,
0 xdc,
0 xe4,
0 xec,
0 xf4,
0 xfc,
};
static const u32 knl_interleave_list[] = {
0 x64,
0 x6c,
0 x74,
0 x7c,
0 x84,
/* 0-4 */
0 x8c,
0 x94,
0 x9c,
0 xa4,
0 xac,
/* 5-9 */
0 xb4,
0 xbc,
0 xc4,
0 xcc,
0 xd4,
/* 10-14 */
0 xdc,
0 xe4,
0 xec,
0 xf4,
0 xfc,
/* 15-19 */
0 x104,
0 x10c,
0 x114,
0 x11c,
/* 20-23 */
};
#define MAX_INTERLEAVE \
(MAX_T(
unsigned int , ARRAY_SIZE(sbridge_interleave_list), \
MAX_T(
unsigned int , ARRAY_SIZE(ibridge_interleave_list), \
ARRAY_SIZE(knl_interleave_list))))
struct interleave_pkg {
unsigned char start;
unsigned char end;
};
static const struct interleave_pkg sbridge_interleave_pkg[] = {
{
0 ,
2 },
{
3 ,
5 },
{
8 ,
10 },
{
11 ,
13 },
{
16 ,
18 },
{
19 ,
21 },
{
24 ,
26 },
{
27 ,
29 },
};
static const struct interleave_pkg ibridge_interleave_pkg[] = {
{
0 ,
3 },
{
4 ,
7 },
{
8 ,
11 },
{
12 ,
15 },
{
16 ,
19 },
{
20 ,
23 },
{
24 ,
27 },
{
28 ,
31 },
};
static inline int sad_pkg(
const struct interleave_pkg *table, u32 reg,
int interleave)
{
return GET_BITFIELD(reg, table[interleave].start,
table[interleave].end);
}
/* Devices 12 Function 7 */
#define TOLM
0 x80
#define TOHM
0 x84
#define HASWELL_TOLM
0 xd0
#define HASWELL_TOHM_0
0 xd4
#define HASWELL_TOHM_1
0 xd8
#define KNL_TOLM
0 xd0
#define KNL_TOHM_0
0 xd4
#define KNL_TOHM_1
0 xd8
#define GET_TOLM(reg) ((GET_BITFIELD(reg,
0 ,
3 ) <<
28 ) |
0 x3ffffff)
#define GET_TOHM(reg) ((GET_BITFIELD(reg,
0 ,
20 ) <<
25 ) |
0 x3ffffff)
/* Device 13 Function 6 */
#define SAD_TARGET
0 xf0
#define SOURCE_ID(reg) GET_BITFIELD(reg,
9 ,
11 )
#define SOURCE_ID_KNL(reg) GET_BITFIELD(reg,
12 ,
14 )
#define SAD_CONTROL
0 xf4
/* Device 14 function 0 */
static const u32 tad_dram_rule[] = {
0 x40,
0 x44,
0 x48,
0 x4c,
0 x50,
0 x54,
0 x58,
0 x5c,
0 x60,
0 x64,
0 x68,
0 x6c,
};
#define MAX_TAD ARRAY_SIZE(tad_dram_rule)
#define TAD_LIMIT(reg) ((GET_BITFIELD(reg,
12 ,
31 ) <<
26 ) |
0 x3ffffff)
#define TAD_SOCK(reg) GET_BITFIELD(reg,
10 ,
11 )
#define TAD_CH(reg) GET_BITFIELD(reg,
8 ,
9 )
#define TAD_TGT3(reg) GET_BITFIELD(reg,
6 ,
7 )
#define TAD_TGT2(reg) GET_BITFIELD(reg,
4 ,
5 )
#define TAD_TGT1(reg) GET_BITFIELD(reg,
2 ,
3 )
#define TAD_TGT0(reg) GET_BITFIELD(reg,
0 ,
1 )
/* Device 15, function 0 */
#define MCMTR
0 x7c
#define KNL_MCMTR
0 x624
#define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr,
2 ,
2 )
#define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr,
1 ,
1 )
#define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr,
0 ,
0 )
/* Device 15, function 1 */
#define RASENABLES
0 xac
#define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg,
0 ,
0 )
/* Device 15, functions 2-5 */
static const int mtr_regs[] = {
0 x80,
0 x84,
0 x88,
};
static const int knl_mtr_reg =
0 xb60;
#define RANK_DISABLE(mtr) GET_BITFIELD(mtr,
16 ,
19 )
#define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr,
14 ,
14 )
#define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr,
12 ,
13 )
#define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr,
2 ,
4 )
#define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr,
0 ,
1 )
static const u32 tad_ch_nilv_offset[] = {
0 x90,
0 x94,
0 x98,
0 x9c,
0 xa0,
0 xa4,
0 xa8,
0 xac,
0 xb0,
0 xb4,
0 xb8,
0 xbc,
};
#define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg,
28 ,
29 )
#define TAD_OFFSET(reg) (GET_BITFIELD(reg,
6 ,
25 ) <<
26 )
static const u32 rir_way_limit[] = {
0 x108,
0 x10c,
0 x110,
0 x114,
0 x118,
};
#define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
#define IS_RIR_VALID(reg) GET_BITFIELD(reg,
31 ,
31 )
#define RIR_WAY(reg) GET_BITFIELD(reg,
28 ,
29 )
#define MAX_RIR_WAY
8
static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
{
0 x120,
0 x124,
0 x128,
0 x12c,
0 x130,
0 x134,
0 x138,
0 x13c },
{
0 x140,
0 x144,
0 x148,
0 x14c,
0 x150,
0 x154,
0 x158,
0 x15c },
{
0 x160,
0 x164,
0 x168,
0 x16c,
0 x170,
0 x174,
0 x178,
0 x17c },
{
0 x180,
0 x184,
0 x188,
0 x18c,
0 x190,
0 x194,
0 x198,
0 x19c },
{
0 x1a0,
0 x1a4,
0 x1a8,
0 x1ac,
0 x1b0,
0 x1b4,
0 x1b8,
0 x1bc },
};
#define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \
GET_BITFIELD(reg,
20 ,
23 ) : GET_BITFIELD(reg,
16 ,
19 ))
#define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \
GET_BITFIELD(reg,
2 ,
15 ) : GET_BITFIELD(reg,
2 ,
14 ))
/* Device 16, functions 2-7 */
/* * FIXME : Implement the error count reads directly
#define RANK_ODD_OV(reg) GET_BITFIELD(reg,
31 ,
31 )
#define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg,
16 ,
30 )
#define RANK_EVEN_OV(reg) GET_BITFIELD(reg,
15 ,
15 )
#define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg,
0 ,
14 )
#if 0 /* Currently unused*/
static const u32 correrrcnt[] = {
0 x104,
0 x108,
0 x10c,
0 x110,
};
static const u32 correrrthrsld[] = {
0 x11c,
0 x120,
0 x124,
0 x128,
};
#endif
#define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg,
16 ,
30 )
#define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg,
0 ,
14 )
/* Device 17, function 0 */
#define SB_RANK_CFG_A
0 x0328
#define IB_RANK_CFG_A
0 x0320
/* * sbridge structs
#define NUM_CHANNELS
6 /* Max channels per MC */
#define MAX_DIMMS
3 /* Max DIMMS per channel */
#define KNL_MAX_CHAS
38 /* KNL max num. of Cache Home Agents */
#define KNL_MAX_CHANNELS
6 /* KNL max num. of PCI channels */
#define KNL_MAX_EDCS
8 /* Embedded DRAM controllers */
#define CHANNEL_UNSPECIFIED
0 xf
/* Intel IA32 SDM 15-14 */
enum type {
SANDY_BRIDGE,
IVY_BRIDGE,
HASWELL,
BROADWELL,
KNIGHTS_LANDING,
};
enum domain {
IMC0 =
0 ,
IMC1,
SOCK,
};
enum mirroring_mode {
NON_MIRRORING,
ADDR_RANGE_MIRRORING,
FULL_MIRRORING,
};
struct sbridge_pvt;
struct sbridge_info {
enum type type;
u32 mcmtr;
u32 rankcfgr;
u64 (*get_tolm)(
struct sbridge_pvt *pvt);
u64 (*get_tohm)(
struct sbridge_pvt *pvt);
u64 (*rir_limit)(u32 reg);
u64 (*sad_limit)(u32 reg);
u32 (*interleave_mode)(u32 reg);
u32 (*dram_attr)(u32 reg);
const u32 *dram_rule;
const u32 *interleave_list;
const struct interleave_pkg *interleave_pkg;
u8 max_sad;
u8 (*get_node_id)(
struct sbridge_pvt *pvt);
u8 (*get_ha)(u8 bank);
enum mem_type (*get_memory_type)(
struct sbridge_pvt *pvt);
enum dev_type (*get_width)(
struct sbridge_pvt *pvt, u32 mtr);
struct pci_dev *pci_vtd;
};
struct sbridge_channel {
u32 ranks;
u32 dimms;
struct dimm {
u32 rowbits;
u32 colbits;
u32 bank_xor_enable;
u32 amap_fine;
} dimm[MAX_DIMMS];
};
struct pci_id_descr {
int dev_id;
int optional;
enum domain dom;
};
struct pci_id_table {
const struct pci_id_descr *descr;
int n_devs_per_imc;
int n_devs_per_sock;
int n_imcs_per_sock;
enum type type;
};
struct sbridge_dev {
struct list_head list;
int seg;
u8 bus, mc;
u8 node_id, source_id;
struct pci_dev **pdev;
enum domain dom;
int n_devs;
int i_devs;
struct mem_ctl_info *mci;
};
struct knl_pvt {
struct pci_dev *pci_cha[KNL_MAX_CHAS];
struct pci_dev *pci_channel[KNL_MAX_CHANNELS];
struct pci_dev *pci_mc0;
struct pci_dev *pci_mc1;
struct pci_dev *pci_mc0_misc;
struct pci_dev *pci_mc1_misc;
struct pci_dev *pci_mc_info;
/* tolm, tohm */
};
struct sbridge_pvt {
/* Devices per socket */
struct pci_dev *pci_ddrio;
struct pci_dev *pci_sad0, *pci_sad1;
struct pci_dev *pci_br0, *pci_br1;
/* Devices per memory controller */
struct pci_dev *pci_ha, *pci_ta, *pci_ras;
struct pci_dev *pci_tad[NUM_CHANNELS];
struct sbridge_dev *sbridge_dev;
struct sbridge_info info;
struct sbridge_channel channel[NUM_CHANNELS];
/* Memory type detection */
bool is_cur_addr_mirrored, is_lockstep, is_close_pg;
bool is_chan_hash;
enum mirroring_mode mirror_mode;
/* Memory description */
u64 tolm, tohm;
struct knl_pvt knl;
};
#define PCI_DESCR(device_id, opt, domain) \
.dev_id = (device_id), \
.optional = opt, \
.dom = domain
static const struct pci_id_descr pci_dev_descr_sbridge[] = {
/* Processor Home Agent */
{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0,
0 , IMC0) },
/* Memory controller */
{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA,
0 , IMC0) },
{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS,
0 , IMC0) },
{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0,
0 , IMC0) },
{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1,
0 , IMC0) },
{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2,
0 , IMC0) },
{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3,
0 , IMC0) },
{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO,
1 , SOCK) },
/* System Address Decoder */
{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0,
0 , SOCK) },
{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1,
0 , SOCK) },
/* Broadcast Registers */
{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR,
0 , SOCK) },
};
#define PCI_ID_TABLE_ENTRY(A, N, M, T) { \
.descr = A, \
.n_devs_per_imc = N, \
.n_devs_per_sock = ARRAY_SIZE(A), \
.n_imcs_per_sock = M, \
.type = T \
}
static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge, ARRAY_SIZE(pci_dev_descr_sbridge),
1 , SAN
DY_BRIDGE),/* This changes depending if 1HA or 2HA: * 1 HA : * 0 x0eb8 ( 17 . 0 ) is DDRIO0 * 2 HA : * 0 x0ebc ( 17 . 4 ) is DDRIO0 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0 x0eb8#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0 x0ebc/* pci ids */ #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0 x0ea0#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0 x0ea8#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0 x0e71#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0 x0eaa#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0 x0eab#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0 x0eac#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0 x0ead#define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0 x0ec8#define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0 x0ec9#define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0 x0eca#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0 x0e60#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0 x0e68#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0 x0e79#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0 x0e6a#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0 x0e6b#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2 0 x0e6c#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3 0 x0e6dstatic const struct pci_id_descr pci_dev_descr_ibridge[] = {/* Processor Home Agent */ 0 , IMC0) },1 , IMC1) },/* Memory controller */ 0 , IMC0) },0 , IMC0) },0 , IMC0) },0 , IMC0) },0 , IMC0) },0 , IMC0) },/* Optional, mode 2HA */ 1 , IMC1) },1 , IMC1) },1 , IMC1) },1 , IMC1) },1 , IMC1) },1 , IMC1) },1 , SOCK) },1 , SOCK) },/* System Address Decoder */ 0 , SOCK) },/* Broadcast Registers */ 1 , SOCK) },0 , SOCK) },static const struct pci_id_table pci_dev_descr_ibridge_table[] = {12 , 2 , IVY_BRIDGE),/* Haswell support */ /* EN processor: * - 1 IMC * - 3 DDR3 channels , 2 DPC per channel * EP processor : * - 1 or 2 IMC * - 4 DDR4 channels , 3 DPC per channel * EP 4 S processor : * - 2 IMC * - 4 DDR4 channels , 3 DPC per channel * EX processor : * - 2 IMC * - each IMC interfaces with a SMI 2 channel * - each SMI channel interfaces with a scalable memory buffer * - each scalable memory buffer supports 4 DDR3 / DDR4 channels , 3 DPC #define HASWELL_DDRCRCLKCONTROLS 0 xa10 /* Ditto on Broadwell */ #define HASWELL_HASYSDEFEATURE2 0 x84#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0 x2f28#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0 x2fa0#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0 x2f60#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0 x2fa8#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM 0 x2f71#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0 x2f68#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM 0 x2f79#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0 x2ffc#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0 x2ffd#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0 x2faa#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0 x2fab#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0 x2fac#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0 x2fad#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0 x2f6a#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0 x2f6b#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0 x2f6c#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0 x2f6d#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0 x2fbd#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0 x2fbf#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0 x2fb9#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0 x2fbbstatic const struct pci_id_descr pci_dev_descr_haswell[] = {/* first item must be the HA */ 0 , IMC0) },1 , IMC1) },0 , IMC0) },0 , IMC0) },0 , IMC0) },0 , IMC0) },1 , IMC0) },1 , IMC0) },1 , IMC1) },1 , IMC1) },1 , IMC1) },1 , IMC1) },1 , IMC1) },1 , IMC1) },0 , SOCK) },0 , SOCK) },1 , SOCK) },1 , SOCK) },1 , SOCK) },1 , SOCK) },static const struct pci_id_table pci_dev_descr_haswell_table[] = {13 , 2 , HASWELL),/* Knight's Landing Support */ /* * KNL ' s memory channels are swizzled between memory controllers . * MC0 is mapped to CH3 , 4 , 5 and MC1 is mapped to CH0 , 1 , 2 #define knl_channel_remap(mc, chan) ((mc) ? (chan) : (chan) + 3 )/* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */ #define PCI_DEVICE_ID_INTEL_KNL_IMC_MC 0 x7840/* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */ #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN 0 x7843/* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */ #define PCI_DEVICE_ID_INTEL_KNL_IMC_TA 0 x7844/* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */ #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0 0 x782a/* SAD target - 1-29-1 (1 of these) */ #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1 0 x782b/* Caching / Home Agent */ #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHA 0 x782c/* Device with TOLM and TOHM, 0-5-0 (1 of these) */ #define PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM 0 x7810/* * KNL differs from SB , IB , and Haswell in that it has multiple * instances of the same device with the same device ID , so we handle that * by creating as many copies in the table as we expect to find . * ( Like device ID must be grouped together . ) static const struct pci_id_descr pci_dev_descr_knl[] = {0 ... 1 ] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_MC, 0 , IMC0)},2 ... 7 ] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN, 0 , IMC0) },8 ] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TA, 0 , IMC0) },9 ] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM, 0 , IMC0) },10 ] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0, 0 , SOCK) },11 ] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1, 0 , SOCK) },12 ... 49 ] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHA, 0 , SOCK) },static const struct pci_id_table pci_dev_descr_knl_table[] = {1 , KNIGHTS_LANDING),/* * Broadwell support * * DE processor : * - 1 IMC * - 2 DDR3 channels , 2 DPC per channel * EP processor : * - 1 or 2 IMC * - 4 DDR4 channels , 3 DPC per channel * EP 4 S processor : * - 2 IMC * - 4 DDR4 channels , 3 DPC per channel * EX processor : * - 2 IMC * - each IMC interfaces with a SMI 2 channel * - each SMI channel interfaces with a scalable memory buffer * - each scalable memory buffer supports 4 DDR3 / DDR4 channels , 3 DPC #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0 x6f28#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0 x6fa0#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1 0 x6f60#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0 x6fa8#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM 0 x6f71#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA 0 x6f68#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM 0 x6f79#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0 x6ffc#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0 x6ffd#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0 x6faa#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0 x6fab#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0 x6fac#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0 x6fad#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0 x6f6a#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0 x6f6b#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0 x6f6c#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0 x6f6d#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0 x6fafstatic const struct pci_id_descr pci_dev_descr_broadwell[] = {/* first item must be the HA */ 0 , IMC0) },1 , IMC1) },0 , IMC0) },0 , IMC0) },0 , IMC0) },0 , IMC0) },1 , IMC0) },1 , IMC0) },1 , IMC1) },1 , IMC1) },1 , IMC1) },1 , IMC1) },1 , IMC1) },1 , IMC1) },0 , SOCK) },0 , SOCK) },1 , SOCK) },static const struct pci_id_table pci_dev_descr_broadwell_table[] = {10 , 2 , BROADWELL),/**************************************************************************** Ancillary status routines static inline int numrank(enum type type, u32 mtr)int ranks = (1 << RANK_CNT_BITS(mtr));int max = 4 ;if (type == HASWELL || type == BROADWELL || type == KNIGHTS_LANDING)8 ;if (ranks > max) {0 , "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n" ,unsigned int )RANK_CNT_BITS(mtr), mtr);return -EINVAL;return ranks;static inline int numrow(u32 mtr)int rows = (RANK_WIDTH_BITS(mtr) + 12 );if (rows < 13 || rows > 18 ) {0 , "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n" ,unsigned int )RANK_WIDTH_BITS(mtr), mtr);return -EINVAL;return 1 << rows;static inline int numcol(u32 mtr)int cols = (COL_WIDTH_BITS(mtr) + 10 );if (cols > 12 ) {0 , "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n" ,unsigned int )COL_WIDTH_BITS(mtr), mtr);return -EINVAL;return 1 << cols;static struct sbridge_dev *get_sbridge_dev(int seg, u8 bus, enum domain dom,int multi_bus,struct sbridge_dev *prev)struct sbridge_dev *sbridge_dev;/* * If we have devices scattered across several busses that pertain * to the same memory controller , we ' ll lump them all together . if (multi_bus) {return list_first_entry_or_null(&sbridge_edac_list,struct sbridge_dev, list);struct sbridge_dev, list);if ((sbridge_dev->seg == seg) && (sbridge_dev->bus == bus) &&return sbridge_dev;return NULL;static struct sbridge_dev *alloc_sbridge_dev(int seg, u8 bus, enum domain dom,const struct pci_id_table *table)struct sbridge_dev *sbridge_dev;sizeof (*sbridge_dev), GFP_KERNEL);if (!sbridge_dev)return NULL;sizeof (*sbridge_dev->pdev),if (!sbridge_dev->pdev) {return NULL;return sbridge_dev;static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)/* Address range is 32:28 */ return GET_TOLM(reg);static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)return GET_TOHM(reg);static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)return GET_TOLM(reg);static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)return GET_TOHM(reg);static u64 rir_limit(u32 reg)return ((u64)GET_BITFIELD(reg, 1 , 10 ) << 29 ) | 0 x1fffffff;static u64 sad_limit(u32 reg)return (GET_BITFIELD(reg, 6 , 25 ) << 26 ) | 0 x3ffffff;static u32 interleave_mode(u32 reg)return GET_BITFIELD(reg, 1 , 1 );static u32 dram_attr(u32 reg)return GET_BITFIELD(reg, 2 , 3 );static u64 knl_sad_limit(u32 reg)return (GET_BITFIELD(reg, 7 , 26 ) << 26 ) | 0 x3ffffff;static u32 knl_interleave_mode(u32 reg)return GET_BITFIELD(reg, 1 , 2 );static const char * const knl_intlv_mode[] = {"[8:6]" , "[10:8]" , "[14:12]" , "[32:30]" static const char *get_intlv_mode_str(u32 reg, enum type t)if (t == KNIGHTS_LANDING)return knl_intlv_mode[knl_interleave_mode(reg)];else return interleave_mode(reg) ? "[8:6]" : "[8:6]XOR[18:16]" ;static u32 dram_attr_knl(u32 reg)return GET_BITFIELD(reg, 3 , 4 );static enum mem_type get_memory_type(struct sbridge_pvt *pvt)enum mem_type mtype;if (pvt->pci_ddrio) {if (GET_BITFIELD(reg, 11 , 11 ))/* FIXME: Can also be LRDIMM */ else else return mtype;static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)bool registered = false ;enum mem_type mtype = MEM_UNKNOWN;if (!pvt->pci_ddrio)goto out;/* Is_Rdimm */ if (GET_BITFIELD(reg, 16 , 16 ))true ;if (GET_BITFIELD(reg, 14 , 14 )) {if (registered)else else {if (registered)else return mtype;static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr)/* for KNL value is fixed */ return DEV_X16;static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)/* there's no way to figure out */ return DEV_UNKNOWN;static enum dev_type __ibridge_get_width(u32 mtr)enum dev_type type = DEV_UNKNOWN;switch (mtr) {case 2 :break ;case 1 :break ;case 0 :break ;return type;static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr)/* * ddr3_width on the documentation but also valid for DDR4 on * Haswell return __ibridge_get_width(GET_BITFIELD(mtr, 7 , 8 ));static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr)/* ddr3_width on the documentation but also valid for DDR4 */ return __ibridge_get_width(GET_BITFIELD(mtr, 8 , 9 ));static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt)/* DDR4 RDIMMS and LRDIMMS are supported */ return MEM_RDDR4;static u8 get_node_id(struct sbridge_pvt *pvt)return GET_BITFIELD(reg, 0 , 2 );static u8 haswell_get_node_id(struct sbridge_pvt *pvt)return GET_BITFIELD(reg, 0 , 3 );static u8 knl_get_node_id(struct sbridge_pvt *pvt)return GET_BITFIELD(reg, 0 , 2 );/* * Use the reporting bank number to determine which memory * controller ( also known as " ha " for " home agent " ) . Sandy * Bridge only has one memory controller per socket , so the * answer is always zero . static u8 sbridge_get_ha(u8 bank)return 0 ;/* * On Ivy Bridge , Haswell and Broadwell the error may be in a * home agent bank ( 7 , 8 ) , or one of the per - channel memory * controller banks ( 9 . . 16 ) . static u8 ibridge_get_ha(u8 bank)switch (bank) {case 7 ... 8 :return bank - 7 ;case 9 ... 16 :return (bank - 9 ) / 4 ;default :return 0 xff;/* Not used, but included for safety/symmetry */ static u8 knl_get_ha(u8 bank)return 0 xff;static u64 haswell_get_tolm(struct sbridge_pvt *pvt)return (GET_BITFIELD(reg, 26 , 31 ) << 26 ) | 0 x3ffffff;static u64 haswell_get_tohm(struct sbridge_pvt *pvt)26 , 31 );6 ) | rc) << 26 ;return rc | 0 x3ffffff;static u64 knl_get_tolm(struct sbridge_pvt *pvt)return (GET_BITFIELD(reg, 26 , 31 ) << 26 ) | 0 x3ffffff;static u64 knl_get_tohm(struct sbridge_pvt *pvt)32 ) | reg_lo;return rc | 0 x3ffffff;static u64 haswell_rir_limit(u32 reg)return (((u64)GET_BITFIELD(reg, 1 , 11 ) + 1 ) << 29 ) - 1 ;static inline u8 sad_pkg_socket(u8 pkg)/* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */ return ((pkg >> 3 ) << 2 ) | (pkg & 0 x3);static inline u8 sad_pkg_ha(u8 pkg)return (pkg >> 2 ) & 0 x1;static int haswell_chan_hash(int idx, u64 addr)int i;/* * XOR even bits from 12 : 26 to bit0 of idx , * odd bits from 13 : 27 to bit1 for (i = 12 ; i < 28 ; i += 2 )3 ;return idx;/* Low bits of TAD limit, and some metadata. */ static const u32 knl_tad_dram_limit_lo[] = {0 x400, 0 x500, 0 x600, 0 x700,0 x800, 0 x900, 0 xa00, 0 xb00,/* Low bits of TAD offset. */ static const u32 knl_tad_dram_offset_lo[] = {0 x404, 0 x504, 0 x604, 0 x704,0 x804, 0 x904, 0 xa04, 0 xb04,/* High 16 bits of TAD limit and offset. */ static const u32 knl_tad_dram_hi[] = {0 x408, 0 x508, 0 x608, 0 x708,0 x808, 0 x908, 0 xa08, 0 xb08,/* Number of ways a tad entry is interleaved. */ static const u32 knl_tad_ways[] = {8 , 6 , 4 , 3 , 2 , 1 ,/* * Retrieve the n ' th Target Address Decode table entry * from the memory controller ' s TAD table . * * @ pvt : driver private data * @ entry : which entry you want to retrieve * @ mc : which memory controller ( 0 or 1 ) * @ offset : output tad range offset * @ limit : output address of first byte above tad range * @ ways : output number of interleave ways * * The offset value has curious semantics . It ' s a sort of running total * of the sizes of all the memory regions that aren ' t mapped in this * tad table . static int knl_get_tad(const struct sbridge_pvt *pvt,const int entry,const int mc,int *ways)struct pci_dev *pci_mc;int way_id;switch (mc) {case 0 :break ;case 1 :break ;default :1 );return -EINVAL;/* Is this TAD entry enabled? */ if (!GET_BITFIELD(reg_limit_lo, 0 , 0 ))return -ENODEV;3 , 5 );if (way_id < ARRAY_SIZE(knl_tad_ways)) {else {0 ;"Unexpected value %d in mc_tad_limit_lo wayness field\n" ,return -ENODEV;/* * The least significant 6 bits of base and limit are truncated . * For limit , we fill the missing bits with 1 s . 6 , 31 ) << 6 ) |0 , 15 ) << 32 );6 , 31 ) << 6 ) | 63 |16 , 31 ) << 32 );return 0 ;/* Determine which memory controller is responsible for a given channel. */ static int knl_channel_mc(int channel)0 || channel >= 6 );return channel < 3 ? 1 : 0 ;/* * Get the Nth entry from EDC_ROUTE_TABLE register . * ( This is the per - tile mapping of logical interleave targets to * physical EDC modules . ) * * entry 0 : 0 : 2 * 1 : 3 : 5 * 2 : 6 : 8 * 3 : 9 : 11 * 4 : 12 : 14 * 5 : 15 : 17 * 6 : 18 : 20 * 7 : 21 : 23 * reserved : 24 : 31 static u32 knl_get_edc_route(int entry, u32 reg)return GET_BITFIELD(reg, entry*3 , (entry*3 )+2 );/* * Get the Nth entry from MC_ROUTE_TABLE register . * ( This is the per - tile mapping of logical interleave targets to * physical DRAM channels modules . ) * * entry 0 : mc 0 : 2 channel 18 : 19 * 1 : mc 3 : 5 channel 20 : 21 * 2 : mc 6 : 8 channel 22 : 23 * 3 : mc 9 : 11 channel 24 : 25 * 4 : mc 12 : 14 channel 26 : 27 * 5 : mc 15 : 17 channel 28 : 29 * reserved : 30 : 31 * * Though we have 3 bits to identify the MC , we should only see * the values 0 or 1 . static u32 knl_get_mc_route(int entry, u32 reg)int mc, chan;3 , (entry*3 )+2 );2 ) + 18 , (entry*2 ) + 18 + 1 );return knl_channel_remap(mc, chan);/* * Render the EDC_ROUTE register in human - readable form . * Output string s should be at least KNL_MAX_EDCS * 2 bytes . static void knl_show_edc_route(u32 reg, char *s)int i;for (i = 0 ; i < KNL_MAX_EDCS; i++) {2 ] = knl_get_edc_route(i, reg) + '0' ;2 +1 ] = '-' ;2 - 1 ] = '\0' ;/* * Render the MC_ROUTE register in human - readable form . * Output string s should be at least KNL_MAX_CHANNELS * 2 bytes . static void knl_show_mc_route(u32 reg, char *s)int i;for (i = 0 ; i < KNL_MAX_CHANNELS; i++) {2 ] = knl_get_mc_route(i, reg) + '0' ;2 +1 ] = '-' ;2 - 1 ] = '\0' ;#define KNL_EDC_ROUTE 0 xb8#define KNL_MC_ROUTE 0 xb4/* Is this dram rule backed by regular DRAM in flat mode? */ #define KNL_EDRAM(reg) GET_BITFIELD(reg, 29 , 29 )/* Is this dram rule cached? */ #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28 , 28 )/* Is this rule backed by edc ? */ #define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29 , 29 )/* Is this rule backed by DRAM, cacheable in EDRAM? */ #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28 , 28 )/* Is this rule mod3? */ #define KNL_MOD3(reg) GET_BITFIELD(reg, 27 , 27 )/* * Figure out how big our RAM modules are . * * The DIMMMTR register in KNL doesn ' t tell us the size of the DIMMs , so we * have to figure this out from the SAD rules , interleave lists , route tables , * and TAD rules . * * SAD rules can have holes in them ( e . g . the 3 G - 4 G hole ) , so we have to * inspect the TAD rules to figure out how large the SAD regions really are . * * When we know the real size of a SAD region and how many ways it ' s * interleaved , we know the individual contribution of each channel to * TAD is size / ways . * * Finally , we have to check whether each channel participates in each SAD * region . * * Fortunately , KNL only supports one DIMM per channel , so once we know how * much memory the channel uses , we know the DIMM is at least that large . * ( The BIOS might possibly choose not to map all available memory , in which * case we will underreport the size of the DIMM . ) * * In theory , we could try to determine the EDC sizes as well , but that would * only work in flat mode , not in cache mode . * * @ mc_sizes : Output sizes of channels ( must have space for KNL_MAX_CHANNELS * elements ) static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes)0 ;int sad_rule = 0 ;int tad_rule = 0 ;int intrlv_ways, tad_ways;int i;2 ]; /* sad size accounting for holes, per mc */ int edram_only;char edc_route_string[KNL_MAX_EDCS*2 ];char mc_route_string[KNL_MAX_CHANNELS*2 ];int cur_reg_start;int mc;int channel;int participants[KNL_MAX_CHANNELS];for (i = 0 ; i < KNL_MAX_CHANNELS; i++)0 ;/* Read the EDC route table in each CHA. */ 0 ;for (i = 0 ; i < KNL_MAX_CHAS; i++) {if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1 ]) {1 ],if (cur_reg_start == i-1 )0 , "edc route table for CHA %d: %s\n" ,else 0 , "edc route table for CHA %d-%d: %s\n" ,1 , edc_route_string);1 ], edc_route_string);if (cur_reg_start == i-1 )0 , "edc route table for CHA %d: %s\n" ,else 0 , "edc route table for CHA %d-%d: %s\n" ,1 , edc_route_string);/* Read the MC route table in each CHA. */ 0 ;for (i = 0 ; i < KNL_MAX_CHAS; i++) {if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1 ]) {1 ], mc_route_string);if (cur_reg_start == i-1 )0 , "mc route table for CHA %d: %s\n" ,else 0 , "mc route table for CHA %d-%d: %s\n" ,1 , mc_route_string);1 ], mc_route_string);if (cur_reg_start == i-1 )0 , "mc route table for CHA %d: %s\n" ,else 0 , "mc route table for CHA %d-%d: %s\n" ,1 , mc_route_string);/* Process DRAM rules */ for (sad_rule = 0 ; sad_rule < pvt->info.max_sad; sad_rule++) {/* previous limit becomes the new base */ if (!DRAM_RULE_ENABLE(dram_rule))break ;1 ;/* * Find out how many ways this dram rule is interleaved . * We stop when we see the first channel again . 0 );for (intrlv_ways = 1 ; intrlv_ways < 8 ; intrlv_ways++) {if ((pkg & 0 x8) == 0 ) {/* * 0 bit means memory is non - local , * which KNL doesn ' t support 0 , "Unexpected interleave target %d\n" ,return -1 ;if (pkg == first_pkg)break ;if (KNL_MOD3(dram_rule))3 ;3 , "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n" ,", EDRAM" : "" );/* * Find out how big the SAD region really is by iterating * over TAD tables ( SAD regions may contain holes ) . * Each memory controller might have a different TAD table , so * we have to look at both . * * Livespace is the memory that ' s mapped in this TAD table , * deadspace is the holes ( this could be the MMIO hole , or it * could be memory that ' s mapped by the other TAD table but * not this one ) . for (mc = 0 ; mc < 2 ; mc++) {0 ;0 ;for (tad_rule = 0 ;if (knl_get_tad(pvt,break ;1 ) -1 ) - tad_size;if (tad_base < sad_base) {if (tad_limit > sad_base)0 , "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n" );else if (tad_base < sad_limit) {if (tad_limit+1 > sad_limit) {0 , "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n" );else {/* TAD region is completely inside SAD region */ 3 , "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n" ,for (mc = 0 ; mc < 2 ; mc++) {3 , " total TAD DRAM footprint in table%d : 0x%llx (%lld bytes)\n" ,/* Ignore EDRAM rule */ if (edram_only)continue ;/* Figure out which channels participate in interleave. */ for (channel = 0 ; channel < KNL_MAX_CHANNELS; channel++)0 ;/* For each channel, does at least one CHA have * this channel mapped to the given target ? for (channel = 0 ; channel < KNL_MAX_CHANNELS; channel++) {int target;int cha;for (target = 0 ; target < KNL_MAX_CHANNELS; target++) {for (cha = 0 ; cha < KNL_MAX_CHAS; cha++) {if (knl_get_mc_route(target,1 ;break ;for (channel = 0 ; channel < KNL_MAX_CHANNELS; channel++) {if (participants[channel]) {4 , "mc channel %d contributes %lld bytes via sad entry %d\n" ,return 0 ;static void get_source_id(struct mem_ctl_info *mci)struct sbridge_pvt *pvt = mci->pvt_info;if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||else if (pvt->info.type == KNIGHTS_LANDING)else static int __populate_dimms(struct mem_ctl_info *mci,enum edac_type mode)struct sbridge_pvt *pvt = mci->pvt_info;int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELSunsigned int i, j, banks, ranks, rows, cols, npages;struct dimm_info *dimm;enum mem_type mtype;if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)0 , "Memory is registered\n" );else if (mtype == MEM_UNKNOWN)0 , "Cannot determine memory type\n" );else 0 , "Memory is unregistered\n" );if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)16 ;else 8 ;for (i = 0 ; i < channels; i++) {0 ;int max_dimms_per_channel;if (pvt->info.type == KNIGHTS_LANDING) {1 ;if (!pvt->knl.pci_channel[i])continue ;else {if (!pvt->pci_tad[i])continue ;0 x8c, &amap);for (j = 0 ; j < max_dimms_per_channel; j++) {0 );if (pvt->info.type == KNIGHTS_LANDING) {else {4 , "Channel #%d MTR%d = %x\n" , i, j, mtr);if (IS_DIMM_PRESENT(mtr)) {if (!IS_ECC_ENABLED(pvt->info.mcmtr)) {"CPU SrcID #%d, Ha #%d, Channel #%d has DIMMs, but ECC is disabled\n" ,return -ENODEV;if (pvt->info.type == KNIGHTS_LANDING) {/* For DDR4, this is fixed. */ 1 << 10 ;8 );else {20 - 3 );0 , "mc#%d: ha %d channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n" ,32 ;9 , 9 );0 , 0 );sizeof (dimm->label),"CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u" ,return 0 ;static int get_dimm_config(struct mem_ctl_info *mci)struct sbridge_pvt *pvt = mci->pvt_info;enum edac_type mode;0 , "mc#%d: Node ID: %d, source ID: %d\n" ,/* KNL doesn't support mirroring or lockstep, * and is always closed page if (pvt->info.type == KNIGHTS_LANDING) {false ;if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0 )return -1 ;if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) {0 , "Failed to read KNL_MCMTR register\n" );return -ENODEV;else {if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®)) {0 , "Failed to read HASWELL_HASYSDEFEATURE2 register\n" );return -ENODEV;21 , 21 );if (GET_BITFIELD(reg, 28 , 28 )) {0 , "Address range partial memory mirroring is enabled\n" );goto next;if (pci_read_config_dword(pvt->pci_ras, RASENABLES, ®)) {0 , "Failed to read RASENABLES register\n" );return -ENODEV;if (IS_MIRROR_ENABLED(reg)) {0 , "Full memory mirroring is enabled\n" );else {0 , "Memory mirroring is disabled\n" );if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) {0 , "Failed to read MCMTR register\n" );return -ENODEV;if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {0 , "Lockstep is enabled\n" );true ;else {0 , "Lockstep is disabled\n" );false ;if (IS_CLOSE_PG(pvt->info.mcmtr)) {0 , "address map is on closed page mode\n" );true ;else {0 , "address map is on open page mode\n" );false ;return __populate_dimms(mci, knl_mc_sizes, mode);static void get_memory_layout(const struct mem_ctl_info *mci)struct sbridge_pvt *pvt = mci->pvt_info;int i, j, k, n_sads, n_tads, sad_interl;0 ;/* * Step 1 ) Get TOLM / TOHM ranges 1 + pvt->tolm) >> 20 ;1024 , &mb);0 , "TOLM: %u.%03u GB (0x%016Lx)\n" ,1000 )/1024 , (u64)pvt->tolm);/* Address range is already 45:25 */ 1 + pvt->tohm) >> 20 ;1024 , &mb);0 , "TOHM: %u.%03u GB (0x%016Lx)\n" ,1000 )/1024 , (u64)pvt->tohm);/* * Step 2 ) Get SAD range and SAD Interleave list * TAD registers contain the interleave wayness . However , it * seems simpler to just discover it indirectly , with the * algorithm bellow . 0 ;for (n_sads = 0 ; n_sads < pvt->info.max_sad; n_sads++) {/* SAD_LIMIT Address range is 45:26 */ if (!DRAM_RULE_ENABLE(reg))continue ;if (limit <= prv)break ;1 ) >> 20 ;1024 , &mb);0 , "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n" ,1000 )/1024 ,20 L,0 );for (j = 0 ; j < 8 ; j++) {if (j > 0 && sad_interl == pkg)break ;0 , "SAD#%d, interleave #%d: %d\n" ,if (pvt->info.type == KNIGHTS_LANDING)return ;/* * Step 3 ) Get TAD range 0 ;for (n_tads = 0 ; n_tads < MAX_TAD; n_tads++) {if (limit <= prv)break ;1 ) >> 20 ;1024 , &mb);0 , "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n" ,1000 )/1024 ,20 L,1 << TAD_SOCK(reg)),1 ,/* * Step 4 ) Get TAD offsets , per each channel for (i = 0 ; i < NUM_CHANNELS; i++) {if (!pvt->channel[i].dimms)continue ;for (j = 0 ; j < n_tads; j++) {20 ;1024 , &mb);0 , "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n" ,1000 )/1024 ,20 L,/* * Step 6 ) Get RIR Wayness / Limit , per each channel for (i = 0 ; i < NUM_CHANNELS; i++) {if (!pvt->channel[i].dimms)continue ;for (j = 0 ; j < MAX_RIR_RANGES; j++) {if (!IS_RIR_VALID(reg))continue ;20 ;1 << RIR_WAY(reg);1024 , &mb);0 , "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n" ,1000 )/1024 ,20 L,for (k = 0 ; k < rir_way; k++) {6 ;1024 , &mb);0 , "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n" ,1000 )/1024 ,20 L,static struct mem_ctl_info *get_mci_for_node_id(u8 node_id, u8 ha)struct sbridge_dev *sbridge_dev;if (sbridge_dev->node_id == node_id && sbridge_dev->dom == ha)return sbridge_dev->mci;return NULL;static u8 sb_close_row[] = {15 , 16 , 17 , 18 , 20 , 21 , 22 , 28 , 10 , 11 , 12 , 13 , 29 , 30 , 31 , 32 , 33 static u8 sb_close_column[] = {3 , 4 , 5 , 14 , 19 , 23 , 24 , 25 , 26 , 27 static u8 sb_open_row[] = {14 , 15 , 16 , 20 , 28 , 21 , 22 , 23 , 24 , 25 , 26 , 27 , 29 , 30 , 31 , 32 , 33 static u8 sb_open_column[] = {3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 static u8 sb_open_fine_column[] = {3 , 4 , 5 , 7 , 8 , 9 , 10 , 11 , 12 , 13 static int sb_bits(u64 addr, int nbits, u8 *bits)int i, res = 0 ;for (i = 0 ; i < nbits; i++)1 ) << i;return res;static int sb_bank_bits(u64 addr, int b0, int b1, int do_xor, int x0, int x1)int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1 );if (do_xor)1 );return ret;static bool sb_decode_ddr4(struct mem_ctl_info *mci, int ch, u8 rank,char *msg)int dimmno = 0 ;int row, col, bank_address, bank_group;struct sbridge_pvt *pvt;0 , rowbits = 0 , colbits = 0 ;0 , bank_xor_enable = 0 ;12 ) ? rank / 4 : 2 ;6 : 13 ;if (pvt->is_lockstep) {"LockStep row/column decode is not supported yet!\n" );0 ] = '\0' ;return false ;if (pvt->is_close_pg) {0 x400; /* C10 is autoprecharge, always set */ 8 , 9 , bank_xor_enable, 22 , 28 );6 , 7 , bank_xor_enable, 20 , 21 );else {if (amap_fine)else 18 , 19 , bank_xor_enable, 22 , 23 );17 , bank_xor_enable, 20 , 21 );1 u << rowbits) - 1 ;"row:0x%x col:0x%x bank_addr:%d bank_group:%d" ,return true ;static bool sb_decode_ddr3(struct mem_ctl_info *mci, int ch, u8 rank,char *msg)"DDR3 row/column decode not support yet!\n" );0 ] = '\0' ;return false ;static int get_memory_error_data(struct mem_ctl_info *mci,long *channel_mask,char **area_type, char *msg)struct mem_ctl_info *new_mci;struct sbridge_pvt *pvt = mci->pvt_info;struct pci_dev *pci_ha;int n_rir, n_sads, n_tads, sad_way, sck_xch;int sad_interl, idx, base_ch;int interleave_mode, shiftup = 0 ;unsigned int sad_interleave[MAX_INTERLEAVE];0 , rankid = 0 ;0 , prv = 0 ;enum mem_type mtype;/* * Step 0 ) Check if the address is at special memory ranges * The check bellow is probably enough to fill all cases where * the error is not inside a memory , except for the legacy * range ( e . g . VGA addresses ) . It is unlikely , however , that the * memory controller would generate an error on that range . if ((addr > (u64) pvt->tolm) && (addr < (1 LL << 32 ))) {"Error at TOLM area, on addr 0x%08Lx" , addr);return -EINVAL;if (addr >= (u64)pvt->tohm) {"Error at MMIOH area, on addr 0x%016Lx" , addr);return -EINVAL;/* * Step 1 ) Get socket for (n_sads = 0 ; n_sads < pvt->info.max_sad; n_sads++) {if (!DRAM_RULE_ENABLE(reg))continue ;if (limit <= prv) {"Can't discover the memory socket" );return -EINVAL;if (addr <= limit)break ;if (n_sads == pvt->info.max_sad) {"Can't discover the memory socket" );return -EINVAL;if (pvt->info.type == SANDY_BRIDGE) {0 );for (sad_way = 0 ; sad_way < 8 ; sad_way++) {if (sad_way > 0 && sad_interl == pkg)break ;0 , "SAD interleave #%d: %d\n" ,0 , "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n" ,7 ,"" : "XOR[18:16]" );if (interleave_mode)6 ) ^ (addr >> 16 )) & 7 ;else 6 ) & 7 ;switch (sad_way) {case 1 :0 ;break ;case 2 :1 ;break ;case 4 :3 ;break ;case 8 :break ;default :"Can't discover socket interleave" );return -EINVAL;0 , "SAD interleave index: %d (wayness %d) = CPU socket %d\n" ,else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {int bits, a7mode = A7MODE(dram_rule);if (a7mode) {/* A7 mode swaps P9 with P6 */ 7 , 8 ) << 1 ;9 , 9 );else 6 , 8 );if (interleave_mode == 0 ) {/* interleave mode will XOR {8,7,6} with {18,17,16} */ 16 , 18 );else if (a7mode) {/* MCChanShiftUpEnable */ 22 , 22 );0 , "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n" ,else {/* Ivy Bridge's SAD mode doesn't support XOR interleave mode */ 6 ) & 7 ;0 , "SAD interleave package: %d = CPU socket %d, HA %d\n" ,/* * Move to the proper node structure , in order to access the * right PCI registers if (!new_mci) {"Struct for socket #%u wasn't initialized" ,return -EINVAL;/* * Step 2 ) Get memory channel 0 ;for (n_tads = 0 ; n_tads < MAX_TAD; n_tads++) {if (limit <= prv) {"Can't discover the memory channel" );return -EINVAL;if (addr <= limit)break ;if (n_tads == MAX_TAD) {"Can't discover the memory channel" );return -EINVAL;1 ;if (ch_way == 3 )6 ;else {6 + sck_way + shiftup)) & 0 x3;if (pvt->is_chan_hash)/* * FIXME : Shouldn ' t we use CHN_IDX_OFFSET ( ) here , when ch_way = = 3 ? ? ? switch (idx) {case 0 :break ;case 1 :break ;case 2 :break ;case 3 :break ;default :"Can't discover the TAD target" );return -EINVAL;1 << base_ch;if (pvt->mirror_mode == FULL_MIRRORING ||0 )) {1 << ((base_ch + 2 ) % 4 );switch (ch_way) {case 2 :case 4 :1 << sck_way) * (ch_way >> 1 );break ;default :"Invalid mirror set. Can't decode addr" );return -EINVAL;true ;else {1 << sck_way) * ch_way;false ;if (pvt->is_lockstep)1 << ((base_ch + 1 ) % 4 );0 , "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n" ,/* Calculate channel address */ /* Remove the TAD offset */ if (offset > addr) {"Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!" ,return -EINVAL;6 + shiftup);6 + shiftup);1 << (6 + shiftup)) - 1 );/* * Step 3 ) Decode rank for (n_rir = 0 ; n_rir < MAX_RIR_RANGES; n_rir++) {if (!IS_RIR_VALID(reg))continue ;20 , 1024 , &mb);0 , "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n" ,1000 )/1024 ,1 << RIR_WAY(reg));if (ch_addr <= limit)break ;if (n_rir == MAX_RIR_RANGES) {"Can't discover the memory rank for ch addr 0x%08Lx" ,return -EINVAL;if (pvt->is_close_pg)6 );else 13 ); /* FIXME: Datasheet says to shift by 15 */ 1 << rir_way;if (pvt->info.type == BROADWELL) {if (pvt->is_close_pg)6 ;else 13 ;1 << rir_way);1 , 0 );if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)else else {0 ] = '\0' ;0 , "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n" ,return 0 ;static int get_memory_error_data_from_mce(struct mem_ctl_info *mci,const struct mce *m, u8 *socket,long *channel_mask,char *msg)0 , 3 );struct mem_ctl_info *new_mci;struct sbridge_pvt *pvt;struct pci_dev *pci_ha;bool tad0;if (channel >= NUM_CHANNELS) {"Invalid channel 0x%x" , channel);return -EINVAL;if (!pvt->info.get_ha) {"No get_ha()" );return -EINVAL;if (*ha != 0 && *ha != 1 ) {"Impossible bank %d" , m->bank);return -EINVAL;if (!new_mci) {"mci socket got corrupted!" );return -EINVAL;0 ], ®);1 << channel;if (pvt->mirror_mode == FULL_MIRRORING ||1 << ((channel + 2 ) % 4 );true ;else {false ;if (pvt->is_lockstep)1 << ((channel + 1 ) % 4 );return 0 ;/**************************************************************************** Device initialization routines : put / get , init / exit /* * sbridge_put_all_devices ' put ' all the devices that we have * reserved via ' get ' static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)int i;0 , "\n" );for (i = 0 ; i < sbridge_dev->n_devs; i++) {struct pci_dev *pdev = sbridge_dev->pdev[i];if (!pdev)continue ;0 , "Removing dev %02x:%02x.%d\n" ,static void sbridge_put_all_devices(void )struct sbridge_dev *sbridge_dev, *tmp;static int sbridge_get_onedevice(struct pci_dev **prev,const struct pci_id_table *table,const unsigned devno,const int multi_bus)struct sbridge_dev *sbridge_dev = NULL;const struct pci_id_descr *dev_descr = &table->descr[devno];struct pci_dev *pdev = NULL;int seg = 0 ;0 ;int i = 0 ;"Seeking for: PCI ID %04x:%04x\n" ,if (!pdev) {if (*prev) {return 0 ;if (dev_descr->optional)return 0 ;/* if the HA wasn't found */ if (devno == 0 )return -ENODEV;"Device not found: %04x:%04x\n" ,/* End of list, leave */ return -ENODEV;if (!sbridge_dev) {/* If the HA1 wasn't found, don't create EDAC second memory controller */ if (dev_descr->dom == IMC1 && devno != 1 ) {0 , "Skip IMC1: %04x:%04x (since HA1 was absent)\n" ,return 0 ;if (dev_descr->dom == SOCK)goto out_imc;if (!sbridge_dev) {return -ENOMEM;if (sbridge_dev->pdev[sbridge_dev->i_devs]) {"Duplicated device for %04x:%04x\n" ,return -ENODEV;/* pdev belongs to more than one IMC, do extra gets */ if (++i > 1 )if (dev_descr->dom == SOCK && i < table->n_imcs_per_sock)goto next_imc;/* Be sure that the device is enabled */ if (unlikely(pci_enable_device(pdev) < 0 )) {"Couldn't enable %04x:%04x\n" ,return -ENODEV;0 , "Detected %04x:%04x\n" ,/* * As stated on drivers / pci / search . c , the reference count for * @ from is always decremented if it is not % NULL . So , as we need * to get all devices up to null , we need to do a get for the device return 0 ;/* * sbridge_get_all_devices - Find and perform ' get ' operation on the MCH ' s * devices we want to reference for this driver . * @ num_mc : pointer to the memory controllers count , to be incremented in case * of success . * @ table : model specific table * * returns 0 in case of success or error code static int sbridge_get_all_devices(u8 *num_mc,const struct pci_id_table *table)int i, rc;struct pci_dev *pdev = NULL;int allow_dups = 0 ;int multi_bus = 0 ;if (table->type == KNIGHTS_LANDING)1 ;while (table && table->descr) {for (i = 0 ; i < table->n_devs_per_sock; i++) {if (!allow_dups || i == 0 ||1 ].dev_id) {do {if (rc < 0 ) {if (i == 0 ) {break ;return -ENODEV;while (pdev && !allow_dups);return 0 ;/* * Device IDs for { SBRIDGE , IBRIDGE , HASWELL , BROADWELL } _ IMC_HA0_TAD0 are in * the format : XXXa . So we can convert from a device to the corresponding * channel like this #define TAD_DEV_TO_CHAN(dev) (((dev) & 0 xf) - 0 xa)static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,struct sbridge_dev *sbridge_dev)struct sbridge_pvt *pvt = mci->pvt_info;struct pci_dev *pdev;0 ;int i;for (i = 0 ; i < sbridge_dev->n_devs; i++) {if (!pdev)continue ;switch (pdev->device) {case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:break ;case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:break ;case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:break ;case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:break ;case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:break ;case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:break ;case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:int id = TAD_DEV_TO_CHAN(pdev->device);1 << id;break ;case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:break ;default :goto error;0 , "Associated PCI %02x:%02x, bus %d with dev = %p\n" ,/* Check if everything were registered */ if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha ||goto enodev;if (saw_chan_mask != 0 x0f)goto enodev;return 0 ;"Some needed devices are missing\n" );return -ENODEV;"Unexpected device %02x:%02x\n" ,return -EINVAL;static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,struct sbridge_dev *sbridge_dev)struct sbridge_pvt *pvt = mci->pvt_info;struct pci_dev *pdev;0 ;int i;for (i = 0 ; i < sbridge_dev->n_devs; i++) {if (!pdev)continue ;switch (pdev->device) {case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:break ;case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA:break ;case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS:break ;case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2:case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3:int id = TAD_DEV_TO_CHAN(pdev->device);1 << id;break ;case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:break ;case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:break ;case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:break ;case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:break ;case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:break ;default :goto error;0 , "Associated PCI %02x.%02d.%d with dev = %p\n" ,/* Check if everything were registered */ if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_br0 ||goto enodev;if (saw_chan_mask != 0 x0f && /* -EN/-EX */ 0 x03) /* -EP */ goto enodev;return 0 ;"Some needed devices are missing\n" );return -ENODEV;"Unexpected device %02x:%02x\n" , PCI_VENDOR_ID_INTEL,return -EINVAL;static int haswell_mci_bind_devs(struct mem_ctl_info *mci,struct sbridge_dev *sbridge_dev)struct sbridge_pvt *pvt = mci->pvt_info;struct pci_dev *pdev;0 ;int i;/* there's only one device per system; not tied to any bus */ if (pvt->info.pci_vtd == NULL)/* result will be checked later */ for (i = 0 ; i < sbridge_dev->n_devs; i++) {if (!pdev)continue ;switch (pdev->device) {case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:break ;case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:break ;case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:break ;case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:break ;case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM:case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM:break ;case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2:case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3:int id = TAD_DEV_TO_CHAN(pdev->device);1 << id;break ;case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1:case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2:case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3:if (!pvt->pci_ddrio)break ;default :break ;0 , "Associated PCI %02x.%02d.%d with dev = %p\n" ,/* Check if everything were registered */ if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 ||goto enodev;if (saw_chan_mask != 0 x0f && /* -EN/-EX */ 0 x03) /* -EP */ goto enodev;return 0 ;"Some needed devices are missing\n" );return -ENODEV;static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,struct sbridge_dev *sbridge_dev)struct sbridge_pvt *pvt = mci->pvt_info;struct pci_dev *pdev;0 ;int i;/* there's only one device per system; not tied to any bus */ if (pvt->info.pci_vtd == NULL)/* result will be checked later */ for (i = 0 ; i < sbridge_dev->n_devs; i++) {if (!pdev)continue ;switch (pdev->device) {case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:break ;case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:break ;case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1:break ;case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA:break ;case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM:case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM:break ;case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0:case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1:case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2:case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3:int id = TAD_DEV_TO_CHAN(pdev->device);1 << id;break ;case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:break ;default :break ;0 , "Associated PCI %02x.%02d.%d with dev = %p\n" ,/* Check if everything were registered */ if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 ||goto enodev;if (saw_chan_mask != 0 x0f && /* -EN/-EX */ 0 x03) /* -EP */ goto enodev;return 0 ;"Some needed devices are missing\n" );return -ENODEV;static int knl_mci_bind_devs(struct mem_ctl_info *mci,struct sbridge_dev *sbridge_dev)struct sbridge_pvt *pvt = mci->pvt_info;struct pci_dev *pdev;int dev, func;int i;int devidx;for (i = 0 ; i < sbridge_dev->n_devs; i++) {if (!pdev)continue ;/* Extract PCI device and function. */ 3 ) & 0 x1f;0 x7;switch (pdev->device) {case PCI_DEVICE_ID_INTEL_KNL_IMC_MC:if (dev == 8 )else if (dev == 9 )else {"Memory controller in unexpected place! (dev %d, fn %d)\n" ,continue ;break ;case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0:break ;case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1:break ;case PCI_DEVICE_ID_INTEL_KNL_IMC_CHA:/* There are one of these per tile, and range from * 1 . 14 . 0 to 1 . 18 . 5 . 14 )*8 )+func;if (devidx < 0 || devidx >= KNL_MAX_CHAS) {"Caching and Home Agent in unexpected place! (dev %d, fn %d)\n" ,continue ;break ;case PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN:1 ;/* * MC0 channels 0 - 2 are device 9 function 2 - 4 , * MC1 channels 3 - 5 are device 8 function 2 - 4 . if (dev == 9 )2 ;else if (dev == 8 )3 + (func-2 );if (devidx < 0 || devidx >= KNL_MAX_CHANNELS) {"DRAM Channel Registers in unexpected place! (dev %d, fn %d)\n" ,continue ;break ;case PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM:break ;case PCI_DEVICE_ID_INTEL_KNL_IMC_TA:break ;default :"Unexpected device %d\n" ,break ;if (!pvt->knl.pci_mc0 || !pvt->knl.pci_mc1 ||goto enodev;for (i = 0 ; i < KNL_MAX_CHANNELS; i++) {if (!pvt->knl.pci_channel[i]) {"Missing channel %d\n" , i);goto enodev;for (i = 0 ; i < KNL_MAX_CHAS; i++) {if (!pvt->knl.pci_cha[i]) {"Missing CHA %d\n" , i);goto enodev;return 0 ;"Some needed devices are missing\n" );return -ENODEV;/**************************************************************************** Error check routines /* * While Sandy Bridge has error count registers , SMI BIOS read values from * and resets the counters . So , they are not reliable for the OS to read * from them . So , we have no option but to just trust on whatever MCE is * telling us about the errors . static void sbridge_mce_output_error(struct mem_ctl_info *mci,const struct mce *m)struct mem_ctl_info *new_mci;struct sbridge_pvt *pvt = mci->pvt_info;enum hw_event_mc_err_type tp_event;bool ripv = GET_BITFIELD(m->mcgstatus, 0 , 0 );bool overflow = GET_BITFIELD(m->status, 62 , 62 );bool uncorrected_error = GET_BITFIELD(m->status, 61 , 61 );bool recoverable;38 , 52 );16 , 31 );0 , 15 );0 , 3 );4 , 6 );/* * Bits 5 - 0 of MCi_MISC give the least significant bit that is valid . * A value 6 is for cache line aligned address , a value 12 is for page * aligned address reported by patrol scrubber . 0 , 5 );char *optype, *area_type = "DRAM" ;long channel_mask, first_channel;0 xff, socket, ha;int rc, dimm;if (pvt->info.type != SANDY_BRIDGE)true ;else 56 , 56 );if (uncorrected_error) {1 ;if (ripv) {else {else {/* * According with Table 15 - 9 of the Intel Architecture spec vol 3 A , * memory errors should fit in this mask : * 000 f 0000 1 mmm cccc ( binary ) * where : * f = Correction Report Filtering Bit . If 1 , subsequent errors * won ' t be shown * mmm = error type * cccc = channel * If the mask doesn ' t match , report an error to the parsing logic switch (optypenum) {case 0 :"generic undef request error" ;break ;case 1 :"memory read error" ;break ;case 2 :"memory write error" ;break ;case 3 :"addr/cmd error" ;break ;case 4 :"memory scrubbing error" ;break ;default :"reserved" ;break ;if (pvt->info.type == KNIGHTS_LANDING) {if (channel == 14 ) {0 , "%s%s err_code:%04x:%04x EDRAM bank %d\n" ," OVERFLOW" : "" ," recoverable" : "" ,else {char A = *("A" );/* * Reported channel is in range 0 - 2 , so we can ' t map it * back to mc . To figure out mc we check machine check * bank register that reported this error . * bank15 means mc0 and bank16 means mc1 . 16 , channel);1 << channel;sizeof (sb_msg),"%s%s err_code:%04x:%04x channel:%d (DIMM_%c)" ," OVERFLOW" : "" ," recoverable" : " " ,0 ,0 , -1 ,return ;else if (lsb < 12 ) {else {if (rc < 0 )goto err_parsing;if (!new_mci) {"Error: socket got corrupted!" );goto err_parsing;if (rank == 0 xff)1 ;else if (rank < 4 )0 ;else if (rank < 8 )1 ;else 2 ;/* * FIXME : On some memory configurations ( mirror , lockstep ) , the * Memory Controller can ' t point the error to a single DIMM . The * EDAC core should be handling the channel mask , in order to point * to the group of dimm ' s where the error may be happening . if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg)sizeof (sb_msg_full),"%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d %s" ," OVERFLOW" : "" ," recoverable" : "" ,0 , "%s\n" , sb_msg_full);/* FIXME: need support for channel mask */ if (channel == CHANNEL_UNSPECIFIED)1 ;/* Call the helper to output message */ 0 ,1 ,return ;0 , 0 , 0 ,1 , -1 , -1 ,"" );/* * Check that logging is enabled and that this is the right type * of error for us to handle . static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,void *data)struct mce *mce = (struct mce *)data;struct mem_ctl_info *mci;char *type;if (mce->kflags & MCE_HANDLED_CEC)return NOTIFY_DONE;/* * Just let mcelog handle it if the error is * outside the memory controller . A memory error * is indicated by bit 7 = 1 and bits = 8 - 11 , 13 - 15 = 0 . * bit 12 has an special meaning . if ((mce->status & 0 xefff) >> 7 != 1 )return NOTIFY_DONE;/* Check ADDRV bit in STATUS */ if (!GET_BITFIELD(mce->status, 58 , 58 ))return NOTIFY_DONE;/* Check MISCV bit in STATUS */ if (!GET_BITFIELD(mce->status, 59 , 59 ))return NOTIFY_DONE;/* Check address type in MISC (physical address only) */ if (GET_BITFIELD(mce->misc, 6 , 8 ) != 2 )return NOTIFY_DONE;if (!mci)return NOTIFY_DONE;if (mce->mcgstatus & MCG_STATUS_MCIP)"Exception" ;else "Event" ;"HANDLING MCE MEMORY ERROR\n" );"CPU %d: Machine Check %s: %Lx " "Bank %d: %016Lx\n" , mce->extcpu, type,"TSC %llx " , mce->tsc);"ADDR %llx " , mce->addr);"MISC %llx " , mce->misc);"PROCESSOR %u:%x TIME %llu SOCKET " "%u APIC %x\n" , mce->cpuvendor, mce->cpuid,/* Advice mcelog that the error were handled */ return NOTIFY_OK;static struct notifier_block sbridge_mce_dec = {/**************************************************************************** EDAC register / unregister logic static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)struct mem_ctl_info *mci = sbridge_dev->mci;if (unlikely(!mci || !mci->pvt_info)) {0 , "MC: dev = %p\n" , &sbridge_dev->pdev[0 ]->dev);"Couldn't find mci handler\n" );return ;0 , "MC: mci = %p, dev = %p\n" ,0 ]->dev);/* Remove MC sysfs nodes */ 1 , "%s: free mci struct\n" , mci->ctl_name);static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)struct mem_ctl_info *mci;struct edac_mc_layer layers[2 ];struct sbridge_pvt *pvt;struct pci_dev *pdev = sbridge_dev->pdev[0 ];int rc;/* allocate a new MC control structure */ 0 ].type = EDAC_MC_LAYER_CHANNEL;0 ].size = type == KNIGHTS_LANDING ?0 ].is_virt_csrow = false ;1 ].type = EDAC_MC_LAYER_SLOT;1 ].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS;1 ].is_virt_csrow = true ;sizeof (*pvt));if (unlikely(!mci))return -ENOMEM;0 , "MC: mci = %p, dev = %p\n" ,0 , sizeof (*pvt));/* Associate sbridge_dev and mci for future usage */ switch (type) {case IVY_BRIDGE:/* Store pci devices at mci for faster access */ if (unlikely(rc < 0 ))goto fail0;"Ivy Bridge SrcID#%d_Ha#%d" ,break ;case SANDY_BRIDGE:/* Store pci devices at mci for faster access */ if (unlikely(rc < 0 ))goto fail0;"Sandy Bridge SrcID#%d_Ha#%d" ,break ;case HASWELL:/* rankcfgr isn't used */ /* Store pci devices at mci for faster access */ if (unlikely(rc < 0 ))goto fail0;"Haswell SrcID#%d_Ha#%d" ,break ;case BROADWELL:/* rankcfgr isn't used */ /* Store pci devices at mci for faster access */ if (unlikely(rc < 0 ))goto fail0;"Broadwell SrcID#%d_Ha#%d" ,break ;case KNIGHTS_LANDING:/* pvt->info.rankcfgr == ??? */ if (unlikely(rc < 0 ))goto fail0;"Knights Landing SrcID#%d_Ha#%d" ,break ;if (!mci->ctl_name) {goto fail0;/* Get dimm basic config and the memory layout */ if (rc < 0 ) {0 , "MC: failed to get_dimm_config()\n" );goto fail;/* record ptr to the generic device */ /* add this new MC control structure to EDAC's list of MCs */ if (unlikely(edac_mc_add_mc(mci))) {0 , "MC: failed edac_mc_add_mc()\n" );goto fail;return 0 ;return rc;static const struct x86_cpu_id sbridge_cpuids[] = {/* * sbridge_probe Get all devices and register memory controllers * present . * return : * 0 for FOUND a device * < 0 for error code static int sbridge_probe(const struct x86_cpu_id *id)int rc;0 ;struct sbridge_dev *sbridge_dev;struct pci_id_table *ptable = (struct pci_id_table *)id->driver_data;/* get the pci devices we want to reserve for our use */ if (unlikely(rc < 0 )) {0 , "couldn't get all devices\n" );goto fail0;0 ;0 , "Registering MC#%d (%d of %d)\n" ,1 , num_mc);if (unlikely(rc < 0 ))goto fail1;"%s\n" , SBRIDGE_REVISION);return 0 ;return rc;/* * sbridge_remove cleanup * static void sbridge_remove(void )struct sbridge_dev *sbridge_dev;0 , "\n" );/* Release PCI resources */ /* * sbridge_init Module entry function * Try to initialize this module for its devices static int __init sbridge_init(void )const struct x86_cpu_id *id;const char *owner;int rc;2 , "\n" );if (ghes_get_devices())return -EBUSY;if (owner && strncmp(owner, EDAC_MOD_STR, sizeof (EDAC_MOD_STR)))return -EBUSY;if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))return -ENODEV;if (!id)return -ENODEV;/* Ensure that the OPSTATE is set correctly for POLL or NMI */ if (rc >= 0 ) {return 0 ;"Failed to register device with error %d.\n" ,return rc;/* * sbridge_exit ( ) Module exit function * Unregister the driver static void __exit sbridge_exit(void )2 , "\n" );int , 0444 );"EDAC Error Reporting state: 0=Poll,1=NMI" );"GPL" );"Mauro Carvalho Chehab" );"Red Hat Inc. (https://www.redhat.com) "); "MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - " Messung V0.5 in Prozent C=95 H=88 G=91
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