Quelle xilinx_dpdma.c
Sprache: C
// SPDX-License-Identifier: GPL-2.0 /* * Xilinx ZynqMP DPDMA Engine driver * * Copyright ( C ) 2015 - 2020 Xilinx , Inc . * * Author : Hyun Woo Kwon < hyun . kwon @ xilinx . com > #include <linux/bitfield.h>#include <linux/bits.h>#include <linux/clk.h>#include <linux/debugfs.h>#include <linux/delay.h>#include <linux/dma/xilinx_dpdma.h>#include <linux/dmaengine.h>#include <linux/dmapool.h>#include <linux/interrupt.h>#include <linux/module.h>#include <linux/of.h>#include <linux/of_dma.h>#include <linux/platform_device.h>#include <linux/sched.h>#include <linux/slab.h>#include <linux/spinlock.h>#include <linux/wait.h>#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>#include "../dmaengine.h" #include "../virt-dma.h" /* DPDMA registers */ #define XILINX_DPDMA_ERR_CTRL 0 x000#define XILINX_DPDMA_ISR 0 x004#define XILINX_DPDMA_IMR 0 x008#define XILINX_DPDMA_IEN 0 x00c#define XILINX_DPDMA_IDS 0 x010#define XILINX_DPDMA_INTR_DESC_DONE(n) BIT((n) + 0 )#define XILINX_DPDMA_INTR_DESC_DONE_MASK GENMASK(5 , 0 )#define XILINX_DPDMA_INTR_NO_OSTAND(n) BIT((n) + 6 )#define XILINX_DPDMA_INTR_NO_OSTAND_MASK GENMASK(11 , 6 )#define XILINX_DPDMA_INTR_AXI_ERR(n) BIT((n) + 12 )#define XILINX_DPDMA_INTR_AXI_ERR_MASK GENMASK(17 , 12 )#define XILINX_DPDMA_INTR_DESC_ERR(n) BIT((n) + 16 )#define XILINX_DPDMA_INTR_DESC_ERR_MASK GENMASK(23 , 18 )#define XILINX_DPDMA_INTR_WR_CMD_FIFO_FULL BIT(24 )#define XILINX_DPDMA_INTR_WR_DATA_FIFO_FULL BIT(25 )#define XILINX_DPDMA_INTR_AXI_4K_CROSS BIT(26 )#define XILINX_DPDMA_INTR_VSYNC BIT(27 )#define XILINX_DPDMA_INTR_CHAN_ERR_MASK 0 x00041000#define XILINX_DPDMA_INTR_CHAN_ERR 0 x00fff000#define XILINX_DPDMA_INTR_GLOBAL_ERR 0 x07000000#define XILINX_DPDMA_INTR_ERR_ALL 0 x07fff000#define XILINX_DPDMA_INTR_CHAN_MASK 0 x00041041#define XILINX_DPDMA_INTR_GLOBAL_MASK 0 x0f000000#define XILINX_DPDMA_INTR_ALL 0 x0fffffff#define XILINX_DPDMA_EISR 0 x014#define XILINX_DPDMA_EIMR 0 x018#define XILINX_DPDMA_EIEN 0 x01c#define XILINX_DPDMA_EIDS 0 x020#define XILINX_DPDMA_EINTR_INV_APB BIT(0 )#define XILINX_DPDMA_EINTR_RD_AXI_ERR(n) BIT((n) + 1 )#define XILINX_DPDMA_EINTR_RD_AXI_ERR_MASK GENMASK(6 , 1 )#define XILINX_DPDMA_EINTR_PRE_ERR(n) BIT((n) + 7 )#define XILINX_DPDMA_EINTR_PRE_ERR_MASK GENMASK(12 , 7 )#define XILINX_DPDMA_EINTR_CRC_ERR(n) BIT((n) + 13 )#define XILINX_DPDMA_EINTR_CRC_ERR_MASK GENMASK(18 , 13 )#define XILINX_DPDMA_EINTR_WR_AXI_ERR(n) BIT((n) + 19 )#define XILINX_DPDMA_EINTR_WR_AXI_ERR_MASK GENMASK(24 , 19 )#define XILINX_DPDMA_EINTR_DESC_DONE_ERR(n) BIT((n) + 25 )#define XILINX_DPDMA_EINTR_DESC_DONE_ERR_MASK GENMASK(30 , 25 )#define XILINX_DPDMA_EINTR_RD_CMD_FIFO_FULL BIT(32 )#define XILINX_DPDMA_EINTR_CHAN_ERR_MASK 0 x02082082#define XILINX_DPDMA_EINTR_CHAN_ERR 0 x7ffffffe#define XILINX_DPDMA_EINTR_GLOBAL_ERR 0 x80000001#define XILINX_DPDMA_EINTR_ALL 0 xffffffff#define XILINX_DPDMA_CNTL 0 x100#define XILINX_DPDMA_GBL 0 x104#define XILINX_DPDMA_GBL_TRIG_MASK(n) ((n) << 0 )#define XILINX_DPDMA_GBL_RETRIG_MASK(n) ((n) << 6 )#define XILINX_DPDMA_ALC0_CNTL 0 x108#define XILINX_DPDMA_ALC0_STATUS 0 x10c#define XILINX_DPDMA_ALC0_MAX 0 x110#define XILINX_DPDMA_ALC0_MIN 0 x114#define XILINX_DPDMA_ALC0_ACC 0 x118#define XILINX_DPDMA_ALC0_ACC_TRAN 0 x11c#define XILINX_DPDMA_ALC1_CNTL 0 x120#define XILINX_DPDMA_ALC1_STATUS 0 x124#define XILINX_DPDMA_ALC1_MAX 0 x128#define XILINX_DPDMA_ALC1_MIN 0 x12c#define XILINX_DPDMA_ALC1_ACC 0 x130#define XILINX_DPDMA_ALC1_ACC_TRAN 0 x134/* Channel register */ #define XILINX_DPDMA_CH_BASE 0 x200#define XILINX_DPDMA_CH_OFFSET 0 x100#define XILINX_DPDMA_CH_DESC_START_ADDRE 0 x000#define XILINX_DPDMA_CH_DESC_START_ADDRE_MASK GENMASK(15 , 0 )#define XILINX_DPDMA_CH_DESC_START_ADDR 0 x004#define XILINX_DPDMA_CH_DESC_NEXT_ADDRE 0 x008#define XILINX_DPDMA_CH_DESC_NEXT_ADDR 0 x00c#define XILINX_DPDMA_CH_PYLD_CUR_ADDRE 0 x010#define XILINX_DPDMA_CH_PYLD_CUR_ADDR 0 x014#define XILINX_DPDMA_CH_CNTL 0 x018#define XILINX_DPDMA_CH_CNTL_ENABLE BIT(0 )#define XILINX_DPDMA_CH_CNTL_PAUSE BIT(1 )#define XILINX_DPDMA_CH_CNTL_QOS_DSCR_WR_MASK GENMASK(5 , 2 )#define XILINX_DPDMA_CH_CNTL_QOS_DSCR_RD_MASK GENMASK(9 , 6 )#define XILINX_DPDMA_CH_CNTL_QOS_DATA_RD_MASK GENMASK(13 , 10 )#define XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS 11 #define XILINX_DPDMA_CH_STATUS 0 x01c#define XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK GENMASK(24 , 21 )#define XILINX_DPDMA_CH_VDO 0 x020#define XILINX_DPDMA_CH_PYLD_SZ 0 x024#define XILINX_DPDMA_CH_DESC_ID 0 x028#define XILINX_DPDMA_CH_DESC_ID_MASK GENMASK(15 , 0 )/* DPDMA descriptor fields */ #define XILINX_DPDMA_DESC_CONTROL_PREEMBLE 0 xa5#define XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR BIT(8 )#define XILINX_DPDMA_DESC_CONTROL_DESC_UPDATE BIT(9 )#define XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE BIT(10 )#define XILINX_DPDMA_DESC_CONTROL_FRAG_MODE BIT(18 )#define XILINX_DPDMA_DESC_CONTROL_LAST BIT(19 )#define XILINX_DPDMA_DESC_CONTROL_ENABLE_CRC BIT(20 )#define XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME BIT(21 )#define XILINX_DPDMA_DESC_ID_MASK GENMASK(15 , 0 )#define XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK GENMASK(17 , 0 )#define XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK GENMASK(31 , 18 )#define XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK GENMASK(15 , 0 )#define XILINX_DPDMA_DESC_ADDR_EXT_SRC_ADDR_MASK GENMASK(31 , 16 )#define XILINX_DPDMA_ALIGN_BYTES 256 #define XILINX_DPDMA_LINESIZE_ALIGN_BITS 128 #define XILINX_DPDMA_NUM_CHAN 6 struct xilinx_dpdma_chan;/** * struct xilinx_dpdma_hw_desc - DPDMA hardware descriptor * @ control : control configuration field * @ desc_id : descriptor ID * @ xfer_size : transfer size * @ hsize_stride : horizontal size and stride * @ timestamp_lsb : LSB of time stamp * @ timestamp_msb : MSB of time stamp * @ addr_ext : upper 16 bit of 48 bit address ( next_desc and src_addr ) * @ next_desc : next descriptor 32 bit address * @ src_addr : payload source address ( 1 st page , 32 LSB ) * @ addr_ext_23 : payload source address ( 2 nd and 3 rd pages , 16 LSBs ) * @ addr_ext_45 : payload source address ( 4 th and 5 th pages , 16 LSBs ) * @ src_addr2 : payload source address ( 2 nd page , 32 LSB ) * @ src_addr3 : payload source address ( 3 rd page , 32 LSB ) * @ src_addr4 : payload source address ( 4 th page , 32 LSB ) * @ src_addr5 : payload source address ( 5 th page , 32 LSB ) * @ crc : descriptor CRC struct xilinx_dpdma_hw_desc {/** * struct xilinx_dpdma_sw_desc - DPDMA software descriptor * @ hw : DPDMA hardware descriptor * @ node : list node for software descriptors * @ dma_addr : DMA address of the software descriptor struct xilinx_dpdma_sw_desc {struct xilinx_dpdma_hw_desc hw;struct list_head node;/** * struct xilinx_dpdma_tx_desc - DPDMA transaction descriptor * @ vdesc : virtual DMA descriptor * @ chan : DMA channel * @ descriptors : list of software descriptors * @ error : an error has been detected with this descriptor struct xilinx_dpdma_tx_desc {struct virt_dma_desc vdesc;struct xilinx_dpdma_chan *chan;struct list_head descriptors;bool error;#define to_dpdma_tx_desc(_desc) \struct xilinx_dpdma_tx_desc, vdesc)/** * struct xilinx_dpdma_chan - DPDMA channel * @ vchan : virtual DMA channel * @ reg : register base address * @ id : channel ID * @ wait_to_stop : queue to wait for outstanding transactions before stopping * @ running : true if the channel is running * @ first_frame : flag for the first frame of stream * @ video_group : flag if multi - channel operation is needed for video channels * @ lock : lock to access struct xilinx_dpdma_chan . Must be taken before * @ vchan . lock , if both are to be held . * @ desc_pool : descriptor allocation pool * @ err_task : error IRQ bottom half handler * @ desc : References to descriptors being processed * @ desc . pending : Descriptor schedule to the hardware , pending execution * @ desc . active : Descriptor being executed by the hardware * @ xdev : DPDMA device struct xilinx_dpdma_chan {struct virt_dma_chan vchan;void __iomem *reg;unsigned int id;bool running;bool first_frame;bool video_group;/* lock to access struct xilinx_dpdma_chan */ struct dma_pool *desc_pool;struct tasklet_struct err_task;struct {struct xilinx_dpdma_tx_desc *pending;struct xilinx_dpdma_tx_desc *active;struct xilinx_dpdma_device *xdev;#define to_xilinx_chan(_chan) \struct xilinx_dpdma_chan, vchan.chan)/** * struct xilinx_dpdma_device - DPDMA device * @ common : generic dma device structure * @ reg : register base address * @ dev : generic device structure * @ irq : the interrupt number * @ axi_clk : axi clock * @ chan : DPDMA channels * @ ext_addr : flag for 64 bit system ( 48 bit addressing ) struct xilinx_dpdma_device {struct dma_device common;void __iomem *reg;struct device *dev;int irq;struct clk *axi_clk;struct xilinx_dpdma_chan *chan[XILINX_DPDMA_NUM_CHAN];bool ext_addr;/* ----------------------------------------------------------------------------- * DebugFS #define XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE 32 #define XILINX_DPDMA_DEBUGFS_UINT16_MAX_STR "65535" /* Match xilinx_dpdma_testcases vs dpdma_debugfs_reqs[] entry */ enum xilinx_dpdma_testcases {struct xilinx_dpdma_debugfs {enum xilinx_dpdma_testcases testcase;unsigned int chan_id;static struct xilinx_dpdma_debugfs dpdma_debugfs;struct xilinx_dpdma_debugfs_request {const char *name;enum xilinx_dpdma_testcases tc;char *buf);int (*write)(char *args);static void xilinx_dpdma_debugfs_desc_done_irq(struct xilinx_dpdma_chan *chan)if (IS_ENABLED(CONFIG_DEBUG_FS) && chan->id == dpdma_debugfs.chan_id)static ssize_t xilinx_dpdma_debugfs_desc_done_irq_read(char *buf)1 );"%d" ,return 0 ;static int xilinx_dpdma_debugfs_desc_done_irq_write(char *args)char *arg;int ret;" " );if (!arg || strncasecmp(arg, "start" , 5 ))return -EINVAL;" " );if (!arg)return -EINVAL;0 , &id);if (ret < 0 )return ret;if (id < ZYNQMP_DPDMA_VIDEO0 || id > ZYNQMP_DPDMA_AUDIO1)return -EINVAL;0 ;return 0 ;/* Match xilinx_dpdma_testcases vs dpdma_debugfs_reqs[] entry */ static struct xilinx_dpdma_debugfs_request dpdma_debugfs_reqs[] = {"DESCRIPTOR_DONE_INTR" ,static ssize_t xilinx_dpdma_debugfs_read(struct file *f, char __user *buf,enum xilinx_dpdma_testcases testcase;char *kern_buff;int ret = 0 ;if (*pos != 0 || size <= 0 )return -EINVAL;if (!kern_buff) {return -ENOMEM;if (testcase != DPDMA_TC_NONE) {if (ret < 0 )goto done;else {"No testcase executed" ,if (copy_to_user(buf, kern_buff, size))if (ret)return ret;1 ;return size;static ssize_t xilinx_dpdma_debugfs_write(struct file *f,const char __user *buf, size_t size,char *kern_buff, *kern_buff_start;char *testcase;unsigned int i;int ret;if (*pos != 0 || size <= 0 )return -EINVAL;/* Supporting single instance of test as of now. */ if (dpdma_debugfs.testcase != DPDMA_TC_NONE)return -EBUSY;if (!kern_buff)return -ENOMEM;if (ret < 0 )goto done;/* Read the testcase name from a user request. */ " " );for (i = 0 ; i < ARRAY_SIZE(dpdma_debugfs_reqs); i++) {if (!strcasecmp(testcase, dpdma_debugfs_reqs[i].name))break ;if (i == ARRAY_SIZE(dpdma_debugfs_reqs)) {goto done;if (ret < 0 )goto done;return ret;static const struct file_operations fops_xilinx_dpdma_dbgfs = {static void xilinx_dpdma_debugfs_init(struct xilinx_dpdma_device *xdev)struct dentry *dent;"testcase" , 0444 , xdev->common.dbg_dev_root,if (IS_ERR(dent))"Failed to create debugfs testcase file\n" );/* ----------------------------------------------------------------------------- * I / O Accessors static inline u32 dpdma_read(void __iomem *base, u32 offset)return ioread32(base + offset);static inline void dpdma_write(void __iomem *base, u32 offset, u32 val)static inline void dpdma_clr(void __iomem *base, u32 offset, u32 clr)static inline void dpdma_set(void __iomem *base, u32 offset, u32 set)/* ----------------------------------------------------------------------------- * Descriptor Operations /** * xilinx_dpdma_sw_desc_set_dma_addrs - Set DMA addresses in the descriptor * @ xdev : DPDMA device * @ sw_desc : The software descriptor in which to set DMA addresses * @ prev : The previous descriptor * @ dma_addr : array of dma addresses * @ num_src_addr : number of addresses in @ dma_addr * * Set all the DMA addresses in the hardware descriptor corresponding to @ dev * from @ dma_addr . If a previous descriptor is specified in @ prev , its next * descriptor DMA address is set to the DMA address of @ sw_desc . @ prev may be * identical to @ sw_desc for cyclic transfers . static void xilinx_dpdma_sw_desc_set_dma_addrs(struct xilinx_dpdma_device *xdev,struct xilinx_dpdma_sw_desc *sw_desc,struct xilinx_dpdma_sw_desc *prev,unsigned int num_src_addr)struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;unsigned int i;0 ]);if (xdev->ext_addr)0 ]));for (i = 1 ; i < num_src_addr; i++) {1 ] = lower_32_bits(dma_addr[i]);if (xdev->ext_addr) {15 , 0 );16 * ((i - 1 ) % 2 );1 ) / 2 ] |= addr_msb;if (!prev)return ;if (xdev->ext_addr)/** * xilinx_dpdma_chan_alloc_sw_desc - Allocate a software descriptor * @ chan : DPDMA channel * * Allocate a software descriptor from the channel ' s descriptor pool . * * Return : a software descriptor or NULL . static struct xilinx_dpdma_sw_desc *struct xilinx_dpdma_chan *chan)struct xilinx_dpdma_sw_desc *sw_desc;if (!sw_desc)return NULL;return sw_desc;/** * xilinx_dpdma_chan_free_sw_desc - Free a software descriptor * @ chan : DPDMA channel * @ sw_desc : software descriptor to free * * Free a software descriptor from the channel ' s descriptor pool . static void struct xilinx_dpdma_chan *chan,struct xilinx_dpdma_sw_desc *sw_desc)/** * xilinx_dpdma_chan_dump_tx_desc - Dump a tx descriptor * @ chan : DPDMA channel * @ tx_desc : tx descriptor to dump * * Dump contents of a tx descriptor static void xilinx_dpdma_chan_dump_tx_desc(struct xilinx_dpdma_chan *chan,struct xilinx_dpdma_tx_desc *tx_desc)struct xilinx_dpdma_sw_desc *sw_desc;struct device *dev = chan->xdev->dev;unsigned int i = 0 ;"------- TX descriptor dump start -------\n" );"------- channel ID = %d -------\n" , chan->id);struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;"------- HW descriptor %d -------\n" , i++);"descriptor DMA addr: %pad\n" , &sw_desc->dma_addr);"control: 0x%08x\n" , hw_desc->control);"desc_id: 0x%08x\n" , hw_desc->desc_id);"xfer_size: 0x%08x\n" , hw_desc->xfer_size);"hsize_stride: 0x%08x\n" , hw_desc->hsize_stride);"timestamp_lsb: 0x%08x\n" , hw_desc->timestamp_lsb);"timestamp_msb: 0x%08x\n" , hw_desc->timestamp_msb);"addr_ext: 0x%08x\n" , hw_desc->addr_ext);"next_desc: 0x%08x\n" , hw_desc->next_desc);"src_addr: 0x%08x\n" , hw_desc->src_addr);"addr_ext_23: 0x%08x\n" , hw_desc->addr_ext_23);"addr_ext_45: 0x%08x\n" , hw_desc->addr_ext_45);"src_addr2: 0x%08x\n" , hw_desc->src_addr2);"src_addr3: 0x%08x\n" , hw_desc->src_addr3);"src_addr4: 0x%08x\n" , hw_desc->src_addr4);"src_addr5: 0x%08x\n" , hw_desc->src_addr5);"crc: 0x%08x\n" , hw_desc->crc);"------- TX descriptor dump end -------\n" );/** * xilinx_dpdma_chan_alloc_tx_desc - Allocate a transaction descriptor * @ chan : DPDMA channel * * Allocate a tx descriptor . * * Return : a tx descriptor or NULL . static struct xilinx_dpdma_tx_desc *struct xilinx_dpdma_chan *chan)struct xilinx_dpdma_tx_desc *tx_desc;sizeof (*tx_desc), GFP_NOWAIT);if (!tx_desc)return NULL;false ;return tx_desc;/** * xilinx_dpdma_chan_free_tx_desc - Free a virtual DMA descriptor * @ vdesc : virtual DMA descriptor * * Free the virtual DMA descriptor @ vdesc including its software descriptors . static void xilinx_dpdma_chan_free_tx_desc(struct virt_dma_desc *vdesc)struct xilinx_dpdma_sw_desc *sw_desc, *next;struct xilinx_dpdma_tx_desc *desc;if (!vdesc)return ;/** * xilinx_dpdma_chan_prep_cyclic - Prepare a cyclic dma descriptor * @ chan : DPDMA channel * @ buf_addr : buffer address * @ buf_len : buffer length * @ period_len : number of periods * @ flags : tx flags argument passed in to prepare function * * Prepare a tx descriptor incudling internal software / hardware descriptors * for the given cyclic transaction . * * Return : A dma async tx descriptor on success , or NULL . static struct dma_async_tx_descriptor *struct xilinx_dpdma_chan *chan,unsigned long flags)struct xilinx_dpdma_tx_desc *tx_desc;struct xilinx_dpdma_sw_desc *sw_desc, *last = NULL;unsigned int periods = buf_len / period_len;unsigned int i;if (!tx_desc)return NULL;for (i = 0 ; i < periods; i++) {struct xilinx_dpdma_hw_desc *hw_desc;if (!IS_ALIGNED(buf_addr, XILINX_DPDMA_ALIGN_BYTES)) {"buffer should be aligned at %d B\n" ,goto error;if (!sw_desc)goto error;1 );struct xilinx_dpdma_sw_desc, node);if (chan->xdev->ext_addr)return vchan_tx_prep(&chan->vchan, &tx_desc->vdesc, flags);return NULL;/** * xilinx_dpdma_chan_prep_interleaved_dma - Prepare an interleaved dma * descriptor * @ chan : DPDMA channel * @ xt : dma interleaved template * * Prepare a tx descriptor including internal software / hardware descriptors * based on @ xt . * * Return : A DPDMA TX descriptor on success , or NULL . static struct xilinx_dpdma_tx_desc *struct xilinx_dpdma_chan *chan,struct dma_interleaved_template *xt)struct xilinx_dpdma_tx_desc *tx_desc;struct xilinx_dpdma_sw_desc *sw_desc;struct xilinx_dpdma_hw_desc *hw_desc;0 ].size;0 ].icg;if (!IS_ALIGNED(xt->src_start, XILINX_DPDMA_ALIGN_BYTES)) {"chan%u: buffer should be aligned at %d B\n" ,return NULL;if (!tx_desc)return NULL;if (!sw_desc) {return NULL;1 );8 );16 );return tx_desc;/* ----------------------------------------------------------------------------- * DPDMA Channel Operations /** * xilinx_dpdma_chan_enable - Enable the channel * @ chan : DPDMA channel * * Enable the channel and its interrupts . Set the QoS values for video class . static void xilinx_dpdma_chan_enable(struct xilinx_dpdma_chan *chan)/** * xilinx_dpdma_chan_disable - Disable the channel * @ chan : DPDMA channel * * Disable the channel and its interrupts . static void xilinx_dpdma_chan_disable(struct xilinx_dpdma_chan *chan)/** * xilinx_dpdma_chan_pause - Pause the channel * @ chan : DPDMA channel * * Pause the channel . static void xilinx_dpdma_chan_pause(struct xilinx_dpdma_chan *chan)/** * xilinx_dpdma_chan_unpause - Unpause the channel * @ chan : DPDMA channel * * Unpause the channel . static void xilinx_dpdma_chan_unpause(struct xilinx_dpdma_chan *chan)static u32 xilinx_dpdma_chan_video_group_ready(struct xilinx_dpdma_chan *chan)struct xilinx_dpdma_device *xdev = chan->xdev;0 ;unsigned int i;for (i = ZYNQMP_DPDMA_VIDEO0; i <= ZYNQMP_DPDMA_VIDEO2; i++) {if (xdev->chan[i]->video_group && !xdev->chan[i]->running)return 0 ;if (xdev->chan[i]->video_group)return channels;/** * xilinx_dpdma_chan_queue_transfer - Queue the next transfer * @ chan : DPDMA channel * * Queue the next descriptor , if any , to the hardware . If the channel is * stopped , start it first . Otherwise retrigger it with the next descriptor . static void xilinx_dpdma_chan_queue_transfer(struct xilinx_dpdma_chan *chan)struct xilinx_dpdma_device *xdev = chan->xdev;struct xilinx_dpdma_sw_desc *sw_desc;struct xilinx_dpdma_tx_desc *desc;struct virt_dma_desc *vdesc;bool first_frame;if (chan->desc.pending)return ;if (!chan->running) {true ;true ;if (!vdesc)return ;/* * Assign the cookie to descriptors in this transaction . Only 16 bit * will be used , but it should be enough . struct xilinx_dpdma_sw_desc, node);if (xdev->ext_addr)false ;if (chan->video_group) {/* * Trigger the transfer only when all channels in the group are * ready . if (!channels)return ;else {if (first_frame)else /** * xilinx_dpdma_chan_ostand - Number of outstanding transactions * @ chan : DPDMA channel * * Read and return the number of outstanding transactions from register . * * Return : Number of outstanding transactions from the status register . static u32 xilinx_dpdma_chan_ostand(struct xilinx_dpdma_chan *chan)return FIELD_GET(XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK,/** * xilinx_dpdma_chan_notify_no_ostand - Notify no outstanding transaction event * @ chan : DPDMA channel * * Notify waiters for no outstanding event , so waiters can stop the channel * safely . This function is supposed to be called when ' no outstanding ' * interrupt is generated . The ' no outstanding ' interrupt is disabled and * should be re - enabled when this event is handled . If the channel status * register still shows some number of outstanding transactions , the interrupt * remains enabled . * * Return : 0 on success . On failure , - EWOULDBLOCK if there ' s still outstanding * transaction ( s ) . static int xilinx_dpdma_chan_notify_no_ostand(struct xilinx_dpdma_chan *chan)if (cnt) {"chan%u: %d outstanding transactions\n" ,return -EWOULDBLOCK;/* Disable 'no outstanding' interrupt */ return 0 ;/** * xilinx_dpdma_chan_wait_no_ostand - Wait for the no outstanding irq * @ chan : DPDMA channel * * Wait for the no outstanding transaction interrupt . This functions can sleep * for 50 ms . * * Return : 0 on success . On failure , - ETIMEOUT for time out , or the error code * from wait_event_interruptible_timeout ( ) . static int xilinx_dpdma_chan_wait_no_ostand(struct xilinx_dpdma_chan *chan)int ret;/* Wait for a no outstanding transaction interrupt upto 50msec */ 50 ));if (ret > 0 ) {return 0 ;"chan%u: not ready to stop: %d trans\n" ,if (ret == 0 )return -ETIMEDOUT;return ret;/** * xilinx_dpdma_chan_poll_no_ostand - Poll the outstanding transaction status * @ chan : DPDMA channel * * Poll the outstanding transaction status , and return when there ' s no * outstanding transaction . This functions can be used in the interrupt context * or where the atomicity is required . Calling thread may wait more than 50 ms . * * Return : 0 on success , or - ETIMEDOUT . static int xilinx_dpdma_chan_poll_no_ostand(struct xilinx_dpdma_chan *chan)50000 ;/* Poll at least for 50ms (20 fps). */ do {1 );while (loop-- > 0 && cnt);if (loop) {return 0 ;"chan%u: not ready to stop: %d trans\n" ,return -ETIMEDOUT;/** * xilinx_dpdma_chan_stop - Stop the channel * @ chan : DPDMA channel * * Stop a previously paused channel by first waiting for completion of all * outstanding transaction and then disabling the channel . * * Return : 0 on success , or - ETIMEDOUT if the channel failed to stop . static int xilinx_dpdma_chan_stop(struct xilinx_dpdma_chan *chan)unsigned long flags;int ret;if (ret)return ret;false ;return 0 ;/** * xilinx_dpdma_chan_done_irq - Handle hardware descriptor completion * @ chan : DPDMA channel * * Handle completion of the currently active descriptor ( @ chan - > desc . active ) . As * we currently support cyclic transfers only , this just invokes the cyclic * callback . The descriptor will be completed at the VSYNC interrupt when a new * descriptor replaces it . static void xilinx_dpdma_chan_done_irq(struct xilinx_dpdma_chan *chan)struct xilinx_dpdma_tx_desc *active;if (active)else "chan%u: DONE IRQ with no active descriptor!\n" ,/** * xilinx_dpdma_chan_vsync_irq - Handle hardware descriptor scheduling * @ chan : DPDMA channel * * At VSYNC the active descriptor may have been replaced by the pending * descriptor . Detect this through the DESC_ID and perform appropriate * bookkeeping . static void xilinx_dpdma_chan_vsync_irq(struct xilinx_dpdma_chan *chan)struct xilinx_dpdma_tx_desc *pending;struct xilinx_dpdma_sw_desc *sw_desc;if (!chan->running || !pending)goto out;/* If the retrigger raced with vsync, retry at the next frame. */ struct xilinx_dpdma_sw_desc, node);if (sw_desc->hw.desc_id != desc_id) {"chan%u: vsync race lost (%u != %u), retrying\n" ,goto out;/* * Complete the active descriptor , if any , promote the pending * descriptor to active , and queue the next transfer , if any . if (chan->desc.active)/** * xilinx_dpdma_chan_err - Detect any channel error * @ chan : DPDMA channel * @ isr : masked Interrupt Status Register * @ eisr : Error Interrupt Status Register * * Return : true if any channel error occurs , or false otherwise . static bool struct xilinx_dpdma_chan *chan, u32 isr, u32 eisr)if (!chan)return false ;if (chan->running &&return true ;return false ;/** * xilinx_dpdma_chan_handle_err - DPDMA channel error handling * @ chan : DPDMA channel * * This function is called when any channel error or any global error occurs . * The function disables the paused channel by errors and determines * if the current active descriptor can be rescheduled depending on * the descriptor status . static void xilinx_dpdma_chan_handle_err(struct xilinx_dpdma_chan *chan)struct xilinx_dpdma_device *xdev = chan->xdev;struct xilinx_dpdma_tx_desc *active;unsigned long flags;"chan%u: cur desc addr = 0x%04x%08x\n" ,"chan%u: cur payload addr = 0x%04x%08x\n" ,false ;if (!chan->desc.active)goto out_unlock;if (active->error)"chan%u: repeated error on desc\n" ,/* Reschedule if there's no new descriptor */ if (!chan->desc.pending &&true ;else {/* ----------------------------------------------------------------------------- * DMA Engine Operations static struct dma_async_tx_descriptor *struct dma_chan *dchan, dma_addr_t buf_addr,enum dma_transfer_direction direction,unsigned long flags)struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);if (direction != DMA_MEM_TO_DEV)return NULL;if (buf_len % period_len)return NULL;return xilinx_dpdma_chan_prep_cyclic(chan, buf_addr, buf_len,static struct dma_async_tx_descriptor *struct dma_chan *dchan,struct dma_interleaved_template *xt,unsigned long flags)struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);struct xilinx_dpdma_tx_desc *desc;if (xt->dir != DMA_MEM_TO_DEV)return NULL;if (!xt->numf || !xt->sgl[0 ].size)return NULL;if (!(flags & DMA_PREP_REPEAT) || !(flags & DMA_PREP_LOAD_EOT))return NULL;if (!desc)return NULL;return &desc->vdesc.tx;/** * xilinx_dpdma_alloc_chan_resources - Allocate resources for the channel * @ dchan : DMA channel * * Allocate a descriptor pool for the channel . * * Return : 0 on success , or - ENOMEM if failed to allocate a pool . static int xilinx_dpdma_alloc_chan_resources(struct dma_chan *dchan)struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);struct xilinx_dpdma_sw_desc);sizeof (struct xilinx_dpdma_sw_desc),0 );if (!chan->desc_pool) {"chan%u: failed to allocate a descriptor pool\n" ,return -ENOMEM;return 0 ;/** * xilinx_dpdma_free_chan_resources - Free all resources for the channel * @ dchan : DMA channel * * Free resources associated with the virtual DMA channel , and destroy the * descriptor pool . static void xilinx_dpdma_free_chan_resources(struct dma_chan *dchan)struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);static void xilinx_dpdma_issue_pending(struct dma_chan *dchan)struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);unsigned long flags;if (vchan_issue_pending(&chan->vchan))static int xilinx_dpdma_config(struct dma_chan *dchan,struct dma_slave_config *config)struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);struct xilinx_dpdma_peripheral_config *pconfig;unsigned long flags;/* * The destination address doesn ' t need to be specified as the DPDMA is * hardwired to the destination ( the DP controller ) . The transfer * width , burst size and port window size are thus meaningless , they ' re * fixed both on the DPDMA side and on the DP controller side . /* * Use the peripheral_config to indicate that the channel is part * of a video group . This requires matching use of the custom * structure in each driver . if (WARN_ON(pconfig && config->peripheral_size != sizeof (*pconfig)))return -EINVAL;if (chan->id <= ZYNQMP_DPDMA_VIDEO2 && pconfig)return 0 ;static int xilinx_dpdma_pause(struct dma_chan *dchan)return 0 ;static int xilinx_dpdma_resume(struct dma_chan *dchan)return 0 ;/** * xilinx_dpdma_terminate_all - Terminate the channel and descriptors * @ dchan : DMA channel * * Pause the channel without waiting for ongoing transfers to complete . Waiting * for completion is performed by xilinx_dpdma_synchronize ( ) that will disable * the channel to complete the stop . * * All the descriptors associated with the channel that are guaranteed not to * be touched by the hardware . The pending and active descriptor are not * touched , and will be freed either upon completion , or by * xilinx_dpdma_synchronize ( ) . * * Return : 0 on success , or - ETIMEDOUT if the channel failed to stop . static int xilinx_dpdma_terminate_all(struct dma_chan *dchan)struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);struct xilinx_dpdma_device *xdev = chan->xdev;unsigned long flags;unsigned int i;/* Pause the channel (including the whole video group if applicable). */ if (chan->video_group) {for (i = ZYNQMP_DPDMA_VIDEO0; i <= ZYNQMP_DPDMA_VIDEO2; i++) {if (xdev->chan[i]->video_group &&false ;else {/* Gather all the descriptors we can free and free them. */ return 0 ;/** * xilinx_dpdma_synchronize - Synchronize callback execution * @ dchan : DMA channel * * Synchronizing callback execution ensures that all previously issued * transfers have completed and all associated callbacks have been called and * have returned . * * This function waits for the DMA channel to stop . It assumes it has been * paused by a previous call to dmaengine_terminate_async ( ) , and that no new * pending descriptors have been issued with dma_async_issue_pending ( ) . The * behaviour is undefined otherwise . static void xilinx_dpdma_synchronize(struct dma_chan *dchan)struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);unsigned long flags;if (chan->desc.pending) {if (chan->desc.active) {/* ----------------------------------------------------------------------------- * Interrupt and Tasklet Handling /** * xilinx_dpdma_err - Detect any global error * @ isr : Interrupt Status Register * @ eisr : Error Interrupt Status Register * * Return : True if any global error occurs , or false otherwise . static bool xilinx_dpdma_err(u32 isr, u32 eisr)if (isr & XILINX_DPDMA_INTR_GLOBAL_ERR ||return true ;return false ;/** * xilinx_dpdma_handle_err_irq - Handle DPDMA error interrupt * @ xdev : DPDMA device * @ isr : masked Interrupt Status Register * @ eisr : Error Interrupt Status Register * * Handle if any error occurs based on @ isr and @ eisr . This function disables * corresponding error interrupts , and those should be re - enabled once handling * is done . static void xilinx_dpdma_handle_err_irq(struct xilinx_dpdma_device *xdev,bool err = xilinx_dpdma_err(isr, eisr);unsigned int i;"error irq: isr = 0x%08x, eisr = 0x%08x\n" ,/* Disable channel error interrupts until errors are handled. */ for (i = 0 ; i < ARRAY_SIZE(xdev->chan); i++)if (err || xilinx_dpdma_chan_err(xdev->chan[i], isr, eisr))/** * xilinx_dpdma_enable_irq - Enable interrupts * @ xdev : DPDMA device * * Enable interrupts . static void xilinx_dpdma_enable_irq(struct xilinx_dpdma_device *xdev)/** * xilinx_dpdma_disable_irq - Disable interrupts * @ xdev : DPDMA device * * Disable interrupts . static void xilinx_dpdma_disable_irq(struct xilinx_dpdma_device *xdev)/** * xilinx_dpdma_chan_err_task - Per channel tasklet for error handling * @ t : pointer to the tasklet associated with this handler * * Per channel error handling tasklet . This function waits for the outstanding * transaction to complete and triggers error handling . After error handling , * re - enable channel error interrupts , and restart the channel if needed . static void xilinx_dpdma_chan_err_task(struct tasklet_struct *t)struct xilinx_dpdma_chan *chan = from_tasklet(chan, t, err_task);struct xilinx_dpdma_device *xdev = chan->xdev;unsigned long flags;/* Proceed error handling even when polling fails. */ static irqreturn_t xilinx_dpdma_irq_handler(int irq, void *data)struct xilinx_dpdma_device *xdev = data;unsigned long mask;unsigned int i;if (!status && !error)return IRQ_NONE;if (status & XILINX_DPDMA_INTR_VSYNC) {/* * There ' s a single VSYNC interrupt that needs to be processed * by each running channel to update the active descriptor . for (i = 0 ; i < ARRAY_SIZE(xdev->chan); i++) {struct xilinx_dpdma_chan *chan = xdev->chan[i];if (chan)if (mask) {if (mask) {if (mask || error)return IRQ_HANDLED;/* ----------------------------------------------------------------------------- * Initialization & Cleanup static int xilinx_dpdma_chan_init(struct xilinx_dpdma_device *xdev,unsigned int chan_id)struct xilinx_dpdma_chan *chan;sizeof (*chan), GFP_KERNEL);if (!chan)return -ENOMEM;false ;return 0 ;static void xilinx_dpdma_chan_remove(struct xilinx_dpdma_chan *chan)if (!chan)return ;static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,struct of_dma *ofdma)struct xilinx_dpdma_device *xdev = ofdma->of_dma_data;0 ];if (chan_id >= ARRAY_SIZE(xdev->chan))return NULL;if (!xdev->chan[chan_id])return NULL;return dma_get_slave_channel(&xdev->chan[chan_id]->vchan.chan);static void dpdma_hw_init(struct xilinx_dpdma_device *xdev)unsigned int i;void __iomem *reg;/* Disable all interrupts */ /* Stop all channels */ for (i = 0 ; i < ARRAY_SIZE(xdev->chan); i++) {/* Clear the interrupt status registers */ static int xilinx_dpdma_probe(struct platform_device *pdev)struct xilinx_dpdma_device *xdev;struct dma_device *ddev;unsigned int i;int ret;sizeof (*xdev), GFP_KERNEL);if (!xdev)return -ENOMEM;sizeof (dma_addr_t) > 4 ;"axi_clk" );if (IS_ERR(xdev->axi_clk))return PTR_ERR(xdev->axi_clk);0 );if (IS_ERR(xdev->reg))return PTR_ERR(xdev->reg);0 );if (xdev->irq < 0 )return xdev->irq;if (ret) {"failed to request IRQ\n" );return ret;1 );/* TODO: Can we achieve better granularity ? */ for (i = 0 ; i < ARRAY_SIZE(xdev->chan); ++i) {if (ret < 0 ) {"failed to initialize channel %u\n" ,goto error;if (ret) {"failed to enable the axi clock\n" );goto error;if (ret) {"failed to register the dma device\n" );goto error_dma_async;if (ret) {"failed to register DMA to DT DMA helper\n" );goto error_of_dma;"Xilinx DPDMA engine is probed\n" );return 0 ;for (i = 0 ; i < ARRAY_SIZE(xdev->chan); i++)return ret;static void xilinx_dpdma_remove(struct platform_device *pdev)struct xilinx_dpdma_device *xdev = platform_get_drvdata(pdev);unsigned int i;/* Start by disabling the IRQ to avoid races during cleanup. */ for (i = 0 ; i < ARRAY_SIZE(xdev->chan); i++)static const struct of_device_id xilinx_dpdma_of_match[] = {"xlnx,zynqmp-dpdma" ,},/* end of table */ }, static struct platform_driver xilinx_dpdma_driver = {"xilinx-zynqmp-dpdma" ,"Xilinx, Inc." );"Xilinx ZynqMP DPDMA driver" );"GPL v2" );
Messung V0.5 in Prozent C=95 H=91 G=92
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(vorverarbeitet am 2026-09-29)
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2026-10-10
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