/* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright(c) 2020-2021 Intel Corporation. */ #ifndef __CXL_MEM_H__#define __CXL_MEM_H__#include <uapi/linux/cxl_mem.h>#include <linux/pci.h>#include <linux/cdev.h>#include <linux/uuid.h>#include <linux/node.h>#include <cxl/event.h>#include <cxl/mailbox.h>#include "cxl.h" /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ #define CXLMDEV_STATUS_OFFSET 0 x0#define CXLMDEV_DEV_FATAL BIT(0 )#define CXLMDEV_FW_HALT BIT(1 )#define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3 , 2 )#define CXLMDEV_MS_NOT_READY 0 #define CXLMDEV_MS_READY 1 #define CXLMDEV_MS_ERROR 2 #define CXLMDEV_MS_DISABLED 3 #define CXLMDEV_READY(status) \#define CXLMDEV_MBOX_IF_READY BIT(4 )#define CXLMDEV_RESET_NEEDED_MASK GENMASK(7 , 5 )#define CXLMDEV_RESET_NEEDED_NOT 0 #define CXLMDEV_RESET_NEEDED_COLD 1 #define CXLMDEV_RESET_NEEDED_WARM 2 #define CXLMDEV_RESET_NEEDED_HOT 3 #define CXLMDEV_RESET_NEEDED_CXL 4 #define CXLMDEV_RESET_NEEDED(status) \/** * struct cxl_memdev - CXL bus object representing a Type - 3 Memory Device * @ dev : driver core device object * @ cdev : char dev core object for ioctl operations * @ cxlds : The device state backing this device * @ detach_work : active memdev lost a port in its ancestry * @ cxl_nvb : coordinate removal of @ cxl_nvd if present * @ cxl_nvd : optional bridge to an nvdimm if the device supports pmem * @ endpoint : connection to the CXL port topology for this memory device * @ id : id number of this memdev instance . * @ depth : endpoint port depth * @ scrub_cycle : current scrub cycle set for this device * @ scrub_region_id : id number of a backed region ( if any ) for which current scrub cycle set * @ err_rec_array : List of xarrarys to store the memdev error records to * check attributes for a memory repair operation are from * current boot . struct cxl_memdev {struct device dev;struct cdev cdev;struct cxl_dev_state *cxlds;struct work_struct detach_work;struct cxl_nvdimm_bridge *cxl_nvb;struct cxl_nvdimm *cxl_nvd;struct cxl_port *endpoint;int id;int depth;int scrub_region_id;void *err_rec_array;static inline struct cxl_memdev *to_cxl_memdev(struct device *dev)return container_of(dev, struct cxl_memdev, dev);static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled)return to_cxl_port(cxled->cxld.dev.parent);static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd)return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent);static inline struct cxl_memdev *struct cxl_endpoint_decoder *cxled)struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent);return to_cxl_memdev(port->uport_dev);bool is_cxl_memdev(const struct device *dev);static inline bool is_cxl_endpoint(struct cxl_port *port)return is_cxl_memdev(port->uport_dev);struct cxl_memdev *devm_cxl_add_memdev(struct device *host,struct cxl_dev_state *cxlds);int devm_cxl_sanitize_setup_notifier(struct device *host,struct cxl_memdev *cxlmd);struct cxl_memdev_state;int devm_cxl_setup_fw_upload(struct device *host, struct cxl_memdev_state *mds);int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled,#define CXL_NR_PARTITIONS_MAX 2 struct cxl_dpa_info {struct cxl_dpa_part_info {struct range range;enum cxl_partition_mode mode;int nr_partitions;int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info);static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port,struct cxl_memdev *cxlmd)if (!port)return NULL;return xa_load(&port->endpoints, (unsigned long )&cxlmd->dev);/* * Per CXL 3 . 0 Section 8 . 2 . 8 . 4 . 5 . 1 #define CMD_CMD_RC_TABLE \0 , NULL), \"background cmd started successfully" ), \"cmd input was invalid" ), \"cmd is not supported" ), \"internal device error" ), \"temporary error, retry once" ), \"ongoing background operation" ), \"media access is disabled" ), \"one FW package can be transferred at a time" ), \"FW package content was transferred out of order" ), \"FW package authentication failed" ), \"FW slot is not supported for requested operation" ), \"rolled back to the previous active FW" ), \"FW failed to activate, needs cold reset" ), \"one or more Event Record Handles were invalid" ), \"physical address specified is invalid" ), \"poison injection limit has been reached" ), \"permanent issue with the media" ), \"background cmd was aborted by device" ), \"not valid in the current security state" ), \"phrase doesn't match current set passphrase" ), \"unsupported on the mailbox it was issued on" ),\"invalid payload length" ), \"invalid or unsupported log page" ), \"asynchronous event occured" ), \"unsupported feature version" ), \"unsupported feature selection value" ), \"feature transfer in progress" ), \"feature transfer out of order" ), \"resources are exhausted" ), \"invalid Extent List" ), \#undef C#define C(a, b, c) CXL_MBOX_CMD_RC_## aenum { CMD_CMD_RC_TABLE };#undef C#define C(a, b, c) { b, c }struct cxl_mbox_cmd_rc {int err;const char *desc;static const struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE };#undef Cstatic inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd)return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc;static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd)return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err;/* * CXL 2 . 0 - Memory capacity multiplier * See Section 8 . 2 . 9 . 5 * * Volatile , Persistent , and Partition capacities are specified to be in * multiples of 256 MB - define a multiplier to convert to / from bytes . #define CXL_CAPACITY_MULTIPLIER SZ_256M/* * Event Interrupt Policy * * CXL rev 3 . 0 section 8 . 2 . 9 . 2 . 4 ; Table 8 - 52 enum cxl_event_int_mode {0 x00,0 x01,0 x02struct cxl_event_interrupt_policy {/** * struct cxl_event_state - Event log driver state * * @ buf : Buffer to receive event data * @ log_lock : Serialize event_buf and log use struct cxl_event_state {struct cxl_get_event_payload *buf;struct mutex log_lock;/* Device enabled poison commands */ enum poison_cmd_enabled_bits {/* Device enabled security commands */ enum security_cmd_enabled_bits {/** * struct cxl_poison_state - Driver poison state info * * @ max_errors : Maximum media error records held in device cache * @ enabled_cmds : All poison commands enabled in the CEL * @ list_out : The poison list payload returned by device * @ mutex : Protect reads of the poison list * * Reads of the poison list are synchronized to ensure that a reader * does not get an incomplete list because their request overlapped * ( was interrupted or preceded by ) another read request of the same * DPA range . CXL Spec 3 . 0 Section 8 . 2 . 9 . 8 . 4 . 1 struct cxl_poison_state {struct cxl_mbox_poison_out *list_out;struct mutex mutex; /* Protect reads of poison list */ /* * Get FW Info * CXL rev 3 . 0 section 8 . 2 . 9 . 3 . 1 ; Table 8 - 56 struct cxl_mbox_get_fw_info {13 ];char slot_1_revision[16 ];char slot_2_revision[16 ];char slot_3_revision[16 ];char slot_4_revision[16 ];#define CXL_FW_INFO_SLOT_INFO_CUR_MASK GENMASK(2 , 0 )#define CXL_FW_INFO_SLOT_INFO_NEXT_MASK GENMASK(5 , 3 )#define CXL_FW_INFO_SLOT_INFO_NEXT_SHIFT 3 #define CXL_FW_INFO_ACTIVATION_CAP_HAS_LIVE_ACTIVATE BIT(0 )/* * Transfer FW Input Payload * CXL rev 3 . 0 section 8 . 2 . 9 . 3 . 2 ; Table 8 - 57 struct cxl_mbox_transfer_fw {2 ];0 x78];#define CXL_FW_TRANSFER_ACTION_FULL 0 x0#define CXL_FW_TRANSFER_ACTION_INITIATE 0 x1#define CXL_FW_TRANSFER_ACTION_CONTINUE 0 x2#define CXL_FW_TRANSFER_ACTION_END 0 x3#define CXL_FW_TRANSFER_ACTION_ABORT 0 x4/* * CXL rev 3 . 0 section 8 . 2 . 9 . 3 . 2 mandates 128 - byte alignment for FW packages * and for each part transferred in a Transfer FW command . #define CXL_FW_TRANSFER_ALIGNMENT 128 /* * Activate FW Input Payload * CXL rev 3 . 0 section 8 . 2 . 9 . 3 . 3 ; Table 8 - 58 struct cxl_mbox_activate_fw {#define CXL_FW_ACTIVATE_ONLINE 0 x0#define CXL_FW_ACTIVATE_OFFLINE 0 x1/* FW state bits */ #define CXL_FW_STATE_BITS 32 #define CXL_FW_CANCEL 0 /** * struct cxl_fw_state - Firmware upload / activation state * * @ state : fw_uploader state bitmask * @ oneshot : whether the fw upload fits in a single transfer * @ num_slots : Number of FW slots available * @ cur_slot : Slot number currently active * @ next_slot : Slot number for the new firmware struct cxl_fw_state {bool oneshot;int num_slots;int cur_slot;int next_slot;/** * struct cxl_security_state - Device security state * * @ state : state of last security operation * @ enabled_cmds : All security commands enabled in the CEL * @ poll_tmo_secs : polling timeout * @ sanitize_active : sanitize completion pending * @ poll_dwork : polling work item * @ sanitize_node : sanitation sysfs file to notify struct cxl_security_state {unsigned long state;int poll_tmo_secs;bool sanitize_active;struct delayed_work poll_dwork;struct kernfs_node *sanitize_node;/* * enum cxl_devtype - delineate type - 2 from a generic type - 3 device * @ CXL_DEVTYPE_DEVMEM - Vendor specific CXL Type - 2 device implementing HDM - D or * HDM - DB , no requirement that this device implements a * mailbox , or other memory - device - standard manageability * flows . * @ CXL_DEVTYPE_CLASSMEM - Common class definition of a CXL Type - 3 device with * HDM - H and class - mandatory memory device registers enum cxl_devtype {/** * struct cxl_dpa_perf - DPA performance property entry * @ dpa_range : range for DPA address * @ coord : QoS performance data ( i . e . latency , bandwidth ) * @ cdat_coord : raw QoS performance data from CDAT * @ qos_class : QoS Class cookies struct cxl_dpa_perf {struct range dpa_range;struct access_coordinate coord[ACCESS_COORDINATE_MAX];struct access_coordinate cdat_coord[ACCESS_COORDINATE_MAX];int qos_class;/** * struct cxl_dpa_partition - DPA partition descriptor * @ res : shortcut to the partition in the DPA resource tree ( cxlds - > dpa_res ) * @ perf : performance attributes of the partition from CDAT * @ mode : operation mode for the DPA capacity , e . g . ram , pmem , dynamic . . . struct cxl_dpa_partition {struct resource res;struct cxl_dpa_perf perf;enum cxl_partition_mode mode;/** * struct cxl_dev_state - The driver device state * * cxl_dev_state represents the CXL driver / device state . It provides an * interface to mailbox commands as well as some cached data about the device . * Currently only memory devices are represented . * * @ dev : The device associated with this CXL state * @ cxlmd : The device representing the CXL . mem capabilities of @ dev * @ reg_map : component and ras register mapping parameters * @ regs : Parsed register blocks * @ cxl_dvsec : Offset to the PCIe device DVSEC * @ rcd : operating in RCD mode ( CXL 3 . 0 9 . 11 . 8 CXL Devices Attached to an RCH ) * @ media_ready : Indicate whether the device media is usable * @ dpa_res : Overall DPA resource tree for the device * @ part : DPA partition array * @ nr_partitions : Number of DPA partitions * @ serial : PCIe Device Serial Number * @ type : Generic Memory Class device or Vendor Specific Memory device * @ cxl_mbox : CXL mailbox context * @ cxlfs : CXL features context struct cxl_dev_state {struct device *dev;struct cxl_memdev *cxlmd;struct cxl_register_map reg_map;struct cxl_regs regs;int cxl_dvsec;bool rcd;bool media_ready;struct resource dpa_res;struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX];unsigned int nr_partitions;enum cxl_devtype type;struct cxl_mailbox cxl_mbox;#ifdef CONFIG_CXL_FEATURESstruct cxl_features_state *cxlfs;#endif static inline resource_size_t cxl_pmem_size(struct cxl_dev_state *cxlds)/* * Static PMEM may be at partition index 0 when there is no static RAM * capacity . for (int i = 0 ; i < cxlds->nr_partitions; i++)if (cxlds->part[i].mode == CXL_PARTMODE_PMEM)return resource_size(&cxlds->part[i].res);return 0 ;static inline struct cxl_dev_state *mbox_to_cxlds(struct cxl_mailbox *cxl_mbox)return dev_get_drvdata(cxl_mbox->host);/** * struct cxl_memdev_state - Generic Type - 3 Memory Device Class driver data * * CXL 8 . 1 . 12 . 1 PCI Header - Class Code Register Memory Device defines * common memory device functionality like the presence of a mailbox and * the functionality related to that like Identify Memory Device and Get * Partition Info * @ cxlds : Core driver state common across Type - 2 and Type - 3 devices * @ lsa_size : Size of Label Storage Area * ( CXL 2 . 0 8 . 2 . 9 . 5 . 1 . 1 Identify Memory Device ) * @ firmware_version : Firmware version for the memory device . * @ total_bytes : sum of all possible capacities * @ volatile_only_bytes : hard volatile capacity * @ persistent_only_bytes : hard persistent capacity * @ partition_align_bytes : alignment size for partition - able capacity * @ active_volatile_bytes : sum of hard + soft volatile * @ active_persistent_bytes : sum of hard + soft persistent * @ event : event log driver state * @ poison : poison driver state info * @ security : security driver state info * @ fw : firmware upload / activation state * @ mce_notifier : MCE notifier * * See CXL 3 . 0 8 . 2 . 9 . 8 . 2 Capacity Configuration and Label Storage for * details on capacity parameters . struct cxl_memdev_state {struct cxl_dev_state cxlds;char firmware_version[0 x10];struct cxl_event_state event;struct cxl_poison_state poison;struct cxl_security_state security;struct cxl_fw_state fw;struct notifier_block mce_notifier;static inline struct cxl_memdev_state *struct cxl_dev_state *cxlds)if (cxlds->type != CXL_DEVTYPE_CLASSMEM)return NULL;return container_of(cxlds, struct cxl_memdev_state, cxlds);enum cxl_opcode {0 x0000,0 x0100,0 x0101,0 x0102,0 x0103,0 x0200,0 x0201,0 x0202,0 x0300,0 x0301,0 x0400,0 x0401,0 x0402,0 x0403,0 x0405,0 x0500,0 x0501,0 x0502,0 x0600,0 x4000,0 x4100,0 x4101,0 x4102,0 x4103,0 x4200,0 x4201,0 x4202,0 x4203,0 x4204,0 x4300,0 x4301,0 x4302,0 x4303,0 x4304,0 x4305,0 x4400,0 x4401,0 x4500,0 x4501,0 x4502,0 x4503,0 x4504,0 x4505,0 x10000#define DEFINE_CXL_CEL_UUID \0 xda9c0b5, 0 xbf41, 0 x4b78, 0 x8f, 0 x79, 0 x96, 0 xb1, 0 x62, \0 x3b, 0 x3f, 0 x17)#define DEFINE_CXL_VENDOR_DEBUG_UUID \0 x5e1819d9, 0 x11a9, 0 x400c, 0 x81, 0 x1f, 0 xd6, 0 x07, 0 x19, \0 x40, 0 x3d, 0 x86)struct cxl_mbox_get_supported_logs {6 ];struct cxl_gsl_entry {struct cxl_cel_entry {struct cxl_mbox_get_log {/* See CXL 2.0 Table 175 Identify Memory Device Output Payload */ struct cxl_mbox_identify {char fw_revision[0 x10];3 ];/* * General Media Event Record UUID * CXL rev 3 . 0 Section 8 . 2 . 9 . 2 . 1 . 1 ; Table 8 - 43 #define CXL_EVENT_GEN_MEDIA_UUID \0 xfbcd0a77, 0 xc260, 0 x417f, 0 x85, 0 xa9, 0 x08, 0 x8b, 0 x16, \0 x21, 0 xeb, 0 xa6)/* * DRAM Event Record UUID * CXL rev 3 . 0 section 8 . 2 . 9 . 2 . 1 . 2 ; Table 8 - 44 #define CXL_EVENT_DRAM_UUID \0 x601dcbb3, 0 x9c06, 0 x4eab, 0 xb8, 0 xaf, 0 x4e, 0 x9b, 0 xfb, \0 x5c, 0 x96, 0 x24)/* * Memory Module Event Record UUID * CXL rev 3 . 0 section 8 . 2 . 9 . 2 . 1 . 3 ; Table 8 - 45 #define CXL_EVENT_MEM_MODULE_UUID \0 xfe927475, 0 xdd59, 0 x4339, 0 xa5, 0 x86, 0 x79, 0 xba, 0 xb1, \0 x13, 0 xb7, 0 x74)/* * Memory Sparing Event Record UUID * CXL rev 3 . 2 section 8 . 2 . 10 . 2 . 1 . 4 : Table 8 - 60 #define CXL_EVENT_MEM_SPARING_UUID \0 xe71f3a40, 0 x2d29, 0 x4092, 0 x8a, 0 x39, 0 x4d, 0 x1c, 0 x96, \0 x6c, 0 x7c, 0 x65)/* * Get Event Records output payload * CXL rev 3 . 0 section 8 . 2 . 9 . 2 . 2 ; Table 8 - 50 #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0 )#define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1 )struct cxl_get_event_payload {10 ];struct cxl_event_record_raw records[];/* * CXL rev 3 . 0 section 8 . 2 . 9 . 2 . 2 ; Table 8 - 49 enum cxl_event_log_type {0 x00,/* * Clear Event Records input payload * CXL rev 3 . 0 section 8 . 2 . 9 . 2 . 3 ; Table 8 - 51 struct cxl_mbox_clear_event_payload {/* enum cxl_event_log_type */ 3 ];#define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAXstruct cxl_mbox_get_partition_info {struct cxl_mbox_get_lsa {struct cxl_mbox_set_lsa {struct cxl_mbox_set_partition_info {#define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0 )/* Get Health Info Output Payload CXL 3.2 Spec 8.2.10.9.3.1 Table 8-148 */ struct cxl_mbox_get_health_info_out {/* Set Shutdown State Input Payload CXL 3.2 Spec 8.2.10.9.3.5 Table 8-152 */ struct cxl_mbox_set_shutdown_state_in {/* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */ struct cxl_mbox_set_timestamp_in {/* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */ struct cxl_mbox_poison_in {struct cxl_mbox_poison_out {20 ];struct cxl_poison_record {/* * Get Poison List address field encodes the starting * address of poison , and the source of the poison . #define CXL_POISON_START_MASK GENMASK_ULL(63 , 6 )#define CXL_POISON_SOURCE_MASK GENMASK(2 , 0 )/* Get Poison List record length is in units of 64 bytes */ #define CXL_POISON_LEN_MULT 64 /* Kernel defined maximum for a list of poison errors */ #define CXL_POISON_LIST_MAX 1024 /* Get Poison List: Payload out flags */ #define CXL_POISON_FLAG_MORE BIT(0 )#define CXL_POISON_FLAG_OVERFLOW BIT(1 )#define CXL_POISON_FLAG_SCANNING BIT(2 )/* Get Poison List: Poison Source */ #define CXL_POISON_SOURCE_UNKNOWN 0 #define CXL_POISON_SOURCE_EXTERNAL 1 #define CXL_POISON_SOURCE_INTERNAL 2 #define CXL_POISON_SOURCE_INJECTED 3 #define CXL_POISON_SOURCE_VENDOR 7 /* Inject & Clear Poison CXL 3.0 Spec 8.2.9.8.4.2/3 */ struct cxl_mbox_inject_poison {/* Clear Poison CXL 3.0 Spec 8.2.9.8.4.3 */ struct cxl_mbox_clear_poison {/** * struct cxl_mem_command - Driver representation of a memory device command * @ info : Command information as it exists for the UAPI * @ opcode : The actual bits used for the mailbox protocol * @ flags : Set of flags effecting driver behavior . * * * % CXL_CMD_FLAG_FORCE_ENABLE : In cases of error , commands with this flag * will be enabled by the driver regardless of what hardware may have * advertised . * * The cxl_mem_command is the driver ' s internal representation of commands that * are supported by the driver . Some of these commands may not be supported by * the hardware . The driver will use @ info to validate the fields passed in by * the user then submit the @ opcode to the hardware . * * See struct cxl_command_info . struct cxl_mem_command {struct cxl_command_info info;enum cxl_opcode opcode;#define CXL_CMD_FLAG_FORCE_ENABLE BIT(0 )#define CXL_PMEM_SEC_STATE_USER_PASS_SET 0 x01#define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0 x02#define CXL_PMEM_SEC_STATE_LOCKED 0 x04#define CXL_PMEM_SEC_STATE_FROZEN 0 x08#define CXL_PMEM_SEC_STATE_USER_PLIMIT 0 x10#define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0 x20/* set passphrase input payload */ struct cxl_set_pass {31 ];/* CXL field using NVDIMM define, same length */ /* disable passphrase input payload */ struct cxl_disable_pass {31 ];/* passphrase secure erase payload */ struct cxl_pass_erase {31 ];enum {0 ,int cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox,struct cxl_mbox_cmd *cmd);int cxl_dev_state_identify(struct cxl_memdev_state *mds);int cxl_await_media_ready(struct cxl_dev_state *cxlds);int cxl_enumerate_cmds(struct cxl_memdev_state *mds);int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info);struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev);void set_exclusive_cxl_commands(struct cxl_memdev_state *mds,unsigned long *cmds);void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds,unsigned long *cmds);void cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status);void cxl_event_trace_record(const struct cxl_memdev *cxlmd,enum cxl_event_log_type type,enum cxl_event_type event_type,const uuid_t *uuid, union cxl_event *evt);int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count);int cxl_arm_dirty_shutdown(struct cxl_memdev_state *mds);int cxl_set_timestamp(struct cxl_memdev_state *mds);int cxl_poison_state_init(struct cxl_memdev_state *mds);int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,struct cxl_region *cxlr);int cxl_trigger_poison_list(struct cxl_memdev *cxlmd);int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa);int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa);#ifdef CONFIG_CXL_EDAC_MEM_FEATURESint devm_cxl_memdev_edac_register(struct cxl_memdev *cxlmd);int devm_cxl_region_edac_register(struct cxl_region *cxlr);int cxl_store_rec_gen_media(struct cxl_memdev *cxlmd, union cxl_event *evt);int cxl_store_rec_dram(struct cxl_memdev *cxlmd, union cxl_event *evt);void devm_cxl_memdev_edac_release(struct cxl_memdev *cxlmd);#else static inline int devm_cxl_memdev_edac_register(struct cxl_memdev *cxlmd)return 0 ; }static inline int devm_cxl_region_edac_register(struct cxl_region *cxlr)return 0 ; }static inline int cxl_store_rec_gen_media(struct cxl_memdev *cxlmd,union cxl_event *evt)return 0 ; }static inline int cxl_store_rec_dram(struct cxl_memdev *cxlmd,union cxl_event *evt)return 0 ; }static inline void devm_cxl_memdev_edac_release(struct cxl_memdev *cxlmd)return ; }#endif #ifdef CONFIG_CXL_SUSPENDvoid cxl_mem_active_inc(void );void cxl_mem_active_dec(void );#else static inline void cxl_mem_active_inc(void )static inline void cxl_mem_active_dec(void )#endif int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd);/** * struct cxl_hdm - HDM Decoder registers and cached / decoded capabilities * @ regs : mapped registers , see devm_cxl_setup_hdm ( ) * @ decoder_count : number of decoders for this port * @ target_count : for switch decoders , max downstream port targets * @ interleave_mask : interleave granularity capability , see check_interleave_cap ( ) * @ iw_cap_mask : bitmask of supported interleave ways , see check_interleave_cap ( ) * @ port : mapped cxl_port , see devm_cxl_setup_hdm ( ) struct cxl_hdm {struct cxl_component_regs regs;unsigned int decoder_count;unsigned int target_count;unsigned int interleave_mask;unsigned long iw_cap_mask;struct cxl_port *port;struct seq_file;struct dentry *cxl_debugfs_create_dir(const char *dir);void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds);#endif /* __CXL_MEM_H__ */
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