Quelle dpll3xxx.c
Sprache: C
// SPDX-License-Identifier: GPL-2.0-only /* * OMAP3 / 4 - specific DPLL control functions * * Copyright ( C ) 2009 - 2010 Texas Instruments , Inc . * Copyright ( C ) 2009 - 2010 Nokia Corporation * * Written by Paul Walmsley * Testing and integration fixes by Jouni H ö gander * * 36 xx support added by Vishwanath BS , Richard Woodruff , and Nishanth * Menon * * Parts of this code are based on code written by * Richard Woodruff , Tony Lindgren , Tuukka Tikkanen , Karthik Dasu #include <linux/kernel.h>#include <linux/device.h>#include <linux/list.h>#include <linux/errno.h>#include <linux/delay.h>#include <linux/clk.h>#include <linux/io.h>#include <linux/bitops.h>#include <linux/clkdev.h>#include <linux/clk/ti.h>#include "clock.h" /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ #define DPLL_AUTOIDLE_DISABLE 0 x0#define DPLL_AUTOIDLE_LOW_POWER_STOP 0 x1#define MAX_DPLL_WAIT_TRIES 1000000 #define OMAP3XXX_EN_DPLL_LOCKED 0 x7/* Forward declarations */ static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);/* Private functions */ /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)const struct dpll_data *dd;/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)const struct dpll_data *dd;int i = 0 ;int ret = -EINVAL;const char *clk_name;while (((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask)1 );if (i == MAX_DPLL_WAIT_TRIES) {"clock: %s failed transition to '%s'\n" ,"locked" : "bypassed" );else {"clock: %s transition to '%s' in %d loops\n" ,"locked" : "bypassed" , i);0 ;return ret;/* From 3430 TRM ES2 4.7.6.2 */ static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)unsigned long fint;0 ;"clock: fint is %lu\n" , fint);if (fint >= 750000 && fint <= 1000000 )0 x3;else if (fint > 1000000 && fint <= 1250000 )0 x4;else if (fint > 1250000 && fint <= 1500000 )0 x5;else if (fint > 1500000 && fint <= 1750000 )0 x6;else if (fint > 1750000 && fint <= 2100000 )0 x7;else if (fint > 7500000 && fint <= 10000000 )0 xB;else if (fint > 10000000 && fint <= 12500000 )0 xC;else if (fint > 12500000 && fint <= 15000000 )0 xD;else if (fint > 15000000 && fint <= 17500000 )0 xE;else if (fint > 17500000 && fint <= 21000000 )0 xF;else "clock: unknown freqsel setting for %d\n" , n);return f;/** * _ omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness * @ clk : pointer to a DPLL struct clk * * Instructs a non - CORE DPLL to lock . Waits for the DPLL to report * readiness before returning . Will save and restore the DPLL ' s * autoidle state across the enable , per the CDP code . If the DPLL * locked successfully , return 0 ; if the DPLL did not lock in the time * allotted , or DPLL3 was passed in , return - EINVAL . static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)const struct dpll_data *dd;1 ;int r = 0 ;"clock: locking DPLL %s\n" , clk_hw_get_name(&clk->hw));/* Check if already locked */ if ((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) ==goto done;if (ai)1 );if (ai)return r;/** * _ omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness * @ clk : pointer to a DPLL struct clk * * Instructs a non - CORE DPLL to enter low - power bypass mode . In * bypass mode , the DPLL ' s rate is set equal to its parent clock ' s * rate . Waits for the DPLL to report readiness before returning . * Will save and restore the DPLL ' s autoidle state across the enable , * per the CDP code . If the DPLL entered bypass mode successfully , * return 0 ; if the DPLL did not enter bypass in the time allotted , or * DPLL3 was passed in , or the DPLL does not support low - power bypass , * return - EINVAL . static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)int r;if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))return -EINVAL;"clock: configuring DPLL %s for low-power bypass\n" ,0 );if (ai)return r;/** * _ omap3_noncore_dpll_stop - instruct a DPLL to stop * @ clk : pointer to a DPLL struct clk * * Instructs a non - CORE DPLL to enter low - power stop . Will save and * restore the DPLL ' s autoidle state across the stop , per the CDP * code . If DPLL3 was passed in , or the DPLL does not support * low - power stop , return - EINVAL ; otherwise , return 0 . static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))return -EINVAL;"clock: stopping DPLL %s\n" , clk_hw_get_name(&clk->hw));if (ai)return 0 ;/** * _ lookup_dco - Lookup DCO used by j - type DPLL * @ clk : pointer to a DPLL struct clk * @ dco : digital control oscillator selector * @ m : DPLL multiplier to set * @ n : DPLL divider to set * * See 36 xx TRM section 3 . 5 . 3 . 3 . 3 . 2 " Type B DPLL ( Low - Jitter ) " * * XXX This code is not needed for 3430 / AM35xx ; can it be optimized * out in non - multi - OMAP builds for those chips ? static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n)unsigned long fint, clkinp; /* watch out for overflow */ if (fint < 1000000000 )2 ;else 4 ;/** * _ lookup_sddiv - Calculate sigma delta divider for j - type DPLL * @ clk : pointer to a DPLL struct clk * @ sd_div : target sigma - delta divider * @ m : DPLL multiplier to set * @ n : DPLL divider to set * * See 36 xx TRM section 3 . 5 . 3 . 3 . 3 . 2 " Type B DPLL ( Low - Jitter ) " * * XXX This code is not needed for 3430 / AM35xx ; can it be optimized * out in non - multi - OMAP builds for those chips ? static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)unsigned long clkinp, sd; /* watch out for overflow */ int mod1, mod2;/* * target sigma - delta to near 250 MHz * sd = ceil [ ( m / ( n + 1 ) ) * ( clkinp_MHz / 250 ) ] 100000 ; /* shift from MHz to 10*Hz for 38.4 and 19.2 */ 250 * n);250 * n);10 ;10 ;if (mod1 || mod2)/** * omap3_noncore_dpll_ssc_program - set spread - spectrum clocking registers * @ clk : struct clk * of DPLL to set * * Enable the DPLL spread spectrum clocking if frequency modulation and * frequency spreading have been set , otherwise disable it . static void omap3_noncore_dpll_ssc_program(struct clk_hw_omap *clk)struct dpll_data *dd = clk->dpll_data;unsigned long ref_rate;if (dd->ssc_modfreq && dd->ssc_deltam) {if (dd->ssc_downspread)else 4 * dd->ssc_modfreq);if (dd->ssc_modfreq > (ref_rate / 70 ))"clock: SSC modulation frequency of DPLL %s greater than %ld\n" ,70 );0 ;while ((mantissa > 127 ) && (exponent < 7 )) {2 ;if (mantissa > 127 )127 ;10 ;if (dd->ssc_downspread)2 ;100 ;if (deltam_step > 0 xFFFFF)0 xFFFFF;if (deltam_step & dd->ssc_deltam_frac_mask)if ((dd->ssc_downspread &&2 * deltam_ceil)) < 20 ||2045 )) ||20 ||2045 ))"clock: SSC multiplier of DPLL %s is out of range\n" ,else {/** * omap3_noncore_dpll_program - set non - core DPLL M , N values directly * @ clk : struct clk * of DPLL to set * @ freqsel : FREQSEL value to set * * Program the DPLL with the last M , N values calculated , and wait for * the DPLL to lock . Returns - EINVAL upon error , or 0 upon success . static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)struct dpll_data *dd = clk->dpll_data;0 ;bool errata_i810;/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ /* * Set jitter correction . Jitter correction applicable for OMAP343X * only since freqsel field is no longer present on other devices . if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) {/* Set DPLL multiplier, divider */ /* Handle Duty Cycle Correction */ if (dd->dcc_mask) {if (dd->last_rounded_rate >= dd->dcc_rate)/* Enable DCC */ else /* Disable DCC */ 1 ) << __ffs(dd->div1_mask);/* Configure dco and sd_div for dplls that have these fields */ if (dd->dco_mask) {if (dd->sddiv_mask) {/* * Errata i810 - DPLL controller can get stuck while transitioning * to a power saving state . Software must ensure the DPLL can not * transition to a low power state while changing M / N values . * Easiest way to accomplish this is to prevent DPLL autoidle * before doing the M / N re - program . if (errata_i810) {if (ai) {/* OCP barrier */ /* Set 4X multiplier and low-power mode */ if (dd->m4xen_mask || dd->lpmode_mask) {if (dd->m4xen_mask) {if (dd->last_rounded_m4xen)else if (dd->lpmode_mask) {if (dd->last_rounded_lpmode)else if (dd->ssc_enable_mask)/* We let the clock framework set the other output dividers later */ /* REVISIT: Set ramp-up delay? */ if (errata_i810 && ai)return 0 ;/* Public functions */ /** * omap3_dpll_recalc - recalculate DPLL rate * @ hw : struct clk_hw containing the DPLL struct clk * @ parent_rate : clock rate of the DPLL parent * * Recalculate and propagate the DPLL rate . unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)struct clk_hw_omap *clk = to_clk_hw_omap(hw);return omap2_get_dpll_rate(clk);/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ /** * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode * @ hw : struct clk_hw containing then pointer to a DPLL struct clk * * Instructs a non - CORE DPLL to enable , e . g . , to enter bypass or lock . * The choice of modes depends on the DPLL ' s programmed rate : if it is * the same as the DPLL ' s parent clock , it will enter bypass ; * otherwise , it will enter lock . This code will wait for the DPLL to * indicate readiness before returning , unless the DPLL takes too long * to enter the target state . Intended to be used as the struct clk ' s * enable function . If DPLL3 was passed in , or the DPLL does not * support low - power stop , or if the DPLL took too long to enter * bypass or lock , return - EINVAL ; otherwise , return 0 . int omap3_noncore_dpll_enable(struct clk_hw *hw)struct clk_hw_omap *clk = to_clk_hw_omap(hw);int r;struct dpll_data *dd;struct clk_hw *parent;if (!dd)return -EINVAL;if (clk->clkdm) {if (r) {1 ,"%s: could not enable %s's clockdomain %s: %d\n" ,return r;if (clk_hw_get_rate(hw) == clk_hw_get_rate(dd->clk_bypass)) {else {return r;/** * omap3_noncore_dpll_disable - instruct a DPLL to enter low - power stop * @ hw : struct clk_hw containing then pointer to a DPLL struct clk * * Instructs a non - CORE DPLL to enter low - power stop . This function is * intended for use in struct clkops . No return value . void omap3_noncore_dpll_disable(struct clk_hw *hw)struct clk_hw_omap *clk = to_clk_hw_omap(hw);if (clk->clkdm)/* Non-CORE DPLL rate set code */ /** * omap3_noncore_dpll_determine_rate - determine rate for a DPLL * @ hw : pointer to the clock to determine rate for * @ req : target rate request * * Determines which DPLL mode to use for reaching a desired target rate . * Checks whether the DPLL shall be in bypass or locked mode , and if * locked , calculates the M , N values for the DPLL via round - rate . * Returns a 0 on success , negative error value in failure . int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,struct clk_rate_request *req)struct clk_hw_omap *clk = to_clk_hw_omap(hw);struct dpll_data *dd;if (!req->rate)return -EINVAL;if (!dd)return -EINVAL;if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&1 << DPLL_LOW_POWER_BYPASS))) {else {return 0 ;/** * omap3_noncore_dpll_set_parent - set parent for a DPLL clock * @ hw : pointer to the clock to set parent for * @ index : parent index to select * * Sets parent for a DPLL clock . This sets the DPLL into bypass or * locked mode . Returns 0 with success , negative error value otherwise . int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index)struct clk_hw_omap *clk = to_clk_hw_omap(hw);int ret;if (!hw)return -EINVAL;if (index)else return ret;/** * omap3_noncore_dpll_set_rate - set rate for a DPLL clock * @ hw : pointer to the clock to set parent for * @ rate : target rate for the clock * @ parent_rate : rate of the parent clock * * Sets rate for a DPLL clock . First checks if the clock parent is * reference clock ( in bypass mode , the rate of the clock can ' t be * changed ) and proceeds with the rate change operation . Returns 0 * with success , negative error value otherwise . int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,unsigned long parent_rate)struct clk_hw_omap *clk = to_clk_hw_omap(hw);struct dpll_data *dd;0 ;int ret;if (!hw || !rate)return -EINVAL;if (!dd)return -EINVAL;if (clk_hw_get_parent(hw) != dd->clk_ref)return -EINVAL;if (dd->last_rounded_rate == 0 )return -EINVAL;/* Freqsel is available only on OMAP343X devices */ if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) {"%s: %s: set rate: locking rate to %lu.\n" , __func__,return ret;/** * omap3_noncore_dpll_set_rate_and_parent - set rate and parent for a DPLL clock * @ hw : pointer to the clock to set rate and parent for * @ rate : target rate for the DPLL * @ parent_rate : clock rate of the DPLL parent * @ index : new parent index for the DPLL , 0 - reference , 1 - bypass * * Sets rate and parent for a DPLL clock . If new parent is the bypass * clock , only selects the parent . Otherwise proceeds with a rate * change , as this will effectively also change the parent as the * DPLL is put into locked mode . Returns 0 with success , negative error * value otherwise . int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,unsigned long rate,unsigned long parent_rate,int ret;if (!hw || !rate)return -EINVAL;/* * clk - ref at index [ 0 ] , in which case we only need to set rate , * the parent will be changed automatically with the lock sequence . * With clk - bypass case we only need to change parent . if (index)else return ret;/* DPLL autoidle read/set code */ /** * omap3_dpll_autoidle_read - read a DPLL ' s autoidle bits * @ clk : struct clk * of the DPLL to read * * Return the DPLL ' s autoidle bits , shifted down to bit 0 . Returns * - EINVAL if passed a null pointer or if the struct clk does not * appear to refer to a DPLL . static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)const struct dpll_data *dd;if (!clk || !clk->dpll_data)return -EINVAL;if (!dd->autoidle_mask)return -EINVAL;return v;/** * omap3_dpll_allow_idle - enable DPLL autoidle bits * @ clk : struct clk * of the DPLL to operate on * * Enable DPLL automatic idle control . This automatic idle mode * switching takes effect only when the DPLL is locked , at least on * OMAP3430 . The DPLL will enter low - power stop when its downstream * clocks are gated . No return value . static void omap3_dpll_allow_idle(struct clk_hw_omap *clk)const struct dpll_data *dd;if (!clk || !clk->dpll_data)return ;if (!dd->autoidle_mask)return ;/* * REVISIT : CORE DPLL can optionally enter low - power bypass * by writing 0 x5 instead of 0 x1 . Add some mechanism to * optionally enter this mode . /** * omap3_dpll_deny_idle - prevent DPLL from automatically idling * @ clk : struct clk * of the DPLL to operate on * * Disable DPLL automatic idle control . No return value . static void omap3_dpll_deny_idle(struct clk_hw_omap *clk)const struct dpll_data *dd;if (!clk || !clk->dpll_data)return ;if (!dd->autoidle_mask)return ;/* Clock control for DPLL outputs */ /* Find the parent DPLL for the given clkoutx2 clock */ static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)struct clk_hw_omap *pclk = NULL;/* Walk up the parents of clk, looking for a DPLL */ do {do {while (hw && (!omap2_clk_is_hw_omap(hw)));if (!hw)break ;while (pclk && !pclk->dpll_data);/* clk does not have a DPLL as a parent? error in the clock data */ if (!pclk) {1 );return NULL;return pclk;/** * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate * @ hw : pointer struct clk_hw * @ parent_rate : clock rate of the DPLL parent * * Using parent clock DPLL data , look up DPLL state . If locked , set our * rate to the dpll_clk * 2 ; otherwise , just use dpll_clk . unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,unsigned long parent_rate)const struct dpll_data *dd;unsigned long rate;struct clk_hw_omap *pclk = NULL;if (!parent_rate)return 0 ;if (!pclk)return 0 ;if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))else 2 ;return rate;/** * omap3_core_dpll_save_context - Save the m and n values of the divider * @ hw : pointer struct clk_hw * * Before the dpll registers are lost save the last rounded rate m and n * and the enable mask . int omap3_core_dpll_save_context(struct clk_hw *hw)struct clk_hw_omap *clk = to_clk_hw_omap(hw);struct dpll_data *dd;if (clk->context == DPLL_LOCKED) {1 ;return 0 ;/** * omap3_core_dpll_restore_context - restore the m and n values of the divider * @ hw : pointer struct clk_hw * * Restore the last rounded rate m and n * and the enable mask . void omap3_core_dpll_restore_context(struct clk_hw *hw)struct clk_hw_omap *clk = to_clk_hw_omap(hw);const struct dpll_data *dd;if (clk->context == DPLL_LOCKED) {0 x4);0 );1 ) << __ffs(dd->div1_mask);1 );else {/** * omap3_noncore_dpll_save_context - Save the m and n values of the divider * @ hw : pointer struct clk_hw * * Before the dpll registers are lost save the last rounded rate m and n * and the enable mask . int omap3_noncore_dpll_save_context(struct clk_hw *hw)struct clk_hw_omap *clk = to_clk_hw_omap(hw);struct dpll_data *dd;if (clk->context == DPLL_LOCKED) {1 ;return 0 ;/** * omap3_noncore_dpll_restore_context - restore the m and n values of the divider * @ hw : pointer struct clk_hw * * Restore the last rounded rate m and n * and the enable mask . void omap3_noncore_dpll_restore_context(struct clk_hw *hw)struct clk_hw_omap *clk = to_clk_hw_omap(hw);const struct dpll_data *dd;if (clk->context == ((ctrl & dd->enable_mask) >>1 ) {/* nothing to be done */ return ;if (clk->context == DPLL_LOCKED)0 );else /* OMAP3/4 non-CORE DPLL clkops */ const struct clk_hw_omap_ops clkhwops_omap3_dpll = {/** * omap3_dpll4_set_rate - set rate for omap3 per - dpll * @ hw : clock to change * @ rate : target rate for clock * @ parent_rate : clock rate of the DPLL parent * * Check if the current SoC supports the per - dpll reprogram operation * or not , and then do the rate change if supported . Returns - EINVAL * if not supported , 0 for success , and potential error codes from the * clock rate change . int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,unsigned long parent_rate)/* * According to the 12 - 5 CDP code from TI , " Limitation 2 . 5 " * on 3430 ES1 prevents us from changing DPLL multipliers or dividers * on DPLL4 . if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {"clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n" );return -EINVAL;return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);/** * omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per - dpll * @ hw : clock to change * @ rate : target rate for clock * @ parent_rate : rate of the parent clock * @ index : parent index , 0 - reference clock , 1 - bypass clock * * Check if the current SoC support the per - dpll reprogram operation * or not , and then do the rate + parent change if supported . Returns * - EINVAL if not supported , 0 for success , and potential error codes * from the clock rate change . int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,unsigned long parent_rate, u8 index)if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {"clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n" );return -EINVAL;return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate,/* Apply DM3730 errata sprz319 advisory 2.1. */ static bool omap3_dpll5_apply_errata(struct clk_hw *hw,unsigned long parent_rate)struct omap3_dpll5_settings {unsigned int rate, m, n;static const struct omap3_dpll5_settings precomputed[] = {/* * From DM3730 errata advisory 2 . 1 , table 35 and 36 . * The N value is increased by 1 compared to the tables as the * errata lists register values while last_rounded_field is the * real divider value . 12000000 , 80 , 0 + 1 },13000000 , 443 , 5 + 1 },19200000 , 50 , 0 + 1 },26000000 , 443 , 11 + 1 },38400000 , 25 , 0 + 1 }const struct omap3_dpll5_settings *d;struct clk_hw_omap *clk = to_clk_hw_omap(hw);struct dpll_data *dd;unsigned int i;for (i = 0 ; i < ARRAY_SIZE(precomputed); ++i) {if (parent_rate == precomputed[i].rate)break ;if (i == ARRAY_SIZE(precomputed))return false ;/* Update the M, N and rounded rate values and program the DPLL. */ 0 );return true ;/** * omap3_dpll5_set_rate - set rate for omap3 dpll5 * @ hw : clock to change * @ rate : target rate for clock * @ parent_rate : rate of the parent clock * * Set rate for the DPLL5 clock . Apply the sprz319 advisory 2 . 1 on OMAP36xx if * the DPLL is used for USB host ( detected through the requested rate ) . int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,unsigned long parent_rate)if (rate == OMAP3_DPLL5_FREQ_FOR_USBHOST * 8 ) {if (omap3_dpll5_apply_errata(hw, parent_rate))return 0 ;return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
Messung V0.5 in Prozent C=95 H=96 G=95
¤ Dauer der Verarbeitung: 0.20 Sekunden
(vorverarbeitet am 2026-09-29)
¤ *© Formatika GbR, Deutschland
2026-10-10
Neuigkeiten Aktuelles Motto des Tages letze Version des Elbe Quellennavigators
Jenseits des Üblichen ....
Besucher
Statistik #Sources=1126864 #Domains=1897691
