// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2017 Rockchip Electronics Co. Ltd. * Author: Elaine <zhangqing@rock-chips.com> #include <linux/clk-provider.h>#include <linux/io.h>#include <linux/of.h>#include <linux/of_address.h>#include <linux/syscore_ops.h>#include <dt-bindings/clock/rk3128-cru.h>#include "clk.h" #define RK3128_GRF_SOC_STATUS0 0 x14cenum rk3128_plls {static struct rockchip_pll_rate_table rk3128_pll_rates[] = {/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 1608000000 , 1 , 67 , 1 , 1 , 1 , 0 ),1584000000 , 1 , 66 , 1 , 1 , 1 , 0 ),1560000000 , 1 , 65 , 1 , 1 , 1 , 0 ),1536000000 , 1 , 64 , 1 , 1 , 1 , 0 ),1512000000 , 1 , 63 , 1 , 1 , 1 , 0 ),1488000000 , 1 , 62 , 1 , 1 , 1 , 0 ),1464000000 , 1 , 61 , 1 , 1 , 1 , 0 ),1440000000 , 1 , 60 , 1 , 1 , 1 , 0 ),1416000000 , 1 , 59 , 1 , 1 , 1 , 0 ),1392000000 , 1 , 58 , 1 , 1 , 1 , 0 ),1368000000 , 1 , 57 , 1 , 1 , 1 , 0 ),1344000000 , 1 , 56 , 1 , 1 , 1 , 0 ),1320000000 , 1 , 55 , 1 , 1 , 1 , 0 ),1296000000 , 1 , 54 , 1 , 1 , 1 , 0 ),1272000000 , 1 , 53 , 1 , 1 , 1 , 0 ),1248000000 , 1 , 52 , 1 , 1 , 1 , 0 ),1200000000 , 1 , 50 , 1 , 1 , 1 , 0 ),1188000000 , 2 , 99 , 1 , 1 , 1 , 0 ),1104000000 , 1 , 46 , 1 , 1 , 1 , 0 ),1100000000 , 12 , 550 , 1 , 1 , 1 , 0 ),1008000000 , 1 , 84 , 2 , 1 , 1 , 0 ),1000000000 , 6 , 500 , 2 , 1 , 1 , 0 ),984000000 , 1 , 82 , 2 , 1 , 1 , 0 ),960000000 , 1 , 80 , 2 , 1 , 1 , 0 ),936000000 , 1 , 78 , 2 , 1 , 1 , 0 ),912000000 , 1 , 76 , 2 , 1 , 1 , 0 ),900000000 , 4 , 300 , 2 , 1 , 1 , 0 ),888000000 , 1 , 74 , 2 , 1 , 1 , 0 ),864000000 , 1 , 72 , 2 , 1 , 1 , 0 ),840000000 , 1 , 70 , 2 , 1 , 1 , 0 ),816000000 , 1 , 68 , 2 , 1 , 1 , 0 ),800000000 , 6 , 400 , 2 , 1 , 1 , 0 ),700000000 , 6 , 350 , 2 , 1 , 1 , 0 ),696000000 , 1 , 58 , 2 , 1 , 1 , 0 ),600000000 , 1 , 75 , 3 , 1 , 1 , 0 ),594000000 , 2 , 99 , 2 , 1 , 1 , 0 ),504000000 , 1 , 63 , 3 , 1 , 1 , 0 ),500000000 , 6 , 250 , 2 , 1 , 1 , 0 ),408000000 , 1 , 68 , 2 , 2 , 1 , 0 ),312000000 , 1 , 52 , 2 , 2 , 1 , 0 ),216000000 , 1 , 72 , 4 , 2 , 1 , 0 ),96000000 , 1 , 64 , 4 , 4 , 1 , 0 ),/* sentinel */ }, #define RK3128_DIV_CPU_MASK 0 x1f#define RK3128_DIV_CPU_SHIFT 8 #define RK3128_DIV_PERI_MASK 0 xf#define RK3128_DIV_PERI_SHIFT 0 #define RK3128_DIV_ACLK_MASK 0 x7#define RK3128_DIV_ACLK_SHIFT 4 #define RK3128_DIV_HCLK_MASK 0 x3#define RK3128_DIV_HCLK_SHIFT 8 #define RK3128_DIV_PCLK_MASK 0 x7#define RK3128_DIV_PCLK_SHIFT 12 #define RK3128_CLKSEL1(_core_aclk_div, _pclk_dbg_div) \1 ), \#define RK3128_CPUCLK_RATE(_prate, _core_aclk_div, _pclk_dbg_div) \static struct rockchip_cpuclk_rate_table rk3128_cpuclk_rates[] __initdata = {1800000000 , 1 , 7 ),1704000000 , 1 , 7 ),1608000000 , 1 , 7 ),1512000000 , 1 , 7 ),1488000000 , 1 , 5 ),1416000000 , 1 , 5 ),1392000000 , 1 , 5 ),1296000000 , 1 , 5 ),1200000000 , 1 , 5 ),1104000000 , 1 , 5 ),1008000000 , 1 , 5 ),912000000 , 1 , 5 ),816000000 , 1 , 3 ),696000000 , 1 , 3 ),600000000 , 1 , 3 ),408000000 , 1 , 1 ),312000000 , 1 , 1 ),216000000 , 1 , 1 ),96000000 , 1 , 1 ),static const struct rockchip_cpuclk_reg_data rk3128_cpuclk_data = {0 ] = RK2928_CLKSEL_CON(0 ),0 ] = 0 ,0 ] = 0 x1f,1 ,1 ,0 ,7 ,0 x1,"clk_24m" , "xin24m" };"dpll_ddr" , "gpll_div2_ddr" };"apll_core" , "gpll_div2_core" };"usb480m_phy" , "xin24m" };"cpll" , "gpll" , "gpll_div2" , "gpll_div3" };"cpll" , "gpll" , "gpll_div2" , "gpll_div3" , "usb480m" };"cpll" , "gpll" , "gpll_div2" , "usb480m" };"cpll" , "gpll" , "gpll_div2" };"gpll" , "cpll" , "gpll_div2" , "gpll_div3" };"cpll" , "gpll" , "gpll_div2" , "xin24m" };"clk_cif_src" , "xin24m" };"cpll" , "gpll" , "gpll_div2" , "gpll_div3" };"i2s0_src" , "i2s0_frac" , "ext_i2s" , "xin12m" };"i2s1_src" , "i2s1_frac" , "ext_i2s" , "xin12m" };"i2s1_pre" , "xin12m" };"sclk_spdif_src" , "spdif_frac" , "xin12m" };"uart0_src" , "uart0_frac" , "xin24m" };"uart1_src" , "uart1_frac" , "xin24m" };"uart2_src" , "uart2_frac" , "xin24m" };"sclk_gmac_src" , "gmac_clkin" };"cpll" , "gpll" , "gpll_div2" , "xin24m" };static struct rockchip_pll_clock rk3128_pll_clks[] __initdata = {"apll" , mux_pll_p, 0 , RK2928_PLL_CON(0 ),0 , 1 , 0 , rk3128_pll_rates),"dpll" , mux_pll_p, 0 , RK2928_PLL_CON(4 ),4 , 0 , 0 , NULL),"cpll" , mux_pll_p, 0 , RK2928_PLL_CON(8 ),8 , 2 , 0 , rk3128_pll_rates),"gpll" , mux_pll_p, 0 , RK2928_PLL_CON(12 ),12 , 3 , ROCKCHIP_PLL_SYNC_RATE, rk3128_pll_rates),#define MFLAGS CLK_MUX_HIWORD_MASK#define DFLAGS CLK_DIVIDER_HIWORD_MASK#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)static struct rockchip_clk_branch rk3128_i2s0_fracmux __initdata =0 , "i2s0_pre" , mux_i2s0_p, CLK_SET_RATE_PARENT,9 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3128_i2s1_fracmux __initdata =0 , "i2s1_pre" , mux_i2s1_pre_p, CLK_SET_RATE_PARENT,3 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3128_spdif_fracmux __initdata ="sclk_spdif" , mux_sclk_spdif_p, CLK_SET_RATE_PARENT,6 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3128_uart0_fracmux __initdata ="sclk_uart0" , mux_uart0_p, CLK_SET_RATE_PARENT,13 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3128_uart1_fracmux __initdata ="sclk_uart1" , mux_uart1_p, CLK_SET_RATE_PARENT,14 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3128_uart2_fracmux __initdata ="sclk_uart2" , mux_uart2_p, CLK_SET_RATE_PARENT,15 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch common_clk_branches[] __initdata = {/* * Clock-Architecture Diagram 1 "gpll_div2" , "gpll" , 0 , 1 , 2 ),"gpll_div3" , "gpll" , 0 , 1 , 3 ),0 , "clk_24m" , "xin24m" , CLK_IGNORE_UNUSED,4 ), 8 , 5 , DFLAGS),/* PD_DDR */ 0 , "dpll_ddr" , "dpll" , CLK_IGNORE_UNUSED,0 ), 2 , GFLAGS),0 , "gpll_div2_ddr" , "gpll_div2" , CLK_IGNORE_UNUSED,0 ), 2 , GFLAGS),0 , "ddrphy2x" , mux_ddrphy_p, CLK_IGNORE_UNUSED,26 ), 8 , 2 , MFLAGS, 0 , 2 , DFLAGS | CLK_DIVIDER_POWER_OF_TWO),"clk_ddrc" , "ddrphy2x" , 0 , 1 , 2 ),0 , "clk_ddrphy" , "ddrphy2x" , 0 , 1 , 2 ),/* PD_CORE */ 0 , "apll_core" , "apll" , CLK_IGNORE_UNUSED,0 ), 6 , GFLAGS),0 , "gpll_div2_core" , "gpll_div2" , CLK_IGNORE_UNUSED,0 ), 6 , GFLAGS),0 , "pclk_dbg" , "armclk" , CLK_IGNORE_UNUSED,1 ), 0 , 4 , DFLAGS | CLK_DIVIDER_READ_ONLY,0 ), 0 , GFLAGS),0 , "armcore" , "armclk" , CLK_IGNORE_UNUSED,1 ), 4 , 3 , DFLAGS | CLK_DIVIDER_READ_ONLY,0 ), 7 , GFLAGS),/* PD_MISC */ "usb480m" , mux_usb480m_p, CLK_SET_RATE_PARENT,15 , 1 , MFLAGS),/* PD_CPU */ 0 , "aclk_cpu_src" , mux_aclk_cpu_src_p, 0 ,0 ), 13 , 2 , MFLAGS, 8 , 5 , DFLAGS,0 ), 1 , GFLAGS),"aclk_cpu" , "aclk_cpu_src" , 0 ,0 ), 3 , GFLAGS),"hclk_cpu" , "aclk_cpu_src" , 0 ,1 ), 8 , 2 , DFLAGS,0 ), 4 , GFLAGS),"pclk_cpu" , "aclk_cpu_src" , 0 ,1 ), 12 , 2 , DFLAGS,0 ), 5 , GFLAGS),"clk_crypto" , "aclk_cpu_src" , 0 ,24 ), 0 , 2 , DFLAGS,0 ), 12 , GFLAGS),/* PD_VIDEO */ "aclk_vepu" , mux_pll_src_5plls_p, 0 ,32 ), 5 , 3 , MFLAGS, 0 , 5 , DFLAGS,3 ), 9 , GFLAGS),"hclk_vepu" , "aclk_vepu" , 0 , 1 , 4 ),"aclk_vdpu" , mux_pll_src_5plls_p, 0 ,32 ), 13 , 3 , MFLAGS, 8 , 5 , DFLAGS,3 ), 11 , GFLAGS),"hclk_vdpu" , "aclk_vdpu" , 0 , 1 , 4 ,3 ), 12 , GFLAGS),"sclk_hevc_core" , mux_pll_src_5plls_p, 0 ,34 ), 13 , 3 , MFLAGS, 8 , 5 , DFLAGS,3 ), 10 , GFLAGS),/* PD_VIO */ "aclk_vio0" , mux_pll_src_5plls_p, 0 ,31 ), 5 , 3 , MFLAGS, 0 , 5 , DFLAGS,3 ), 0 , GFLAGS),"aclk_vio1" , mux_pll_src_5plls_p, 0 ,31 ), 13 , 3 , MFLAGS, 8 , 5 , DFLAGS,1 ), 4 , GFLAGS),"hclk_vio" , mux_pll_src_4plls_p, 0 ,30 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,0 ), 11 , GFLAGS),/* PD_PERI */ 0 , "clk_peri_src" , mux_clk_peri_src_p, 0 ,10 ), 14 , 2 , MFLAGS, 0 , 5 , DFLAGS,2 ), 0 , GFLAGS),"pclk_peri" , "clk_peri_src" , 0 ,10 ), 12 , 2 , DFLAGS | CLK_DIVIDER_POWER_OF_TWO,2 ), 3 , GFLAGS),"hclk_peri" , "clk_peri_src" , 0 ,10 ), 8 , 2 , DFLAGS | CLK_DIVIDER_POWER_OF_TWO,2 ), 2 , GFLAGS),"aclk_peri" , "clk_peri_src" , 0 ,2 ), 1 , GFLAGS),"sclk_timer0" , "xin24m" , 0 ,10 ), 3 , GFLAGS),"sclk_timer1" , "xin24m" , 0 ,10 ), 4 , GFLAGS),"sclk_timer2" , "xin24m" , 0 ,10 ), 5 , GFLAGS),"sclk_timer3" , "xin24m" , 0 ,10 ), 6 , GFLAGS),"sclk_timer4" , "xin24m" , 0 ,10 ), 7 , GFLAGS),"sclk_timer5" , "xin24m" , 0 ,10 ), 8 , GFLAGS),"clk_pvtm_core" , "xin24m" , 0 ,10 ), 0 , GFLAGS),"clk_pvtm_gpu" , "xin24m" , 0 ,10 ), 1 , GFLAGS),"clk_pvtm_func" , "xin24m" , 0 ,10 ), 2 , GFLAGS),"clk_mipi_24m" , "xin24m" , CLK_IGNORE_UNUSED,2 ), 15 , GFLAGS),"sclk_sdmmc" , mux_mmc_src_p, 0 ,11 ), 6 , 2 , MFLAGS, 0 , 6 , DFLAGS,2 ), 11 , GFLAGS),"sclk_sdio" , mux_mmc_src_p, 0 ,12 ), 6 , 2 , MFLAGS, 0 , 6 , DFLAGS,2 ), 13 , GFLAGS),"sclk_emmc" , mux_mmc_src_p, 0 ,12 ), 14 , 2 , MFLAGS, 8 , 6 , DFLAGS,2 ), 14 , GFLAGS),"clk_pvtm" , "clk_pvtm_func" , 0 ,2 ), 0 , 7 , DFLAGS),/* * Clock-Architecture Diagram 2 "dclk_vop" , mux_sclk_vop_src_p, 0 ,27 ), 0 , 2 , MFLAGS, 8 , 8 , DFLAGS,3 ), 1 , GFLAGS),"sclk_vop" , mux_sclk_vop_src_p, 0 ,28 ), 0 , 2 , MFLAGS, 8 , 8 , DFLAGS,3 ), 2 , GFLAGS),"dclk_ebc" , mux_pll_src_3plls_p, 0 ,23 ), 0 , 2 , MFLAGS, 8 , 8 , DFLAGS,3 ), 4 , GFLAGS),0 , "xin12m" , "xin24m" , 0 , 1 , 2 ),"sclk_cif_src" , mux_pll_src_4plls_p, 0 ,29 ), 0 , 2 , MFLAGS,3 ), 7 , GFLAGS),"sclk_cif_out_src" , mux_clk_cif_out_src_p, 0 ,13 ), 14 , 2 , MFLAGS),"sclk_cif_out" , "sclk_cif_out_src" , 0 ,29 ), 2 , 5 , DFLAGS),0 , "i2s0_src" , mux_pll_src_3plls_p, 0 ,9 ), 14 , 2 , MFLAGS, 0 , 7 , DFLAGS,4 ), 4 , GFLAGS),0 , "i2s0_frac" , "i2s0_src" , CLK_SET_RATE_PARENT,8 ), 0 ,4 ), 5 , GFLAGS,"sclk_i2s0" , "i2s0_pre" , CLK_SET_RATE_PARENT,4 ), 6 , GFLAGS),0 , "i2s1_src" , mux_pll_src_3plls_p, 0 ,3 ), 14 , 2 , MFLAGS, 0 , 7 , DFLAGS,0 ), 9 , GFLAGS),0 , "i2s1_frac" , "i2s1_src" , CLK_SET_RATE_PARENT,7 ), 0 ,0 ), 10 , GFLAGS,"sclk_i2s1" , "i2s1_pre" , CLK_SET_RATE_PARENT,0 ), 14 , GFLAGS),"i2s_out" , mux_i2s_out_p, 0 ,3 ), 12 , 1 , MFLAGS,0 ), 13 , GFLAGS),0 , "sclk_spdif_src" , mux_pll_src_3plls_p, 0 ,6 ), 14 , 2 , MFLAGS, 0 , 7 , DFLAGS,2 ), 10 , GFLAGS),0 , "spdif_frac" , "sclk_spdif_src" , CLK_SET_RATE_PARENT,20 ), 0 ,2 ), 12 , GFLAGS,0 , "jtag" , "ext_jtag" , CLK_IGNORE_UNUSED,1 ), 3 , GFLAGS),"sclk_otgphy0" , "xin12m" , 0 ,1 ), 5 , GFLAGS),"sclk_otgphy1" , "xin12m" , 0 ,1 ), 6 , GFLAGS),"sclk_saradc" , "xin24m" , 0 ,24 ), 8 , 8 , DFLAGS,2 ), 8 , GFLAGS),"aclk_gpu" , mux_pll_src_5plls_p, 0 ,34 ), 5 , 3 , MFLAGS, 0 , 5 , DFLAGS,3 ), 13 , GFLAGS),"sclk_spi0" , mux_pll_src_3plls_p, 0 ,25 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,2 ), 9 , GFLAGS),/* PD_UART */ 0 , "uart0_src" , mux_pll_src_4plls_p, 0 ,13 ), 12 , 2 , MFLAGS, 0 , 7 , DFLAGS,1 ), 8 , GFLAGS),0 , "uart12_src" , mux_pll_src_4plls_p, 0 ,13 ), 14 , 2 , MFLAGS),0 , "uart1_src" , "uart12_src" , 0 ,14 ), 0 , 7 , DFLAGS,1 ), 10 , GFLAGS),0 , "uart2_src" , "uart12_src" , 0 ,15 ), 0 , 7 , DFLAGS,1 ), 13 , GFLAGS),0 , "uart0_frac" , "uart0_src" , CLK_SET_RATE_PARENT,17 ), 0 ,1 ), 9 , GFLAGS,0 , "uart1_frac" , "uart1_src" , CLK_SET_RATE_PARENT,18 ), 0 ,1 ), 11 , GFLAGS,0 , "uart2_frac" , "uart2_src" , CLK_SET_RATE_PARENT,19 ), 0 ,1 ), 13 , GFLAGS,"sclk_gmac_src" , mux_pll_src_3plls_p, 0 ,5 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,1 ), 7 , GFLAGS),"sclk_gmac" , mux_sclk_gmac_p, 0 ,5 ), 15 , 1 , MFLAGS),"sclk_mac_refout" , "sclk_gmac" , 0 ,2 ), 5 , GFLAGS),"sclk_mac_ref" , "sclk_gmac" , 0 ,2 ), 4 , GFLAGS),"sclk_mac_rx" , "sclk_gmac" , 0 ,2 ), 6 , GFLAGS),"sclk_mac_tx" , "sclk_gmac" , 0 ,2 ), 7 , GFLAGS),"sclk_tsp" , mux_pll_src_3plls_p, 0 ,4 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,1 ), 14 , GFLAGS),"sclk_nandc" , mux_pll_src_3plls_p, 0 ,2 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,10 ), 15 , GFLAGS),"pclk_pmu_pre" , "cpll" , 0 ,29 ), 8 , 6 , DFLAGS,1 ), 0 , GFLAGS),/* * Clock-Architecture Diagram 3 /* PD_VOP */ "aclk_lcdc0" , "aclk_vio0" , 0 , RK2928_CLKGATE_CON(6 ), 0 , GFLAGS),"aclk_cif" , "aclk_vio0" , 0 , RK2928_CLKGATE_CON(6 ), 5 , GFLAGS),"aclk_rga" , "aclk_vio0" , 0 , RK2928_CLKGATE_CON(6 ), 11 , GFLAGS),0 , "aclk_vio0_niu" , "aclk_vio0" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6 ), 13 , GFLAGS),"aclk_iep" , "aclk_vio1" , 0 , RK2928_CLKGATE_CON(9 ), 8 , GFLAGS),0 , "aclk_vio1_niu" , "aclk_vio1" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9 ), 10 , GFLAGS),"hclk_vio_h2p" , "hclk_vio" , 0 , RK2928_CLKGATE_CON(9 ), 5 , GFLAGS),"pclk_mipi" , "hclk_vio" , 0 , RK2928_CLKGATE_CON(9 ), 6 , GFLAGS),"hclk_rga" , "hclk_vio" , 0 , RK2928_CLKGATE_CON(6 ), 10 , GFLAGS),"hclk_lcdc0" , "hclk_vio" , 0 , RK2928_CLKGATE_CON(6 ), 1 , GFLAGS),"hclk_iep" , "hclk_vio" , 0 , RK2928_CLKGATE_CON(9 ), 7 , GFLAGS),0 , "hclk_vio_niu" , "hclk_vio" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6 ), 12 , GFLAGS),"hclk_cif" , "hclk_vio" , 0 , RK2928_CLKGATE_CON(6 ), 4 , GFLAGS),"hclk_ebc" , "hclk_vio" , 0 , RK2928_CLKGATE_CON(9 ), 9 , GFLAGS),/* PD_PERI */ 0 , "aclk_peri_axi" , "aclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4 ), 3 , GFLAGS),"aclk_gmac" , "aclk_peri" , 0 , RK2928_CLKGATE_CON(10 ), 10 , GFLAGS),"aclk_dmac" , "aclk_peri" , 0 , RK2928_CLKGATE_CON(5 ), 1 , GFLAGS),0 , "aclk_peri_niu" , "aclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9 ), 15 , GFLAGS),0 , "aclk_cpu_to_peri" , "aclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4 ), 2 , GFLAGS),"hclk_i2s_8ch" , "hclk_peri" , 0 , RK2928_CLKGATE_CON(7 ), 4 , GFLAGS),0 , "hclk_peri_matrix" , "hclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4 ), 0 , GFLAGS),"hclk_i2s_2ch" , "hclk_peri" , 0 , RK2928_CLKGATE_CON(7 ), 2 , GFLAGS),0 , "hclk_usb_peri" , "hclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9 ), 13 , GFLAGS),"hclk_host2" , "hclk_peri" , 0 , RK2928_CLKGATE_CON(7 ), 3 , GFLAGS),"hclk_otg" , "hclk_peri" , 0 , RK2928_CLKGATE_CON(5 ), 13 , GFLAGS),0 , "hclk_peri_ahb" , "hclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9 ), 14 , GFLAGS),"hclk_spdif" , "hclk_peri" , 0 , RK2928_CLKGATE_CON(10 ), 9 , GFLAGS),"hclk_tsp" , "hclk_peri" , 0 , RK2928_CLKGATE_CON(10 ), 12 , GFLAGS),"hclk_sdmmc" , "hclk_peri" , 0 , RK2928_CLKGATE_CON(5 ), 10 , GFLAGS),"hclk_sdio" , "hclk_peri" , 0 , RK2928_CLKGATE_CON(5 ), 11 , GFLAGS),"hclk_emmc" , "hclk_peri" , 0 , RK2928_CLKGATE_CON(7 ), 0 , GFLAGS),0 , "hclk_emmc_peri" , "hclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3 ), 6 , GFLAGS),"hclk_nandc" , "hclk_peri" , 0 , RK2928_CLKGATE_CON(5 ), 9 , GFLAGS),"hclk_usbhost" , "hclk_peri" , 0 , RK2928_CLKGATE_CON(10 ), 14 , GFLAGS),"pclk_sim_card" , "pclk_peri" , 0 , RK2928_CLKGATE_CON(9 ), 12 , GFLAGS),"pclk_gmac" , "pclk_peri" , 0 , RK2928_CLKGATE_CON(10 ), 11 , GFLAGS),0 , "pclk_peri_axi" , "pclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4 ), 1 , GFLAGS),"pclk_spi0" , "pclk_peri" , 0 , RK2928_CLKGATE_CON(7 ), 12 , GFLAGS),"pclk_uart0" , "pclk_peri" , 0 , RK2928_CLKGATE_CON(8 ), 0 , GFLAGS),"pclk_uart1" , "pclk_peri" , 0 , RK2928_CLKGATE_CON(8 ), 1 , GFLAGS),"pclk_uart2" , "pclk_peri" , 0 , RK2928_CLKGATE_CON(8 ), 2 , GFLAGS),"pclk_pwm" , "pclk_peri" , 0 , RK2928_CLKGATE_CON(7 ), 10 , GFLAGS),"pclk_wdt" , "pclk_peri" , 0 , RK2928_CLKGATE_CON(7 ), 15 , GFLAGS),"pclk_i2c0" , "pclk_peri" , 0 , RK2928_CLKGATE_CON(8 ), 4 , GFLAGS),"pclk_i2c1" , "pclk_peri" , 0 , RK2928_CLKGATE_CON(8 ), 5 , GFLAGS),"pclk_i2c2" , "pclk_peri" , 0 , RK2928_CLKGATE_CON(8 ), 6 , GFLAGS),"pclk_i2c3" , "pclk_peri" , 0 , RK2928_CLKGATE_CON(8 ), 7 , GFLAGS),"pclk_saradc" , "pclk_peri" , 0 , RK2928_CLKGATE_CON(7 ), 14 , GFLAGS),"pclk_efuse" , "pclk_peri" , 0 , RK2928_CLKGATE_CON(5 ), 2 , GFLAGS),"pclk_timer" , "pclk_peri" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7 ), 7 , GFLAGS),"pclk_gpio0" , "pclk_peri" , 0 , RK2928_CLKGATE_CON(8 ), 9 , GFLAGS),"pclk_gpio1" , "pclk_peri" , 0 , RK2928_CLKGATE_CON(8 ), 10 , GFLAGS),"pclk_gpio2" , "pclk_peri" , 0 , RK2928_CLKGATE_CON(8 ), 11 , GFLAGS),"pclk_gpio3" , "pclk_peri" , 0 , RK2928_CLKGATE_CON(8 ), 12 , GFLAGS),/* PD_BUS */ 0 , "aclk_initmem" , "aclk_cpu" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4 ), 12 , GFLAGS),0 , "aclk_strc_sys" , "aclk_cpu" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4 ), 10 , GFLAGS),0 , "hclk_rom" , "hclk_cpu" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5 ), 6 , GFLAGS),"hclk_crypto" , "hclk_cpu" , 0 , RK2928_CLKGATE_CON(3 ), 5 , GFLAGS),"pclk_acodec" , "pclk_cpu" , 0 , RK2928_CLKGATE_CON(5 ), 14 , GFLAGS),0 , "pclk_ddrupctl" , "pclk_cpu" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5 ), 7 , GFLAGS),0 , "pclk_grf" , "pclk_cpu" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5 ), 4 , GFLAGS),"pclk_mipiphy" , "pclk_cpu" , 0 , RK2928_CLKGATE_CON(5 ), 0 , GFLAGS),0 , "pclk_pmu" , "pclk_pmu_pre" , 0 , RK2928_CLKGATE_CON(9 ), 2 , GFLAGS),0 , "pclk_pmu_niu" , "pclk_pmu_pre" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9 ), 3 , GFLAGS),/* PD_MMC */ "sdmmc_drv" , "sclk_sdmmc" , RK3228_SDMMC_CON0, 1 ),"sdmmc_sample" , "sclk_sdmmc" , RK3228_SDMMC_CON1, 0 ),"sdio_drv" , "sclk_sdio" , RK3228_SDIO_CON0, 1 ),"sdio_sample" , "sclk_sdio" , RK3228_SDIO_CON1, 0 ),"emmc_drv" , "sclk_emmc" , RK3228_EMMC_CON0, 1 ),"emmc_sample" , "sclk_emmc" , RK3228_EMMC_CON1, 0 ),static struct rockchip_clk_branch rk3126_clk_branches[] __initdata = {0 , "pclk_stimer" , "pclk_cpu" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3 ), 15 , GFLAGS),0 , "pclk_s_efuse" , "pclk_cpu" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3 ), 14 , GFLAGS),0 , "pclk_sgrf" , "pclk_cpu" , CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3 ), 8 , GFLAGS),static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {"sclk_sfc" , mux_sclk_sfc_src_p, 0 ,11 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,3 ), 15 , GFLAGS),"hclk_sfc" , "hclk_peri" , 0 , RK2928_CLKGATE_CON(7 ), 1 , GFLAGS),"hclk_gps" , "aclk_peri" , 0 , RK2928_CLKGATE_CON(3 ), 14 , GFLAGS),"pclk_hdmi" , "pclk_cpu" , 0 , RK2928_CLKGATE_CON(3 ), 8 , GFLAGS),static const char *const rk3128_critical_clocks[] __initconst = {"aclk_cpu" ,"hclk_cpu" ,"pclk_cpu" ,"aclk_peri" ,"hclk_peri" ,"hclk_vio_h2p" ,"pclk_peri" ,"pclk_pmu" ,"sclk_timer5" ,static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np,unsigned long soc_nr_clks)struct rockchip_clk_provider *ctx;unsigned long common_nr_clks;void __iomem *reg_base;1 ;0 );if (!reg_base) {"%s: could not map cru region\n" , __func__);return ERR_PTR(-ENOMEM);if (IS_ERR(ctx)) {"%s: rockchip clk init failed\n" , __func__);return ERR_PTR(-ENOMEM);"armclk" ,9 , reg_base + RK2928_SOFTRST_CON(0 ),return ctx;static void __init rk3126_clk_init(struct device_node *np)struct rockchip_clk_provider *ctx;unsigned long soc_nr_clks;1 ;if (IS_ERR(ctx))return ;"rockchip,rk3126-cru" , rk3126_clk_init);static void __init rk3128_clk_init(struct device_node *np)struct rockchip_clk_provider *ctx;unsigned long soc_nr_clks;1 ;if (IS_ERR(ctx))return ;"rockchip,rk3128-cru" , rk3128_clk_init);
Messung V0.5 in Prozent C=97 H=94 G=95
¤ Dauer der Verarbeitung: 0.16 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
