// SPDX-License-Identifier: GPL-2.0 /* * r8a7791 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2015-2017 Glider bvba * * Based on clk-rcar-gen2.c * * Copyright (C) 2013 Ideas On Board SPRL #include <linux/device.h>#include <linux/init.h>#include <linux/kernel.h>#include <linux/of.h>#include <linux/soc/renesas/rcar-rst.h>#include <dt-bindings/clock/r8a7791-cpg-mssr.h>#include "renesas-cpg-mssr.h" #include "rcar-gen2-cpg.h" enum clk_ids {/* Core Clock Outputs exported to DT */ /* External Input Clocks */ /* Internal Core Clocks */ /* Module Clocks */ static struct cpg_core_clk r8a7791_core_clks[] __initdata = {/* External Clock Inputs */ "extal" , CLK_EXTAL),"usb_extal" , CLK_USB_EXTAL),/* Internal Core Clocks */ ".main" , CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),".pll0" , CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),".pll1" , CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),".pll3" , CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),".pll1_div2" , CLK_PLL1_DIV2, CLK_PLL1, 2, 1),/* Core Clock Outputs */ "z" , R8A7791_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),"adsp" , R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),"sdh" , R8A7791_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),"sd0" , R8A7791_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),"qspi" , R8A7791_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),"rcan" , R8A7791_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),"zg" , R8A7791_CLK_ZG, CLK_PLL1, 3, 1),"zx" , R8A7791_CLK_ZX, CLK_PLL1, 3, 1),"zs" , R8A7791_CLK_ZS, CLK_PLL1, 6, 1),"hp" , R8A7791_CLK_HP, CLK_PLL1, 12, 1),"i" , R8A7791_CLK_I, CLK_PLL1, 2, 1),"b" , R8A7791_CLK_B, CLK_PLL1, 12, 1),"lb" , R8A7791_CLK_LB, CLK_PLL1, 24, 1),"p" , R8A7791_CLK_P, CLK_PLL1, 24, 1),"cl" , R8A7791_CLK_CL, CLK_PLL1, 48, 1),"m2" , R8A7791_CLK_M2, CLK_PLL1, 8, 1),"zb3" , R8A7791_CLK_ZB3, CLK_PLL3, 4, 1),"zb3d2" , R8A7791_CLK_ZB3D2, CLK_PLL3, 8, 1),"ddr" , R8A7791_CLK_DDR, CLK_PLL3, 8, 1),"mp" , R8A7791_CLK_MP, CLK_PLL1_DIV2, 15, 1),"cp" , R8A7791_CLK_CP, CLK_EXTAL, 2, 1),"r" , R8A7791_CLK_R, CLK_PLL1, 49152, 1),"osc" , R8A7791_CLK_OSC, CLK_PLL1, 12288, 1),"sd2" , R8A7791_CLK_SD2, CLK_PLL1_DIV2, 0x078),"sd3" , R8A7791_CLK_SD3, CLK_PLL1_DIV2, 0x26c),"mmc0" , R8A7791_CLK_MMC0, CLK_PLL1_DIV2, 0x240),"ssp" , R8A7791_CLK_SSP, CLK_PLL1_DIV2, 0x248),"ssprs" , R8A7791_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),static const struct mssr_mod_clk r8a7791_mod_clks[] __initconst = {"msiof0" , 0, R8A7791_CLK_MP),"vcp0" , 101, R8A7791_CLK_ZS),"vpc0" , 103, R8A7791_CLK_ZS),"jpu" , 106, R8A7791_CLK_M2),"ssp1" , 109, R8A7791_CLK_ZS),"tmu1" , 111, R8A7791_CLK_P),"3dg" , 112, R8A7791_CLK_ZG),"2d-dmac" , 115, R8A7791_CLK_ZS),"fdp1-1" , 118, R8A7791_CLK_ZS),"fdp1-0" , 119, R8A7791_CLK_ZS),"tmu3" , 121, R8A7791_CLK_P),"tmu2" , 122, R8A7791_CLK_P),"cmt0" , 124, R8A7791_CLK_R),"tmu0" , 125, R8A7791_CLK_CP),"vsp1du1" , 127, R8A7791_CLK_ZS),"vsp1du0" , 128, R8A7791_CLK_ZS),"vsps" , 131, R8A7791_CLK_ZS),"scifa2" , 202, R8A7791_CLK_MP),"scifa1" , 203, R8A7791_CLK_MP),"scifa0" , 204, R8A7791_CLK_MP),"msiof2" , 205, R8A7791_CLK_MP),"scifb0" , 206, R8A7791_CLK_MP),"scifb1" , 207, R8A7791_CLK_MP),"msiof1" , 208, R8A7791_CLK_MP),"scifb2" , 216, R8A7791_CLK_MP),"sys-dmac1" , 218, R8A7791_CLK_ZS),"sys-dmac0" , 219, R8A7791_CLK_ZS),"tpu0" , 304, R8A7791_CLK_CP),"sdhi3" , 311, R8A7791_CLK_SD3),"sdhi2" , 312, R8A7791_CLK_SD2),"sdhi0" , 314, R8A7791_CLK_SD0),"mmcif0" , 315, R8A7791_CLK_MMC0),"iic0" , 318, R8A7791_CLK_HP),"pciec" , 319, R8A7791_CLK_MP),"iic1" , 323, R8A7791_CLK_HP),"usb3.0" , 328, R8A7791_CLK_MP),"cmt1" , 329, R8A7791_CLK_R),"usbhs-dmac0" , 330, R8A7791_CLK_HP),"usbhs-dmac1" , 331, R8A7791_CLK_HP),"rwdt" , 402, R8A7791_CLK_R),"irqc" , 407, R8A7791_CLK_CP),"intc-sys" , 408, R8A7791_CLK_ZS),"audio-dmac1" , 501, R8A7791_CLK_HP),"audio-dmac0" , 502, R8A7791_CLK_HP),"adsp_mod" , 506, R8A7791_CLK_ADSP),"thermal" , 522, CLK_EXTAL),"pwm" , 523, R8A7791_CLK_P),"usb-ehci" , 703, R8A7791_CLK_MP),"usbhs" , 704, R8A7791_CLK_HP),"hscif2" , 713, R8A7791_CLK_ZS),"scif5" , 714, R8A7791_CLK_P),"scif4" , 715, R8A7791_CLK_P),"hscif1" , 716, R8A7791_CLK_ZS),"hscif0" , 717, R8A7791_CLK_ZS),"scif3" , 718, R8A7791_CLK_P),"scif2" , 719, R8A7791_CLK_P),"scif1" , 720, R8A7791_CLK_P),"scif0" , 721, R8A7791_CLK_P),"du1" , 723, R8A7791_CLK_ZX),"du0" , 724, R8A7791_CLK_ZX),"lvds0" , 726, R8A7791_CLK_ZX),"ipmmu-sgx" , 800, R8A7791_CLK_ZX),"mlb" , 802, R8A7791_CLK_HP),"vin2" , 809, R8A7791_CLK_ZG),"vin1" , 810, R8A7791_CLK_ZG),"vin0" , 811, R8A7791_CLK_ZG),"etheravb" , 812, R8A7791_CLK_HP),"ether" , 813, R8A7791_CLK_P),"sata1" , 814, R8A7791_CLK_ZS),"sata0" , 815, R8A7791_CLK_ZS),"gyro-adc" , 901, R8A7791_CLK_P),"gpio7" , 904, R8A7791_CLK_CP),"gpio6" , 905, R8A7791_CLK_CP),"gpio5" , 907, R8A7791_CLK_CP),"gpio4" , 908, R8A7791_CLK_CP),"gpio3" , 909, R8A7791_CLK_CP),"gpio2" , 910, R8A7791_CLK_CP),"gpio1" , 911, R8A7791_CLK_CP),"gpio0" , 912, R8A7791_CLK_CP),"can1" , 915, R8A7791_CLK_P),"can0" , 916, R8A7791_CLK_P),"qspi_mod" , 917, R8A7791_CLK_QSPI),"i2c5" , 925, R8A7791_CLK_HP),"iicdvfs" , 926, R8A7791_CLK_CP),"i2c4" , 927, R8A7791_CLK_HP),"i2c3" , 928, R8A7791_CLK_HP),"i2c2" , 929, R8A7791_CLK_HP),"i2c1" , 930, R8A7791_CLK_HP),"i2c0" , 931, R8A7791_CLK_HP),"ssi-all" , 1005, R8A7791_CLK_P),"ssi9" , 1006, MOD_CLK_ID(1005)),"ssi8" , 1007, MOD_CLK_ID(1005)),"ssi7" , 1008, MOD_CLK_ID(1005)),"ssi6" , 1009, MOD_CLK_ID(1005)),"ssi5" , 1010, MOD_CLK_ID(1005)),"ssi4" , 1011, MOD_CLK_ID(1005)),"ssi3" , 1012, MOD_CLK_ID(1005)),"ssi2" , 1013, MOD_CLK_ID(1005)),"ssi1" , 1014, MOD_CLK_ID(1005)),"ssi0" , 1015, MOD_CLK_ID(1005)),"scu-all" , 1017, R8A7791_CLK_P),"scu-dvc1" , 1018, MOD_CLK_ID(1017)),"scu-dvc0" , 1019, MOD_CLK_ID(1017)),"scu-ctu1-mix1" , 1020, MOD_CLK_ID(1017)),"scu-ctu0-mix0" , 1021, MOD_CLK_ID(1017)),"scu-src9" , 1022, MOD_CLK_ID(1017)),"scu-src8" , 1023, MOD_CLK_ID(1017)),"scu-src7" , 1024, MOD_CLK_ID(1017)),"scu-src6" , 1025, MOD_CLK_ID(1017)),"scu-src5" , 1026, MOD_CLK_ID(1017)),"scu-src4" , 1027, MOD_CLK_ID(1017)),"scu-src3" , 1028, MOD_CLK_ID(1017)),"scu-src2" , 1029, MOD_CLK_ID(1017)),"scu-src1" , 1030, MOD_CLK_ID(1017)),"scu-src0" , 1031, MOD_CLK_ID(1017)),"scifa3" , 1106, R8A7791_CLK_MP),"scifa4" , 1107, R8A7791_CLK_MP),"scifa5" , 1108, R8A7791_CLK_MP),static const unsigned int r8a7791_crit_mod_clks[] __initconst = {/* RWDT */ /* INTC-SYS (GIC) */ /* * CPG Clock Data /* * MD EXTAL PLL0 PLL1 PLL3 * 14 13 19 (MHz) *1 *1 *--------------------------------------------------- * 0 0 0 15 x172/2 x208/2 x106 * 0 0 1 15 x172/2 x208/2 x88 * 0 1 0 20 x130/2 x156/2 x80 * 0 1 1 20 x130/2 x156/2 x66 * 1 0 0 26 / 2 x200/2 x240/2 x122 * 1 0 1 26 / 2 x200/2 x240/2 x102 * 1 1 0 30 / 2 x172/2 x208/2 x106 * 1 1 1 30 / 2 x172/2 x208/2 x88 * * *1 : Table 7.5a indicates VCO output (PLLx = VCO/2) #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {static int __init r8a7791_cpg_mssr_init(struct device *dev)const struct rcar_gen2_cpg_pll_config *cpg_pll_config;struct device_node *np = dev->of_node;unsigned int i;int error;if (error)return error;if (of_device_is_compatible(np, "renesas,r8a7793-cpg-mssr" )) {/* R-Car M2-N uses a 1/5 divider for ZG */ for (i = 0; i < ARRAY_SIZE(r8a7791_core_clks); i++)if (r8a7791_core_clks[i].id == R8A7791_CLK_ZG) {break ;return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);const struct cpg_mssr_info r8a7791_cpg_mssr_info __initconst = {/* Core Clocks */ /* Module Clocks */ /* Critical Module Clocks */ /* Callbacks */
Messung V0.5 C=97 H=58 G=79
¤ Dauer der Verarbeitung: 0.1 Sekunden
(vorverarbeitet)
¤ *© Formatika GbR, Deutschland
