// SPDX-License-Identifier: GPL-2.0-only /* * Pistachio SoC clock controllers * * Copyright (C) 2014 Google, Inc. #include <linux/clk-provider.h>#include <linux/init.h>#include <linux/io.h>#include <linux/kernel.h>#include <linux/of.h>#include <dt-bindings/clock/pistachio-clk.h>#include "clk.h" static struct pistachio_gate pistachio_gates[] __initdata = {"mips" , "mips_div" , 0x104, 0),"audio_in" , "audio_clk_in_gate" , 0x104, 1),"audio" , "audio_div" , 0x104, 2),"i2s" , "i2s_div" , 0x104, 3),"spdif" , "spdif_div" , 0x104, 4),"audio_dac" , "audio_dac_div" , 0x104, 5),"rpu_v" , "rpu_v_div" , 0x104, 6),"rpu_l" , "rpu_l_div" , 0x104, 7),"rpu_sleep" , "rpu_sleep_div" , 0x104, 8),"wifi_pll_gate" , "wifi_pll_mux" , 0x104, 9),"rpu_core" , "rpu_core_div" , 0x104, 10),"wifi_adc" , "wifi_div8_mux" , 0x104, 11),"wifi_dac" , "wifi_div4_mux" , 0x104, 12),"usb_phy" , "usb_phy_div" , 0x104, 13),"enet_in" , "enet_clk_in_gate" , 0x104, 14),"enet" , "enet_div" , 0x104, 15),"uart0" , "uart0_div" , 0x104, 16),"uart1" , "uart1_div" , 0x104, 17),"periph_sys" , "sys_internal_div" , 0x104, 18),"spi0" , "spi0_div" , 0x104, 19),"spi1" , "spi1_div" , 0x104, 20),"event_timer" , "event_timer_div" , 0x104, 21),"aux_adc_internal" , "sys_internal_div" ,"aux_adc" , "aux_adc_div" , 0x104, 23),"sd_host" , "sd_host_div" , 0x104, 24),"bt" , "bt_div" , 0x104, 25),"bt_div4" , "bt_div4_div" , 0x104, 26),"bt_div8" , "bt_div8_div" , 0x104, 27),"bt_1mhz" , "bt_1mhz_div" , 0x104, 28),static struct pistachio_fixed_factor pistachio_ffs[] __initdata = {"wifi_div4" , "wifi_pll" , 4),"wifi_div8" , "wifi_pll" , 8),static struct pistachio_div pistachio_divs[] __initdata = {"mips_internal_div" , "mips_pll_mux" ,"mips_div" , "mips_internal_div" , 0x208, 8),"audio_div" , "audio_mux" ,"i2s_div" , "audio_pll_mux" ,"spdif_div" , "audio_pll_mux" ,"audio_dac_div" , "audio_pll_mux" ,"rpu_v_div" , "rpu_v_pll_mux" , 0x21c, 2),"rpu_l_div" , "rpu_l_mux" , 0x220, 2),"rpu_sleep_div" , "xtal" , 0x224, 10),"rpu_core_div" , "rpu_core_mux" , 0x228, 3),"usb_phy_div" , "sys_internal_div" , 0x22c, 6),"enet_div" , "enet_mux" , 0x230, 6),"uart0_internal_div" , "sys_pll_mux" ,"uart0_div" , "uart0_internal_div" , 0x238, 10,"uart1_internal_div" , "sys_pll_mux" ,"uart1_div" , "uart1_internal_div" , 0x240, 10,"sys_internal_div" , "sys_pll_mux" , 0x244, 3),"spi0_internal_div" , "sys_pll_mux" ,"spi0_div" , "spi0_internal_div" , 0x24c, 7),"spi1_internal_div" , "sys_pll_mux" ,"spi1_div" , "spi1_internal_div" , 0x254, 7),"event_timer_internal_div" ,"event_timer_mux" , 0x258, 3),"event_timer_div" , "event_timer_internal_div" ,"aux_adc_internal_div" ,"aux_adc_internal" , 0x260, 3),"aux_adc_div" , "aux_adc_internal_div" , 0x264, 10),"sd_host_div" , "sd_host_mux" , 0x268, 6),"bt_div" , "bt_pll_mux" , 0x26c, 6),"bt_div4_div" , "bt_pll_mux" , 0x270, 6),"bt_div8_div" , "bt_pll_mux" , 0x274, 6),"bt_1mhz_internal_div" , "bt_pll_mux" ,"bt_1mhz_div" , "bt_1mhz_internal_div" , 0x27c, 10),"xtal" , "audio_clk_in_gate" };"xtal" , "mips_pll" };"xtal" , "audio_pll" , "audio_in" };"audio_pll_mux" , "debug_mux" };"xtal" , "rpu_v_pll" };"xtal" , "rpu_l_pll" };"rpu_l_pll_mux" , "mips_pll_mux" };"xtal" , "wifi_pll" };"xtal" , "wifi_div4" };"xtal" , "wifi_div8" };"wifi_pll_gate" , "wifi_div4_mux" ,"rpu_l_pll_mux" };"xtal" , "sys_pll" };"sys_internal_div" , "enet_in" };"audio_pll_mux" , "sys_internal_div" };"sys_internal_div" , "bt_pll_mux" };"xtal" , "bt_pll" };static struct pistachio_mux pistachio_muxes[] __initdata = {"audio_refclk_mux" , mux_xtal_audio_refclk,"mips_pll_mux" , mux_xtal_mips, 0x200, 1),"audio_pll_mux" , mux_xtal_audio, 0x200, 2),"audio_mux" , mux_audio_debug, 0x200, 4),"rpu_v_pll_mux" , mux_xtal_rpu_v, 0x200, 5),"rpu_l_pll_mux" , mux_xtal_rpu_l, 0x200, 6),"rpu_l_mux" , mux_rpu_l_mips, 0x200, 7),"wifi_pll_mux" , mux_xtal_wifi, 0x200, 8),"wifi_div4_mux" , mux_xtal_wifi_div4, 0x200, 9),"wifi_div8_mux" , mux_xtal_wifi_div8, 0x200, 10),"rpu_core_mux" , mux_wifi_div4_rpu_l, 0x200, 11),"sys_pll_mux" , mux_xtal_sys, 0x200, 13),"enet_mux" , mux_sys_enet, 0x200, 14),"event_timer_mux" , mux_audio_sys, 0x200, 15),"sd_host_mux" , mux_sys_bt, 0x200, 16),"bt_pll_mux" , mux_xtal_bt, 0x200, 17),static struct pistachio_pll pistachio_plls[] __initdata = {"mips_pll" , "xtal" , PLL_GF40LP_LAINT, 0x0),"audio_pll" , "audio_refclk_mux" ,"rpu_v_pll" , "xtal" , PLL_GF40LP_LAINT, 0x20),"rpu_l_pll" , "xtal" , PLL_GF40LP_LAINT, 0x2c),"sys_pll" , "xtal" , PLL_GF40LP_FRAC, 0x38),"wifi_pll" , "xtal" , PLL_GF40LP_FRAC, 0x4c),"bt_pll" , "xtal" , PLL_GF40LP_LAINT, 0x60),"mips_pll_mux" , "rpu_v_pll_mux" ,"rpu_l_pll_mux" , "sys_pll_mux" ,"wifi_pll_mux" , "bt_pll_mux" };static const u32 mux_debug_idx[] = { 0x0, 0x1, 0x2, 0x4, 0x8, 0x10 };static unsigned int pistachio_critical_clks_core[] __initdata = {static unsigned int pistachio_critical_clks_sys[] __initdata = {static void __init pistachio_clk_init(struct device_node *np)struct pistachio_clk_provider *p;struct clk *debug_clk;if (!p)return ;"debug_mux" , mux_debug,"img,pistachio-clk" , pistachio_clk_init);static struct pistachio_gate pistachio_periph_gates[] __initdata = {"sys" , "periph_sys" , 0x100, 0),"bus_sys" , "periph_sys" , 0x100, 1),"ddr" , "periph_sys" , 0x100, 2),"rom" , "rom_div" , 0x100, 3),"counter_fast" , "counter_fast_div" ,"counter_slow" , "counter_slow_div" ,"ir" , "ir_div" , 0x100, 6),"wd" , "wd_div" , 0x100, 7),"pdm" , "pdm_div" , 0x100, 8),"pwm" , "pwm_div" , 0x100, 9),"i2c0" , "i2c0_div" , 0x100, 10),"i2c1" , "i2c1_div" , 0x100, 11),"i2c2" , "i2c2_div" , 0x100, 12),"i2c3" , "i2c3_div" , 0x100, 13),static struct pistachio_div pistachio_periph_divs[] __initdata = {"rom_div" , "periph_sys" , 0x10c, 7),"counter_fast_div" , "periph_sys" ,"counter_slow_pre_div" ,"periph_sys" , 0x114, 7),"counter_slow_div" ,"counter_slow_pre_div" , 0x118, 7),"ir_pre_div" , "periph_sys" , 0x11c, 7,"ir_div" , "ir_pre_div" , 0x120, 7,"wd_pre_div" , "periph_sys" , 0x124, 7,"wd_div" , "wd_pre_div" , 0x128, 7,"pdm_pre_div" , "periph_sys" , 0x12c, 7),"pdm_div" , "pdm_pre_div" , 0x130, 7),"pwm_pre_div" , "periph_sys" , 0x134, 7),"pwm_div" , "pwm_pre_div" , 0x138, 7),"i2c0_pre_div" , "periph_sys" , 0x13c, 7),"i2c0_div" , "i2c0_pre_div" , 0x140, 7),"i2c1_pre_div" , "periph_sys" , 0x144, 7),"i2c1_div" , "i2c1_pre_div" , 0x148, 7),"i2c2_pre_div" , "periph_sys" , 0x14c, 7),"i2c2_div" , "i2c2_pre_div" , 0x150, 7),"i2c3_pre_div" , "periph_sys" , 0x154, 7),"i2c3_div" , "i2c3_pre_div" , 0x158, 7),static void __init pistachio_clk_periph_init(struct device_node *np)struct pistachio_clk_provider *p;if (!p)return ;"img,pistachio-clk-periph" ,static struct pistachio_gate pistachio_sys_gates[] __initdata = {"i2c0_sys" , "sys" , 0x8, 0),"i2c1_sys" , "sys" , 0x8, 1),"i2c2_sys" , "sys" , 0x8, 2),"i2c3_sys" , "sys" , 0x8, 3),"i2s_in_sys" , "sys" , 0x8, 4),"paud_out_sys" , "sys" , 0x8, 5),"spdif_out_sys" , "sys" , 0x8, 6),"spi0_master_sys" , "sys" , 0x8, 7),"spi0_slave_sys" , "sys" , 0x8, 8),"pwm_sys" , "sys" , 0x8, 9),"uart0_sys" , "sys" , 0x8, 10),"uart1_sys" , "sys" , 0x8, 11),"spi1_sys" , "sys" , 0x8, 12),"mdc_sys" , "sys" , 0x8, 13),"sd_host_sys" , "sys" , 0x8, 14),"enet_sys" , "sys" , 0x8, 15),"ir_sys" , "sys" , 0x8, 16),"wd_sys" , "sys" , 0x8, 17),"timer_sys" , "sys" , 0x8, 18),"i2s_out_sys" , "sys" , 0x8, 24),"spdif_in_sys" , "sys" , 0x8, 25),"event_timer_sys" , "sys" , 0x8, 26),"hash_sys" , "sys" , 0x8, 27),static void __init pistachio_cr_periph_init(struct device_node *np)struct pistachio_clk_provider *p;if (!p)return ;"img,pistachio-cr-periph" ,static struct pistachio_gate pistachio_ext_gates[] __initdata = {"enet_clk_in_gate" , "enet_clk_in" , 0x58, 5),"audio_clk_in_gate" , "audio_clk_in" , 0x58, 8)static void __init pistachio_cr_top_init(struct device_node *np)struct pistachio_clk_provider *p;if (!p)return ;"img,pistachio-cr-top" ,
Messung V0.5 C=98 H=98 G=97
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