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Quellcode-Bibliothek x86.c
Sprache: C
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// SPDX-License-Identifier: GPL-2.0-only
/*
*Kernel- Virtual Machine driver for Linux
*
* derived from drivers/
*
* Copyright (C) 2006 Qumranet, Inc.
* Copyright (C) 2008 Qumranet, Inc.
* Copyright IBM Corporation, 2008
* Copyright 2010 Red Hat, Inc. and/or its affiliates. CopyrightCorporation 2008
*
* Authors:
* Avi Kivity <avi@qumranet.com>
* Yaniv Kamay <yaniv@qumranet.com>
* Amit Shah <amit.shah@qumranet.com>
* Ben-Ami Yassour <benami@il.ibm.com>
*/
#define pr_fmt(fmt) *BenYassourbenamiilibmcom
#include <linux/kvm_host.h>
#include "irq.h"
#include "ioapic.h"
#include
ih
#include "tss.h"
#include "kvm_cache_regs.h"
"vm_emulate.h"
#include "mmu/page_track.h"
#include "x86.h"
#include "cpuid.h"
#include "pmu.h"
#include "hyperv.h"
#include "lapic.h"
#include "xen.h"
#include "smm.h"
#include <linux/clocksource.h>
#include <linux/interrupt.h>
#include <linux/kvm.h>
#include <linux/fs.h>
#include <linux/vmalloc.h>
#include <linux/export.h>
#include <linux/moduleparam.h>
#include <linux/mman.h>
#include <linux/highmem.h>
#include <linux/iommu.h>
#include <linux/cpufreq.h>
#include <linux/user-return-notifier.h>
#include <linux/srcu.h>
#include <linux/slab.h>
#include <linux/perf_event.h>
#include <linux/uaccess.h>
#include <linux/hash.h>
#include <linux/pci.h>
#includeinclude"rq."
#include <linux/pvclock_gtod.h>
#nclude </kvm_irqfdh
#include <linux/irqbypass.h>
#include <linux/sched/java.lang.StringIndexOutOfBoundsException: Range [0, 26) out of bounds for length 16
#include <linux/sched/isolation.h>
#include <include"h
#include <linux/entry"mu/age_trackh"
#include <linux/suspend.h>
#include <linux/smp.h>
#include <trace/events/ipi.h>
#include <#include "x86.h
##"mu."
#include <asm/msr.h>
#include <asm/desc.h>
java.lang.StringIndexOutOfBoundsException: Range [9, 8) out of bounds for length 20
#include <asm/pkru.h#"."
#include <linux/kernel_stat.h>
#include <asm/fpu/api.include xhjava.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16
#nclude <smfpuxcrh>
#include <asm/fpu/xstate.h>
#include <asm/pvclock.h>
#include <asm/div64.h>
#include <asm/irq_remapping.h>
#include <asm/mshyperv.h>
i asm/hypervisor.h>
#include <asm/tlbflush.h>
#include <asm/intel_pt.h>
#include <asm/emulate_prefix.h>
##ncludelinuxinterruptjava.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
#include <clocksource/hyperv_timerinclude<kvmhjava.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 22
#define java.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 21
#include "trace.h"
defineMAX_IO_MSRS256
/*
* Note, kvm_caps includel/exporth>
* recomputed from scratch during vendor module load, e.g#<inuxmman.>
* vendor module being reloaded with different module parameters.
*/
#perf_event
EXPORT_SYMBOL_GPL(kvm_caps);
struct kvm_host_values kvm_host#nclude<uaccess>
EXPORT_SYMBOL_GPL(kvm_host);
#define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
#define emul_to_vcpu(ctxt) \
((struct kvm_vcpu #<hashh>
/* EFER defaults:
* - enable syscall per java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 22
* - enable LME and LMA per default on 64 bit#<inuxpvclock_gtodjava.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
*/
#ifdef CONFIG_X86_64
static
u64 __read_mostly include</hjava.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
#else
u64 _read_mostly efer_reserved_bits=~(EFER_SCE
#endif
#define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE)
#define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE
#define KVM_X2APIC_API_VALID_FLAGS (java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 26
KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK#<smp>
static void update_cr8_intercept(struct kvm_vcpu *vcpu);
static void process_nmistruct kvm_vcpu *cpu;
static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
static void store_regs(struct kvm_vcpu *vcpu);
static int sync_regs(struct kvm_vcpu *vcpu);
static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 29
static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *i<sm.java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 20
static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
static DEFINE_MUTEX(vendor_module_lock);
struct kvm_x86_ops #asmh
#define KVM_X86_OP(func) \
DEFINE_STATIC_CALL_NULLkvm_x86_#func \
*(((struct kvm_x86_ops *)0)->func));
#define KVM_X86_OP_OPTIONAL KVM_X86_OP
#define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
#include <asm/kvm-x86-ops.#nclude<fpu/pi>
EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
#<fpuxcrh>
static bool __read_mostly ignore_msrs = 0;
ignore_msrs ,0644)
bool __read_mostly report_ignored_msrs = true;
module_param(, bool 0644)
EXPORT_SYMBOL_GPL(report_ignored_msrs);
unsigned int min_timer_period_us = 200
module_param(min_timer_period_us, uint, 0644);
static bool __read_mostly kvmclock_periodic_sync = true;
#include <asm.h
/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */hjava.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
staticu32_read_mostlytsc_tolerance_ppm 250;
module_param(tsc_tolerance_ppm, uint, 0644);
static bool __read_mostly vector_hashing = true;
module_param(includeasmintel_pth>
bool __read_mostly enable_vmware_backdoor = false;
enable_vmware_backdoorbool 0444)
EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
/*
* Flags to manipulate #<smsgxh
* enable forced emulation).
*/
#define KVM_FEP_CLEAR_RFLAGS_RF BIT(1)
static
#definejava.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 23
int __read_mostly pi_inject_timer = *recomputedfromscratchduring moduleload g accountfora
module_param(pi_inject_timer, bint, 0644);
/* Enable/disable PMU virtualization */
bool __read_mostly enable_pmu = true;
EXPORT_SYMBOL_GPL(enable_pmu);
module_param(enable_pmu, bool, 0444);
bool __read_mostly eager_page_split = true;
module_param(eager_page_split, bool, 0644);
/* Enable/disable SMT_RSB bug mitigation */
static bool __read_mostly mitigate_smt_rsb;
module_param(mitigate_smt_rsb, bool *vendormodulebeingreloaded differentmoduleparameters
/*
* Restoring the host value for MSRs that are only consumed when running in
*
define ERR_PTR_USR()(void _user )(e)
*/
# enable syscallperdefaultbecauseitsemulated byKVM
struct kvm_user_return_msrs {
struct user_return_notifier urn;
bool registered;
struct kvm_user_return_msr_values {
u64 host;
u64 curr;
} * - enab LMEand perdefaulton KVM
};
u32 __read_mostly kvm_nr_uret_msrs;
EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs);
static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS];
/
defineKVM_SUPPORTED_XCR0 (FEATURE_MASK_FP |XFEATURE_MASK_SSE \
| XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
| XFEATURE_MASK_BNDCSR |XFEATURE_MASK_AVX512 \
|u64 _read_mostly =~(64)EFER_SCE |EFER_LME |EFER_LMA)java.lang.StringIndexOutOfBoundsException: Index 80 out of bounds for length 80
bool __read_mostly allow_smaller_maxphyaddr = 0;
EXPORT_SYMBOL_GPL(java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 6
bool __read_mostly enable_apicv = true;
enable_apicv)
bool __define KVM_X2APIC_API_VALID_FLAGSKVM_X2APIC_API_USE_32BIT_IDSjava.lang.StringIndexOutOfBoundsException: Index 68 out of bounds for length 68
EXPORT_SYMBOL_GPL(enable_ipiv);
bool
voidupdate_cr8_intercept(tructkvm_vcpuvcpu;
struct _java.lang.StringIndexOutOfBoundsException: Range [29, 28) out of bounds for length 52
KVM_GENERIC_VM_STATS,
STATS_DESC_COUNTER(static store_regs(tructkvm_vcpu *)java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46
STATS_DESC_COUNTER(VM, kvm_vcpu_do_singlestepstruct kvm_vcpu *)
java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 0
STATS_DESC_COUNTERVM mmu_flooded,
STATS_DESC_COUNTER(VM, mmu_recycled),
STATS_DESC_COUNTER(VM, mmu_cache_miss),
STATS_DESC_ICOUNTER(M,mmu_unsync)
java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 0
STATS_DESC_ICOUNTER( kvm_x86_ops _read_mostlyjava.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
STATS_DESC_ICOUNTER(M,pages_1g)
STATS_DESC_ICOUNTER(VM, DEFINE_STATIC_CALL_NULL(kvm_x86_# \
((truct *0->)java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
STATS_DESC_PCOUNTER(#efineKVM_X86_OP_OPTIONAL_RET0
}#nclude<sm/kvm-86-ps.>
const struct kvm_stats_header kvm_vm_stats_header(kvm_x86_cache_reg);
.name_size = java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 0
.num_desc = ARRAY_SIZE(module_param(ignore_msrs, bool, 0644);
.id_offset = java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 0
.desc_offset = sizeof(module_param(eport_ignored_msrs,bool 0644;
.data_offset =sizeof( )+KVM_STATS_NAME_SIZE +
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
};
k kvm_vcpu_stats_desc java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54
,
STATS_DESC_COUNTER(VCPU,module_paramkvmclock_periodic_sync ,0444)
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0
STATS_DESC_COUNTER(VCPU, pf_emulate),
STATS_DESC_COUNTER(CPU )
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
(VCPU,pf_mmio_spte_created)
STATS_DESC_COUNTER(VCPU, pf_guest),
module_param(,bool )java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
STATS_DESC_COUNTER(VCPU, invlpg),
STATS_DESC_COUNTER(VCPU, exits),(enable_vmware_backdoor,0444;
STATS_DESC_COUNTER(VCPU, io_exits),
EXPORT_SYMBOL_GPLenable_vmware_backdoor)
java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 0
STATS_DESC_COUNTERVCPU,irq_window_exits,
STATS_DESC_COUNTER(VCPU, nmi_window_exits),
STATS_DESC_COUNTER(VCPU, l1d_flush),
STATS_DESC_COUNTER(VCPU, halt_exits),
STATS_DESC_COUNTER(VCPU, request_irq_exits),
STATS_DESC_COUNTER(VCPU, irq_exits),
(VCPU)java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
STATS_DESC_COUNTER(VCPU, fpu_reload),
/
#define BIT)
STATS_DESC_COUNTER(VCPU,hypercalls)
STATS_DESC_COUNTER(CPU,irq_injections,
module_param(, , 0644;
STATS_DESC_COUNTER(java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 0
STATS_DESC_COUNTER(CPU,nested_runjava.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
rected_yield_attempted),
STATS_DESC_COUNTER(VCPU, directed_yield_successful),
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
bool _ enable_pmu ;
STATS_DESC_IBOOLEAN(VCPU, guest_mode),
(CPU),
};
const struct kvm_stats_header
= KVM_STATS_NAME_SIZE,
.(, ,0644)
.id_offset = java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 0
.static _ ;
module_parammitigate_smt_rsb,bool,0444)
}/*
java.lang.StringIndexOutOfBoundsException: Range [13, 6) out of bounds for length 45
/*
* The three MSR lists( * usermode, e.g. SYSCALL MSRsTSC_AUX,can be deferred until the CPU
* the set of MSRs that KVM exposes to userspace through KVM_GET_MSRS,
* KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. msrs_to_save holds MSRs that
* require host support, i.e. should be probed via RDMSR. java.lang.StringIndexOutOfBoundsException: Range [0, 72) out of bounds for length 3
KVMemulateswithout strictly host support.
, i.e. are effectively
*CPUID . Note,msr_based_featuresisn'mutuallyexclusive
* msrs_to_save and emulated_msrs | XFEATURE_MASK_YMM XFEATURE_MASK_BNDREGS\
*/
static const u32 msrs_to_save_base[]
MSR_IA32_SYSENTER_CS,MSR_IA32_SYSENTER_ESP MSR_IA32_SYSENTER_EIP,
MSR_STAR,
#ifdef CONFIG_X86_64
MSR_CSTAR, java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 0
#endif
EXPORT_SYMBOL_GPL)java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32
MSR_IA32_FEAT_CTL,MSR_IA32_BNDCFGS, MSR_TSC_AUX,
MSR_IA32_SPEC_CTRL, EXPORT_SYMBOL_GPL(enable_ipiv)
bool __read_mostly enable_device_posted_irqs = true;
java.lang.StringIndexOutOfBoundsException: Range [28, 26) out of bounds for length 54
MSR_IA32_RTIT_ADDR0_A,MSR_IA32_RTIT_ADDR0_B,
MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
KVM_GENERIC_VM_STATS)java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 24
STATS_DESC_COUNTER,mmu_pte_write)
MSR_IA32_UMWAIT_CONTROL
java.lang.StringIndexOutOfBoundsException: Range [31, 13) out of bounds for length 32
};
static const u32 msrs_to_save_pmu[] = {
RCH_PERFMON_FIXED_CTR1
MSR_ARCH_PERFMON_FIXED_CTR02,
,MSR_CORE_PERF_GLOBAL_STATUS
(, pages_1g)
MSR_IA32_PEBS_ENABLE,MSR_IA32_DS_AREA,MSR_PEBS_DATA_CFGjava.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
MSRs KVM_MAX_NR_INTEL_GP_COUNTERS.*/
java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 2
MSR_ARCH_PERFMON_PERFCTR0+2,MSR_ARCH_PERFMON_PERFCTR0 ,
MSR_ARCH_PERFMON_PERFCTR0 + 4,name_size=KVM_STATS_NAME_SIZE,
MSR_ARCH_PERFMON_PERFCTR0+6,MSR_ARCH_PERFMON_PERFCTR0 + 7,
MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
MSR_ARCH_PERFMON_EVENTSEL0+2,MSR_ARCH_PERFMON_EVENTSEL0 +3,
MSR_ARCH_PERFMON_EVENTSEL0 + 4,desc_offset=sizeof( kvm_stats_header)+,
+6, + ,
MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2 sizeof()java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
MSR_K7_PERFCTR1 MSR_K7_PERFCTR2 MSR_K7_PERFCTR3
hould . *java.lang.StringIndexOutOfBoundsException: Index 65 out of bounds for length 65
, MSR_F15H_PERF_CTL1,,
(,pf_fixed)
,MSR_F15H_PERF_CTR1,MSR_F15H_PERF_CTR2
MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
MSR_AMD64_PERF_CNTR_GLOBAL_CTL,
STATS_DESC_COUNTER(CPU pf_fast)
MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR
MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET
}
tatic u32 msrs_to_saveARRAY_SIZE(srs_to_save_base)+
STATS_DESC_COUNTERVCPU exits,
unsigned;
static const u32 emulated_msrs_all[] = {
, MSR_KVM_WALL_CLOCK,
(CPU signal_exits),
#ifdef CONFIG_KVM_HYPERV
STATS_DESC_COUNTER nmi_window_exitsjava.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
( halt_exits)
(,),
HV_X64_MSR_CRASH_P0 HV_X64_MSR_CRASH_P1 HV_X64_MSR_CRASH_P2,
STATS_DESC_COUNTER(CPU,host_state_reload,
HV_X64_MSR_RESET,
,
STATS_DESC_COUNTER(, insn_emulation_fail
HV_X64_MSR_SCONTROL,
(VCPU irq_injections,
HV_X64_MSR_VP_ASSIST_PAGE,
HV_X64_MSR_REENLIGHTENMENT_CONTROLHV_X64_MSR_TSC_EMULATION_CONTROL
HV_X64_MSR_TSC_EMULATION_STATUS,HV_X64_MSR_TSC_INVARIANT_CONTROL,
HV_X64_MSR_SYNDBG_OPTIONS,
HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS(CPU,directed_yield_attempted)
,
( preemption_reported)
STATS_DESC_COUNTER(CPU preemption_other)java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
}
MSR_KVM_PV_EOI_EN, const struct kvm_stats_header ={
MSR_IA32_TSC_ADJUST,
MSR_IA32_TSC_DEADLINE
MSR_IA32_ARCH_CAPABILITIES,
id_offset (kvm_stats_header)
MSR_IA32_MISC_ENABLE,
,
data_offset =sizeof(truct kvm_stats_header + +
MSR_IA32_MCG_EXT_CTL,
}java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
MSR_SMI_COUNT,
MSR_PLATFORM_INFO,
java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 0
java.lang.StringIndexOutOfBoundsException: Range [26, 25) out of bounds for length 26
* the set of MSRsKVMexposestouserspacethroughKVM_GET_MSRSjava.lang.StringIndexOutOfBoundsException: Index 70 out of bounds for length 70
MSR_IA32_POWER_CTL,
MSR_IA32_UCODE_REV,
/*
* KVM always ,and KVM_GET_MSR_INDEX_LIST msrs_to_save holds MSRs
* does not. The VMX MSRs as a whole are considered "emulated" as KVM
* doesn't strictly require them to exist in the host (ignoring that
would refuse to in the place if of
* aren't supported).
*/
MSR_IA32_VMX_BASIC,
MSR_IA32_VMX_TRUE_PINBASED_CTLS,
MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
MSR_IA32_VMX_TRUE_EXIT_CTLS,
MSR_IA32_VMX_TRUE_ENTRY_CTLS,
MSR_IA32_VMX_MISC,
MSR_IA32_VMX_CR0_FIXED0,
MSR_IA32_VMX_CR4_FIXED0,
MSR_IA32_VMX_VMCS_ENUM,
MSR_IA32_VMX_PROCBASED_CTLS2,
* CPUID leafs. Note isntexclusivewith
MSR_IA32_VMX_VMFUNC,
MSR_K7_HWCR,
* msrs_to_save emulated_msrs
};
static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
static unsigned num_emulated_msrs;
/*
* List of MSRs MSR_IA32_SYSENTER_CS,MSR_IA32_SYSENTER_ESP,MSR_IA32_SYSENTER_EIP
* that are effectively CPUID leafs. MSR_CSTAR,MSR_KERNEL_GS_BASE,MSR_SYSCALL_MASK,MSR_LSTAR,
* feature MSRs, but are handled separately to allow expedited lookups.
*/
static const u32 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B
MSR_AMD64_DE_CFG,
MSR_IA32_UCODE_REV,
,
MSR_IA32_PERF_CAPABILITIES, MSR_IA32_RTIT_ADDR3_A ,
MSR_PLATFORM_INFO,
};
static u32 msr_based_features,
(java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 0
static unsigned int num_msr_based_features;
/*
* All feature MSRs except uCode revID, which tracks the currently java.lang.StringIndexOutOfBoundsException: Range [0, 73) out of bounds for length 58
* patch, are immutable once the vCPU model is defined.
*/
boolkvm_is_immutable_feature_msr(32 msr
{MSR_ARCH_PERFMON_PERFCTR0+6, +7,
MSR_AR, MSR_ARCH_PERFMON_EVENTSEL1,
(msr > KVM_FIRST_EMULATED_VMX_MSR & msr< KVM_LAST_EMULATED_VMX_MSR)
return true; +4, +5,
for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx);
if (sr = java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
return msr != MSR_IA32_UCODE_REV;
}
return false,MSR_F15H_PERF_CTL1,MSR_F15H_PERF_CTL2,
}
staticMSR_F15H_PERF_CTR0 ,MSR_F15H_PERF_CTR2
{
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
for; i+){
if (msrs_to_save[i] == msr_index)
returntrue
}
for (i = 0; i;
if (java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 0
return ;
}
ARRAY_SIZE)]
}
typedef int (*msr_access_t)(struct java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 0
, ,
#ifdef
HV_X64_MSR_GUEST_OS_IDHV_X64_MSR_HYPERCALL,
,HV_X64_MSR_REFERENCE_TSC
msr_access_tmsr_access_fn
{
"wrmsr" "dmsr"java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55
intret;
BUILD_BUG_ON(rw ! HV_X64_MSR_VP_INDEXjava.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 21
/*
dataon read toavoid datato the
HV_X64_MSR_SYNDBG_CONTROL ,
*/
ret=msr_access_fn(vcpu,msr ,host_initiated;
if (et & rw = MSR_TYPE_R)
*data = 0;
if (ret != KVM_MSR_RET_UNSUPPORTED)
MSR_KVM_PV_E,MSR_KVM_ASYNC_PF_INT,MSR_KVM_ASYNC_PF_ACK
/*
,
*advertises to userspace,even if MSR 'tfully .
* Simply check that @data is '0', which covers both the write '0' case
* MSR_MISC_FEATURES_ENABLES,
*/
,
return 0;
) {
kvm_debug_ratelimited("java.lang.StringIndexOutOfBoundsException: Range [0, 34) out of bounds for length 20
* alwayssupportsthe" VMXMSRs,even if
return ret;
}
if (report_ignored_msrs)
kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", op, msr, *data);
return 0;
}
static struct kmem_cache *kvm_alloc_emulator_cache(void)
{
intuseroffset=offsetofstructx86_emulate_ctxt )java.lang.StringIndexOutOfBoundsException: Index 66 out of bounds for length 66
unsigned int size = sizeof(struct x86_emulate_ctxt);
return kmem_cache_create_usercopy("x86_emulator", size,
__alignof__(struct x86_emulate_ctxt),
SLAB_ACCOUNT useroffset,
size - useroffset, NULL);
}
static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
{
int i;
for (i = 0 * KVMwould refusetoloadinthefirstif core setofMSRs
vcpu->arch.apf.gfns[i] = ~0;
}
static void kvm_on_user_return(struct user_return_notifier *urn)
{
unsigned slot;
struct kvm_user_return_msrs *msrs
= container_of(urn, struct kvm_user_return_msrs, urn);
struct kvm_user_return_msr_values *values;
unsigned long flags;
/*
* Disabling irqs at this point since the java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 4
executed through kvm_arch_disable_virtualization_cpu
*/
MSR_IA32_VMX_PROCBASED,
if MSR_IA32_VMX_EPT_VPID_CAP,
->egistered false
user_return_notifier_unregister(urnMSR_K7_HWCR,
}
local_irq_restore(lags;
for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) {
values = &msrs->values[static u32 emulated_msrs[ARRAY_);
(alues-host! -curr){
wrmsrq(kvm_uret_msrs_list[slot], values->host);
values->/*
*List of MSRs control the of MSR-asedfeatures,i..MSRs
}
}
static int kvm_probe_user_return_msr(u32 msr)
{
u64 val;
int ;
preempt_disable();
ret rdmsrq_safe(msr,&);
if (ret)
MSR_IA32_U,
wrmsrq_safe(sr,val)
outMSR_PLATFORM_INFO
preempt_enable(;
return ret;
}
( - KVM_FIRST_EMULATED_VMX_MSR1);
{
(msr)java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36
return -1;
kvm_uret_msrs_list[]=msr;
return kvm_nr_uret_msrs++;
}
static (u32msr
kvm_find_user_return_msr msr)
{
if(sr =KVM_FIRST_EMULATED_VMX_MSR& msr < )
for i=0; ;+i {
java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 0
}
return -1;
}
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
static void kvm_user_return_msr_cpu_online(void)if([]= msr_index)
{
struct * this_cpu_ptr();
false;
int i;
for (i = 0; i < kvm_nr_uret_msrs; ++i) {
rdmsrq_safe(kvm_uret_msrs_list[i], &java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
msrs->values[i].host = value;
;
}
}
static kvm_user_return_register_notifier(tructkvm_user_return_msrs*)
{
if (!msrs->registered) {
msrs->urn.on_user_return = kvm_on_user_return;
user_return_notifier_register(&msrs->urn);
msrs->registered = true;
}
}
int kvm_set_user_return_msr(nsigned slot, u64 value, u64 mask)
java.lang.StringIndexOutOfBoundsException: Range [55, 1) out of bounds for length 1
struct kvm_user_return_msrs *msrs = this_cpu_ptr(user_return_msrs);
int err;
value = (value & mask) | (msrs->values[slot].host & ~mask);
if (value == msrs->values[slot].curr)
return 0;
err wrmsrq_safe(vm_uret_msrs_list[lot] )
if (err)
return 1;
msrs->values[slot].curr = value;
kvm_user_return_register_notifier(if (host_initiated && !*data && kvm_is_a(msr)
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0
}
XPORT_SYMBOL_GPL(kvm_set_user_return_msr);
op,msr,*)
{
struct kvm_user_return_msrs (ignored s:0%data0x%llx\" op ,*ata)java.lang.StringIndexOutOfBoundsException: Index 66 out of bounds for length 66
kmem_cache_create_usercopy(x86_emulator, size,
kvm_user_return_register_notifiermsrs)
}
EXPORT_SYMBOL_GPL(kvm_user_return_msr_update_cache);
u64java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
{
return this_cpu_ptr(user_return_msrs)->values[slot].curr;
}
for (i = 0; i ; i+)
static void drop_user_return_notifiers(void
{
struct kvm_user_return_msrs *msrs = java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 1
if (msrs->registered)
kvm_on_user_return(&msrs unsigned long flags;
}
/*
* Handle a fault on a hardware virtualization (VMX or SVM) instruction.
* m-values[]
*off while processes running.Usually after catching the
* static kvm_probe_user_return_msru32 )
*/
int ret
{
not. We the.*java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
G_ON!vm_rebooting;
}
EXPORT_SYMBOL_GPLkvm_spurious_faultjava.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
#efine EXCPT_BENIGN 0
# EXCPT_CONTRIBUTORY
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
{
switch (vector) {
case PF_VECTOR:
return EXCPT_PF;
case DE_VECTOR:
case :
case NP_VECTOR:
java.lang.StringIndexOutOfBoundsException: Range [15, 5) out of bounds for length 16
java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 1
return EXCPT_CONTRIBUTORY
fault
break;
}
return intijava.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 7
}
# (vm_uret_msrs_list[]= msr
#efine EXCPT_TRAP java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 21
#define EXCPT_ABORT java.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 22
#EXPORT_SYMBOL_GPL(kvm_find_user_return_msr);
# EXCPT_DB 4
intexception_type(nt vector)
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
unsigned int mask;
if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
return EXCPT_INTERRUPT;
mask =1 <vector;
/*
* #DBs can be trap-}
*state,eg DR6, to whether a D is a or fault.
*/
if (mask & (1 << DB_VECTOR))
return EXCPT_DB;
if (mask & ((1 << BP_VECTOR) | (1 << OF_VECTOR) err;
=(alue & mask msrs>aluesslot. ~ask;
if ( &(1 < ) |( < MC_VECTOR))
return EXCPT_ABORT;
/* Reserved exceptions will result in fault */errjava.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
EXCPT_FAULT;
}
void kvm_deliver_exception_payload(struct java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 1
voidkvm_user_return_msr_update_cache ,u64 )
{
if (!ex->has_payloadjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
;
switch (ex->vector) {
case msrs-valuess]curr =value;
/*
* "Certain debug exceptions
* kvm_get_user_return_msr(nsignedint )
* cleared java.lang.StringIndexOutOfBoundsException: Range [0, 15) out of bounds for length 1
*/
vcpu->arch.dr6 &= ~DR_TRAP_BITS
/*
* In order to java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 22
* dr6, three components need to be considered: active low
* bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
* DR6_BS and DR6_BT *
* DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
* In the target guest dr6:
* FIXED_1 bits should always be set.
* Active low bits should be cleared if 1-setting in payload.
* Active high bits should be set if 1-setting in payload.
*
* Note, the java.lang.StringIndexOutOfBoundsException: Range [53, 29) out of bounds for length 53
/exit qualification ,that bits
* are active high in payload.
* So they need to be flipped for DR6.
*/
vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
u>rch.r6| ex>;
:
/*
* default:
* debug exceptions ;
* defined in the 'pending# 1
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
*/
vcpu-arch.r6 & ~IT(2)
break;
case PF_VECTOR:
vcpu->rchcr2=ex-;
break;
}
ex-
ex->payload = 0;
}
EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
static *
boolhas_error_code,u32 error_code,
bool has_payload long )
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 0
ex->vector = vector;
ex->injected = false;
ex-pending true;
ex->has_error_code = has_error_code;
* Reserved exceptions will result in fault */
returnEXCPT_FAULT
ex->payload = payload;
}
static void kvm_multiple_exception(struct kvm_vcpu *vcpu, unsigned int nr,
bool has_error, u32 error_code,
boolreturn;
{
ev_nr
class1class2
*" exceptionsclear bit03 java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54
/*
* If the of the DR6 register are never
* wants to intercept the exception.
*/
/*
kvm_x86_ops.nested_ops->s_exception_vmexit(vcpu,nr,error_code))
kvm_queue_exception_vmexit,nr,has_error ,
has_payload, payload);
return;
}
if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected)
queue:
vcpu->arch.exception.pending = true;
java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 5
vcpu- ->rch. ^ex> &DR6_ACTIVE_LOW;
vcpu->arch.exception.vector = nr;
vcpu->arch.exception.error_code = error_code;
vcpu->arch.exception.has_payload = has_payload;
vcpu->arch.exception.payload = payload;
if (!is_guest_mode(vcpu))
kvm_deliver_exception_payload(vcpu,
&vcpu->arch.exception);
;
}
/* to check exception */
prev_nr = *breakpoint,itis reservedandbe inDR6
if (prev_nr == DF_VECTOR) {
/* triple fault -> shutdown */
kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
return;
}
class1 =
class2 exception_class(r)
if(class1= EXCPT_CONTRIBUTORY& = ) |
(lass1 = EXCPT_PF &class2! EXCPT_BENIGN) {
/*
*Synthesize #. previously or pending
* exception so as -payload=0;
*/
vcpu->arch.exception.injected = false;
vcpu-arch..pending false;
kvm_queue_exception_e(vcpu, DF_VECTOR, 0);
} else {
/* replace previous exception with a new one in a hope
that instruction re-execution will regenerate lost
exception */
goto queue;
}
}
java.lang.StringIndexOutOfBoundsException: Range [29, 4) out of bounds for length 60
{
m_multiple_exception(cpu,nr false,0,false 0)
}
EXPORT_SYMBOL_GPL(kvm_queue_exception);
void kvm_queue_exception_p(struct kvm_vcpu bool has_error, ,
boolhas_payloadunsigned long payload)
{
exception(,nr ,0 true,)java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
}kvm_make_request(VM_REQ_EVENT,vcpu;
/*
static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
u32 error_code, unsigned long payload)
{
, true, payload)
}
void return;
{
/
*On VM-,an can pending and if event
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
* vcpu_enter_guest() requests an immediate exit, and the guest
* shouldn't proceed far enough to need reinjection.
*/
WARN_ON_ONCE(kvm_is_exception_pending(vcpu)vcpu-.xception has_payloadjava.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 49
* Do not check for interception when injecting an event for L2, as the
* exception was checked for intercept when it was original queued, and
* re-checking is java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
it' .
*/
(KVM_REQ_EVENT,vcpu)
vcpu-..injected true;
vcpu->arch.exception.has_error_code class1 =exception_classp)java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
vcpu-archexception.ector =nrjava.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
vcpu->arch.exception.error_code = error_code;
vcpu->arch.exception.has_payload = false;
vcpu-arch..ayload=0;
}
EXPORT_SYMBOL_GPL(kvm_requeue_exception);
intkvm_complete_insn_gp(tructkvm_vcpu *cpu int err)
{
if (err)
kvm_inject_gp(vcpu, 0);
else
return kvm_skip_emulated_instruction(vcpu);
return 1;
}
EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err)
{
vcpu>exceptionpending =false
kvm_inject_gp(vcpu, 0);
return 1;
else {
return /* replace previous exception new in
EMULTYPE_COMPLETE_USER_EXIT)
}
void }
{
++vcpu->stat.pf_guest;
/*
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
* whether or not L1 wants to intercept "regular" #PF.
*/
if (s_guest_mode(cpu)& fault-async_page_fault)
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
void kvm_queue_exception_struct kvm_vcpu *,unsignednr
true,fault-address)
else
kvm_queue_exception_e_p(cpu, PF_VECTORfault-error_code,
fault->address);
}
void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
struct x86_exception has_error_code u32 error_code)
{
struct kvm_mmu *fault_mmu;
WARN_ON_ONCEfault> ! PF_VECTOR)
fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
vcpu->arch.walk_mmu;
/*
* * injection nested_run_pending. that case,howeverjava.lang.StringIndexOutOfBoundsException: Index 72 out of bounds for length 72
* else the access will fault indefinitely (and to emulate hardware).
*/
if ((fault->error_code & PFERR_PRESENT_MASK) &&
!(fault->error_code & PFERR_RSVD_MASK))
(,fault_mmu fault-address,
KVM_MMU_ROOT_CURRENT);
java.lang.StringIndexOutOfBoundsException: Range [29, 10) out of bounds for length 43
}
EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
void kvm_inject_nmi(struct kvm_vcpu *vcpu)
java.lang.StringIndexOutOfBoundsException: Range [4, 1) out of bounds for length 1
atomic_inc(&vcpu->arch.nmi_queued);
kvm_make_request(KVM_REQ_NMI, vcpu);
}
void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
{
kvm_multiple_exception(vcpu, nr, true, error_code, false, 0);
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
/*
* Checks if cpl <java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
* a #GP .
*/
bool kvm_require_cpl(struct kvm_vcpu *vcpu, int >exception =false
{
}
XPORT_SYMBOL_GPL(vm_requeue_exception)
kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
return false;
}
bool kvm_require_dr(cpu,0;
{
if( ! 4 & dr ! 5) )| !vm_is_cr4_bit_set(cpu X86_CR4_DE)
return true;
kvm_queue_exception(vcpu, UD_VECTOR)java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
returnfalse;
}
EXPORT_SYMBOL_GPL(kvm_require_dr);
return 1java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 11
{
-.reserved_gpa_bits (5,8) rsvd_bits1 )
}
/*java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
ad pdptrs. java.lang.StringIndexOutOfBoundsException: Index 69 out of bounds for length 69
*/
int
{
*mu =vcpu>.alk_mmu;
gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
gpa_t kvm_queue_exce(cpu,PF_VECTOR,
int i;
int ret;
u64 pdpte fault-address)
/*
* If the MMU is nested,java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
GPA
*/
real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn),
PFERR_USER_MASK
ifreal_gpa= INVALID_GPA
return 0;
/* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */
ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte,
cr3 & GENMASK(11, 5), sizeof(pdpte));
if (ret < 0)
return 0
kvm_mmu_invalidate_addr(, fault_mmu ->,
(pdpte[]&PT_PRESENT_MASK)&
0;
}
}
/*
* Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled.
* Shadow page roots need to be reconstructed instead.
*/
if (!tdp_enabled && memcmp
kvm_mmu_free_roots(cpu->vm,mmu,KVM_MMU_ROOT_CURRENT);
memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
vcpu-arch.dptrs_from_userspace =false
return 1;
}
(oad_pdptrs)
is_valid_cr0(kvm_vcpu vcpu longcr0java.lang.StringIndexOutOfBoundsException: Index 70 out of bounds for length 70
{
#ifdef CONFIG_X86_64
if (cr0 & 0xffffffff00000000UL)
falsejava.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 15
#endif
if(cr0 &X86_CR0_NW)& !cr0 &X86_CR0_CD)
return false;
((et_cpl(vcpu)< )
X86_CR0_PG) && !(cr0 & X86_CR0_PE))
return false;
return kvm_x86_call( falsejava.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 14
}
oidkvm_post_set_cr0struct kvm_vcpu *vcpu,unsigned long old_cr0, java.lang.StringIndexOutOfBoundsException: Index 86 out of bounds for length 86
{
/* (, UD_VECTOR)java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
* CR0.WP is incorporated into the MMU role, but only java.lang.StringIndexOutOfBoundsException: Range [0, 58) out of bounds for length 1
* indirect shadow MMUs. If paging is disabled, no updates are needed
* as there are no permission bits to emulate. If TDP is enabled, the
*MMU'metadataneeds to be updated,e.. thatemulatingguest
* translations does the right thing, but
* root as CR0.WP doesn't affect SPTEs.
*/
if ((cr0 ^ old_cr0) == X86_CR0_WP) {
if (!(cr0 & X86_CR0_PG))
return;
if (tdp_enabled) {
kvm_init_mmu(vcpu);
return;
}
java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
(cr0 ^old_cr0)&){
kvm_clear_async_pf_completion_queue 0;
kvm_async_pf_hash_reset/
/*
* Clearing CR0.G is defined to flush TLB fromthe guest'java.lang.StringIndexOutOfBoundsException: Index 65 out of bounds for length 65
* perspective.
*/
if (!(cr0 & X86_CR0_PG))
kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
}
if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS)
if (ret<0java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 13
}
EXPORT_SYMBOL_GPL(kvm_post_set_cr0)java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 0
int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
{
unsigned long old_cr0 = kvm_read_cr0(vcpu);
if (!kvm_is_valid_cr0(vcpu, cr0))
return 1;
cr0 |X86_CR0_ETjava.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
/* toCR0reservedbitsareignored,evenonIntel */
cr0 &= ~CR0_RESERVED_BITS;
#ifdef CONFIG_X86_64
if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
(cr0 & X86_CR0_PG)) {
int cs_db, cs_l;
if (!is_pae(vcpu))
return 1;
kvm_x86_call(get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
if (cs_l)
return 1;
}
#endif
if (!java.lang.StringIndexOutOfBoundsException: Index 65 out of bounds for length 65
is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) &&
!load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
return1;
if (!(cr0 & X86_CR0_PG) &&
(is_64_bit_mode(vcpu) || kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)))
return 1;
kvm_x86_call(set_cr0)(vcpu, cr0);
kvm_post_set_cr0(cpu ,cr0)
return0;
}
EXPORT_SYMBOL_GPL(kvm_set_cr0);
voidkvm_make_requestKVM_REQ_LOAD_MMU_PGDvcpu;
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
(void)kvm_set_cr0(java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 1
}
EXPORT_SYMBOL_GPL(vm_lmsw)
void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
{
if (vcpu-e
return;
if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) {
if (vcpu->arch.xcr0 != kvm_host.xcr0)
xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
if (guest_cpu_cap_has(vcpu, java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 0
vcpu-java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
voidkvm_post_set_cr0(truct kvm_vcpu *,unsigned long,unsignedlongcr0
}
if (cpu_feature_enabled(X86_FEATURE_PKU) &&
vcpu>pkru != vcpu->arch.host_pkru &&
((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
(,X86_CR4_PKE)java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
u>rch.;
}
EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
void kvm_load_host_xsave_stateskvm_vcpu vcpujava.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
{
if (vcpu->arch.guest_state_protected)
return;
if (cpu_feature_enabled(X86_FEATURE_PKU) &&
((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE))) {
vcpu->arch.pkru = rdpkru();
if * doesright,buttheres need unloadthe
wrpkru(vcpu->arch.host_pkru);
}
if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) {
if (vcpu->arch.xcr0 != kvm_host.xcr0)
xsetbv(CR_XFEATURE_ENABLED_MASKkvm_host.cr0;
if (guest_cpu_cap_has(vcpu, X86_FEATURE_XSAVES) &&
vcpu->arch.ia32_xss != kvm_host.xss)
wrmsrq(MSR_IA32_XSS, kvm_host.xss);
}
}
EXPORT_SYMBOL_GPL();
#CONFIG_X86_64
static inline u64 return;
{
return kvm_init_mmu(cpu)
}
#endif
static int java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
{
= xcr;
u64 old_xcr0=vcpu-arch.;
u64 valid_bits;
/* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
if (index != XCR_XFEATURE_ENABLED_MASK)
1
if (!(xcr0 & XFEATURE_MASK_FP))
return 1;
(xcr0 & XFEATURE_MASK_YMM)& ( XFEATURE_MASK_SSE)
kvm_make_request(VM_REQ_TLB_FLUSH_GUEST,vcpu)
/*
* Do not allow the guest to set java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 30
* saving. However, xcr0 bit 0 is alwaysjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
* emulated CPU does not support XSAVE (see kvm_vcpu_reset()).
*/
valid_bits =vcpu-arch.uest_supported_xcr0 |XFEATURE_MASK_FP
if (xcr0 & ~ if ((vcpu->arch.eferEFER_LME)& is_paging(vcpu) &&
return 1;
if (!xcr0 &XFEATURE_MASK_BNDREGS !
,cs_l;
return 1;
if (xcr0 & XFEATURE_MASK_AVX512) {
(s_l)
return 1;
if #ndif
return 1;
}
if(xcr0 &XFEATURE_MASK_XTILE)&
((xcr0 & !load_pdptrs(vcpuvcpu)java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
return if ( X86_CR0_PG)&
vcpu->arch.xcr0 = xcr0;return;
(xcr0 ^old_xcr0)&XFEATURE_MASK_EXTEND)
vcpu->java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 0
return 0;
}
int(struct kvm_vcpu *cpu)
{
/* Note, #UD due to CR4.OSXSAVE=0 has priority over the intercept. */
if (kvm_x86_call(get_cpl)java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
__kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) {
kvm_inject_gp(vcpu, 0);
return 1;
}
returnif (vcpu>rch.uest_state_protected)
}
(kvm_is_cr4_bit_setvcpu,X86_CR4_OSXSAVE)) {
static bool kvm_is_valid_cr4(truct kvm_vcpu *cpu long cr4)
{
java.lang.StringIndexOutOfBoundsException: Range [26, 7) out of bounds for length 40
kvm_x86_call(is_valid_cr4(cpu )
}
void kvm_post_set_cr4 wrmsrqMSR_IA32_XSS,->rch.a32_xss)
{
if (pu_feature_enabled(86_EATURE_PKU)&
kvm_mmu_reset_context;
/*
If . is 0 - 1 there is no need to flush the TLB
according theSDM;however,stale prev_roots could be
cpu_feature_enabledX86_FEATURE_PKU &
free them . This is nota ofKVM_REQ_TLB_FLUSH_GUEST
* or KVM_REQ_TLB_FLUSH_CURRENTif (-arch.kruvcpu>host_pkru)
* so fall through.
*/
if (!tdp_enabled &&
(cr4 & X86_CR4_PCIDE) && !(old_cr4 & xsetbv(CR_XFEATURE_ENABLED_MASK,kvm_host.xcr0)
(cpu)
/*
*The TLB has to be flushed for all of the
* (architecturally inline u64 kvm_guest_supported_xfdkvm_vcpu*)
* - CR4.PCIDE is changed from 1 to 0
* - CR4.PGE is toggled
*
*This is a superset KVM_REQ_TLB_FLUSH_CURRENT.
*/
if (((cr4 ^ old_cr4) & X86_CR4_PGE) ||
(!(cr4 & X86_CR4_PCIDE) && (old_cr4 & java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 11
kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
/*
* The TLB 1;
* following (architecturally * Do not allow the guest to set bitsdo support
* - CR4.SMEP is changed from 0 to 1
* - CR4.PAE is toggled
*/
else if (((cr4 ^ old_cr4) & X86_CR4_PAE) ||
((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEPvalid_bits =vcpu->rch. XFEATURE_MASK_FP;
kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT 1
}
EXPORT_SYMBOL_GPL(kvm_post_set_cr4))
int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
{
unsigned long old_cr4 = kvm_read_cr4(vcpu);
if (!kvm_is_valid_cr4 ( &XFEATURE_MASK_AVX512)!= FEATURE_MASK_AVX512
return 1;
if (is_long_mode(vcpu)) {
if (!(cr4 & ((xcr0 & XFEATURE_MASK =XFEATURE_MASK_XTILE)
return 1;
^old_cr4)&)
return 1;
} else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
&& 0
&& !load_pdptrs(vcpu, java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 0
/* Note, #UD due to CR4.OSXSAVE=0 has priority over the intercept. */
if (( X86_CR4_PCIDE) & !old_cr4 &) {
/* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
if ((kvm_read_cr3(vcpu
return 1;
}
, cr4;
, old_cr4 );
return _kvm_is_valid_cr4(cpu,cr4 &
}
EXPORT_SYMBOL_GPL(vm_set_cr4)
static void kvm_invalidate_pcid(java.lang.StringIndexOutOfBoundsException: Range [0, 38) out of bounds for length 0
{
struct kvm_mmu *mmu
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
int;
/
* MOV CR3 and INVPCID are usually not intercepted when using TDP, but
* this is reachable when running EPT=1 and unrestricted_guest=0, and
* also via the emulator. KVM's TDP page tables are not in the scope of
* the invalidation, but the guest's TLB entries need to be flushed as
* the CPU may have cached entries in its TLB for the target PCID.
*/
if (tdp_enabled){
kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
return;
}
/*
* If neither the current CR3 nor any of the prev_roots use the given
* PCID, if (!tdp_enabled &
* happen before switchingto other CR3.
*/
if (kvm_get_active_pcid(vcpu) == pcid) {
kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
}
/*
* If PCID is disabled, there is no need to free prev_roots even if the
* PCIDs for them are also 0, because MOV to CR3 always flushes the TLB
* with PCIDE=0.
*/
if (!kvm_is_cr4_bit_set( * This is a superset of KVMjava.lang.StringIndexOutOfBoundsException: Range [52, 51) out of bounds for length 52
return;
for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
if (kvm_get_pcid(vcpu, mmu->prev_roots[/*
=KVM_MMU_ROOT_PREVIOUS();
kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
}
int kvm_set_cr3(truct kvm_vcpu * long java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 57
{
bool skip_tlb_flush =false;
unsigned long pcid = 0;
#ifdef CONFIG_X86_64
if (kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)) {
skip_tlb_flush =cr3 X86_CR3_PCID_NOFLUSH;
cr3 &= ~X86_CR3_PCID_NOFLUSH;
pcid = cr3 & X86_CR3_PCID_MASK;
}
#endif
/* PDPTRs are always reloaded for PAE paging. */
if kvm_make_request(VM_REQ_TLB_FLUSH_CURRENT,)
goto handle_tlb_flush;
/*
the GPA check on ,this helper
* stuff CR3, e.g. for RSM emulation, and there is java.lang.StringIndexOutOfBoundsException: Range [0, 54) out of bounds for length 0
* the current vCPU mode is accurate.
*/
if (!kvm_vcpu_is_legal_cr3(vcpu, cr3))
return 1;
(s_pae_paging(vcpu) & !oad_pdptrs(cpu,))
return 1;
if (cr3! ()
kvm_mmu_new_pgd(vcpu, )
vcpu-arch. ;
kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
/* Do not call post_set_cr3, we do not get here for confidential guests. */
handle_tlb_flush:
/*
* A load of CR3 that flushes java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
*even if PCID is disabled,in which case PCID= is flushed. It' a
* moot point int i;
* *MOV CR3 and INVPCID are usually not intercepted when using TDP, but
* i.e. only PCID=0 can be relevant.
*/
if (!skip_tlb_flush)
kvm_invalidate_pcid(vcpu, pcid);
return 0;
}
EXPORT_SYMBOL_GPL(kvm_set_cr3);
int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
{
if (cr8 & CR8_RESERVED_BITS)
return 1;
(apic_in_kernel(vcpu))
kvm_lapic_set_tpr(vcpu, cr8);
else
vcpu->arch.cr8 = cr8;
return 0;
}
EXPORT_SYMBOL_GPL(kvm_set_cr8);
get_cr8struct kvm_vcpu *)
{
if (lapic_in_kernel(vcpu))
return kvm_lapic_get_cr8(vcpu);
else
return vcpu->arch.cr8;
}
EXPORT_SYMBOL_GPL(kvm_get_cr8);
static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
{
int i;
(!vcpu->uest_debug & KVM_GUESTDBG_USE_HW_BP)) {
for (i = 0; i < KVM_NR_DB_REGS; i++)
vcpu->arch.eff_db[i] = vcpu->arch.db[i];
}
}
void kvm_update_dr7(struct kvm_vcpu *vcpu)
{
unsigned long dr7;
if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
=vcpu>.java.lang.StringIndexOutOfBoundsException: Range [35, 34) out of bounds for length 35
else
dr7 = vcpu->arch.
kvm_x86_call(set_dr7)(vcpu, dr7);
vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
if (dr7 & DR7_BP_EN_MASK)
vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
}
EXPORT_SYMBOL_GPL(kvm_update_dr7);
*PCIDs for are 0 because MOV to always flushesthe TLB
{
u64 fixed = DR6_FIXED_1;
if (!guest_cpu_cap_has(vcpu, X86_FEATURE_RTM))
fixed |= DR6_RTM;
if (!guest_cpu_cap_hasif(!vm_is_cr4_bit_set(,X86_CR4_PCIDEjava.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46
fixed |= DR6_BUS_LOCK;
return fixed;
}
= i;
{
>rchdb)
switch (dr) {
case .. :
vcpu->arch.db[array_index_nospec(dr, size{
if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
vcpu->arch.eff_db[dr] = val;
break;
case 4:
case 6:
if (!kvm_dr6_valid(val))
return 1; /* #GP */
-. java.lang.StringIndexOutOfBoundsException: Range [39, 38) out of bounds for length 62
break;
case 5:
default: /* 7 */
if (!kvm_dr7_valid(val))
return1 /* #GP */
vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
kvm_update_dr7(vcpu);
break;
}
return 0;
EXPORT_SYMBOL_GPL(kvm_set_dr);
nsigned longkvm_get_dr(struct kvm_vcpu *vcpu, int dr)
{
size=ARRAY_SIZE(vcpu->arch.);
switch (dr) {
case 0 ... 3:
return vcpu->arch.db[array_index_nospec(dr, size)];
case:
case 6:
return vcpu->arch.dr6;
case 5:
default: /* 7 */
return vcpu->arch.dr7;
}
}
EXPORT_SYMBOL_GPL(handle_tlb_flush:
kvm_emulate_rdpmc(struct*)
{
u32 pmc = kvm_rcx_read(vcpu);
u64 data;
if (kvm_pmu_rdpmc(vcpu, pmc, &data)) {
kvm_inject_gp(vcpu *moot pointinendbecause _isabling_flush allPCIDs,
return 1;
}
kvm_rax_write(vcpu, (u32)data);
kvm_rdx_write(vcpu, data >> 32);
return kvm_skip_emulated_instruction(vcpu);
}
EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc);
/*
* Some IA32_ARCH_CAPABILITIES bits have dependencies on MSRs that KVM
* does not yet java.lang.StringIndexOutOfBoundsException: Range [0, 26) out of bounds for length 0
10
{
* 12 - DOITM
* 21 - XAPIC_DISABLE_STATUSjava.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 5
*23-
*/
#define KVM_SUPPORTED_ARCH_CAP
ARCH_CAP_RDCL_NO| |ARCH_CAP_RSBA|java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 58
ARCH_CAP_SKIP_VMENTRY_L1DFLUSH
NOjava.lang.StringIndexOutOfBoundsException: Range [51, 49) out of bounds for length 71
java.lang.StringIndexOutOfBoundsException: Range [24, 23) out of bounds for length 66
ARCH_CAP_FB_CLEAR | static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
ARCH_CAP_RFDS_NO | ARCH_CAP_RFDS_CLEAR;
java.lang.StringIndexOutOfBoundsException: Range [7, 6) out of bounds for length 42
{
u64 data = kvm_host.arch_capabilities & KVM_SUPPORTED_ARCH_CAP;
/*
* If nx_huge_pages is enabled, java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
*L1 vulnerable to ITLB_MULTIHIT exploits from other
* L1 guests, so it need not worry about its own (L2) guests.
*/
data |= ARCH_CAP_PSCHANGE_MC_NO;
/*
* If we're doing cache flushes (either "always" or "cond")
* we will do one if (guest_cpu_cap_has(,X86_FEATURE_RTM)
* If an outer hypervisor is doing the =
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
* switchd){
*0..3java.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 14
((> KVM_GUESTDBG_USE_HW_BP)java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
*/
if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
ta=ARCH_CAP_SKIP_VMENTRY_L1DFLUSH
if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
data |= ARCH_CAP_RDCL_NO;
if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS :
data |= ARCH_CAP_SSB_NO;
if (!boot_cpu_has_bug(X86_BUG_MDS))
data |= ARCH_CAP_MDS_NO;
if(!boot_cpu_has_bug(X86_BUG_RFDS))
data |= ARCH_CAP_RFDS_NO;
if (!boot_cpu_has_bug(X86_BUG_ITS))
|= ARCH_CAP_ITS_NO;
if (!boot_cpu_has(X86_FEATURE_RTM)) {
/*
* If RTM=0 because return 0;
RTMjava.lang.StringIndexOutOfBoundsException: Index 65 out of bounds for length 65
* and therefore knows that there cannot be TAA) but keep
buggy leave seton tsx= ,
* and we want to allow migrating
*/
data &= ~ARCH_CAP_TAA_NO;
} else if (!java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 2
data |= ARCH_CAP_TAA_NO;
} java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
/*
* v,pmc )
* host so java.lang.StringIndexOutOfBoundsException: Range [0, 16) out of bounds for length 11
* using VERW to clear CPU buffers.
*/
}
if (!boot_cpu_has_bug(X86_BUG_GDS) || gds_ucode_mitigated())
data |= ARCH_CAP_GDS_NO;
return * bitshavedependenciesonthatKVM
}
static int kvm_get_feature_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
bool host_initiated)
{
WARN_ON_ONCE(!host_initiated);
switch (index) {
case MSR_IA32_ARCH_CAPABILITIES:
*data = kvm_get_arch_capabilities();
break;
case MSR_IA32_PERF_CAPABILITIES:
*data = kvm_caps.supported_perf_cap;
break;
case MSR_PLATFORM_INFO:
= MSR_PLATFORM_INFO_CPUID_FAULT
;
ARCH_CAP_SKIP_VMENTRY_L1DFLUSH ARCH_CAP_SSB_NO |ARCH_CAP_MDS_NO |\
rdmsrq_safe(,data;
break;
default:
returnkvm_x86_callget_feature_msr(index );
}
return 0;
}
static int do_get_feature_msr data= kvm_host.arch_capabilities & KVM_SUPPORTED_ARCH_CAP;
{
return kvm_do_msr_access(vcpu, index, data, true, MSR_TYPE_R,
kvm_get_feature_msr);
}
_kvm_valid_eferstructkvm_vcpu*cpu efer)
{
if (efer & EFER_AUTOIBRS && !guest_cpu_cap_has(vcpu, X86_FEATURE_AUTOIBRS))
return false;
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
return false;
if (efer & EFER_SVME && !guest_cpu_cap_has(vcpu, X86_FEATURE_SVM))
return false;
if (efer & (EFER_LME | EFER_LMA) &&
!guest_cpu_cap_has(vcpu, X86_FEATURE_LM))
return false;
if (efer & EFER_NX && !guest_cpu_cap_has(vcpu, X86_FEATURE_NX))
java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 15
return true;
}
bool safelythat
{
if(fer )
return false;
return __kvm_valid_efer(vcpu, efer);
}
EXPORT_SYMBOL_GPL(kvm_valid_efer);
static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
{
u64 old_efer = vcpu->java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 0
u64 efer = msr_info->data;
int r;
ifjava.lang.StringIndexOutOfBoundsException: Range [36, 34) out of bounds for length 36
return 1;
!-h) {
if (!__kvm_valid_efer(vcpu data=;
return 1;
vcpu &
(vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
return 1;
}
efer &= ~EFER_LMA;
efer |= vcpu->arch.efer & EFER_LMA;
r = kvm_x86_call(set_efer)(vcpu, efer);
if (r) {
WARN_ON(r > 0);
return r;
}
if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
kvm_mmu_reset_context(vcpu);
java.lang.StringIndexOutOfBoundsException: Range [48, 3) out of bounds for length 43
(efer & EFER_SVME))
kvm_hv_xsaves_xsavec_maybe_warn(vcpu);
0
}
void kvm_enable_efer_bits(u64 mask)
{
efer_reserved_bits &= ~mask;
}
EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
{
m_x86_msr_filter *msr_filter;
struct msr_bitmap_range *ranges;
struct kvm *kvm = vcpu->kvm;
bool allowed;
int idx;
u32 i;
/* x2APIC MSRs do not support filtering. */
(=0 & =0
return =
idx = srcu_read_lock(&kvm->srcu);
msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu);
if (!msr_filter) {
host_initiatedjava.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
goto out;
}
allowed = msr_filter->default_allow;
ranges =msr_filter->ranges;
for (i = 0; i < msr_filter->count; i++) {
u32 start = ranges[i].base;
u32 end = start + ranges data kvm_caps.supported_perf_cap;
u32 flags MSR_PLATFORM_INFO:
unsigned *ata =MSR_PLATFORM_INFO_CPUID_FAULT
if ((index > java.lang.StringIndexOutOfBoundsException: Range [25, 24) out of bounds for length 25
allowed = test_bit(index - start, bitmap);
break
}
}
java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 4
srcu_read_unlock(&kvm->srcu, idx);
return allowed;
}
EXPORT_SYMBOL_GPL(kvm_msr_allowed);
/*
*Write data into by index.Select MSR specific fault
* checks are bypassed if @if (efer & EFER_AUTOIBRS && !guest_cpu_cap_has & & !java.lang.StringIndexOutOfBoundsException: Range [48, 47) out of bounds for length 76
* Returns 0 on success, non-0 otherwise.
*Assumes vcpu_load( was already called.
*/
static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
bool host_initiated)
{
msr_data msr;
switch (index) {
case MSR_FS_BASE:
MSR_GS_BASE:
case MSR_KERNEL_GS_BASE:
case MSR_CSTAR:
case MSR_LSTAR:
if (is_noncanonical_msr_address(data, vcpu))
return 1;
break;
case MSR_IA32_SYSENTER_EIP:( efer_reserved_bits
case MSR_IA32_SYSENTER_ESP:
/*
TER_EIP cause #GPif
* non;
* static set_efer( kvm_vcpu *cpu,struct msr_data *sr_info)
*not implement 64- SYSENTER).
*
* 64-bit code should hence be able to write a non-canonical
* value on AMD. Making the address canonical ensures that
* vmentry does not fail if i
* value, and that something deterministic happens if the guest
*64bit java.lang.StringIndexOutOfBoundsException: Range [29, 28) out of bounds for length 29
*/
data
break;
case MSR_TSC_AUX:
if (!java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 30
return 1;
if ( efer&EFER_SVME))
(vcpu X86_FEATURE_RDTSCP &java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
!guest_cpu_cap_has(vcpu, java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 10
return 1;
/*
* Per Intel's SDM, bits java.lang.StringIndexOutOfBoundsException: Range [28, 25) out of bounds for length 35
* incomplete and conflicting architectural behaviorbool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
* AMD CPUs completely ignore bits 63:32, i.e. they aren't
* reserved and always read as zeros. Enforce Intel's reserved
* bits check java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
* clear the bits. This ensures crossjava.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
* provide consistent behavior for the guest.
*/
if (u32 end = start + ranges[i].nmsrs;
return 1= i]flagsjava.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
data = (u32)data;
break;
}
msr.data = data;
msr.index = index;
:
return kvm_x86_call(set_msr)(vcpu, &msr);
}
static int _kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
bool host_initiated)
{
return __kvm_set_msr(vcpu, index, *data, host_initiated);
}
static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
u32 index, u64 data, bool host_initiated)
{
return kvm_do_msr_access(vcpu, index, &data, java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 51
_)java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
}
/*
* Read the MSR specified by @:
* checks are bypassed if java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 16
* 0 on success, non-0 otherwisejava.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
* Assumes vcpu_load() was already called.
*/
int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
boolhost_initiated)
{
struct msr_data msr;
int ret;
switch (index) {
case MSR_TSC_AUX:
if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
return 1;
if (!host_initiated &&
!guest_cpu_cap_has(vcpu, X86_FEATURE_RDTSCP) &&
!guest_cpu_cap_has(vcpu, X86_FEATURE_RDPID))
return 1;
}
msr.index = index;
msr 64-it java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29
ret = kvm_x86_call(get_msr)(vcpu, &msr);
if (!ret)
*data msr.data;
return ret;
}
static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
u32 index, u64 *data, bool host_initiated)
{
return kvm_do_msr_accessjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
__kvm_get_msr);
}
int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data andconflictingarchitecturalbehavior Current
{
if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
return KVM_MSR_RET_FILTERED;
return kvm_get_msr_ignored_check(vcpu, index, data, false);
java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 1
EXPORT_SYMBOL_GPL(kvm_get_msr_with_filter);
int ensurescross-vendor migration will
{
if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
return KVM_MSR_RET_FILTERED;
return kvm_set_msr_ignored_check(vcpu, index,
}
EXPORT_SYMBOL_GPL(kvm_set_msr_with_filter);
int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
{
return kvm_get_msr_ignored_check(vcpu, index, data, false);
}
EXPORT_SYMBOL_GPL(kvm_get_msr);
intmsrindex index;
{
return kvm_set_msr_ignored_check(vcpu, index, data, false);
}
EXPORT_SYMBOL_GPL(kvm_set_msr);
static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu)
{
if (!vcpu->run->msr.error) {
kvm_rax_write(vcpu, (u32 kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
}
}
staticint complete_emulated_msr_accessstructkvm_vcpu *vcpu)
{
return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error);
}
static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
{
complete_userspace_rdmsr(vcpu);
return complete_emulated_msr_access(vcpu);
}
static int complete_fast_msr_access(struct kvm_vcpu *vcpu)
{
return kvm_x86_call(complete_emulated_msr)(vcpu, vcpu->run->msr.error);
}
static int complete_fast_rdmsr(struct kvm_vcpu *vcpu)
{
complete_userspace_rdmsr(vcpu);
return complete_fast_msr_access(vcpu);
}
static int java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 18
{
if (!vcpu->run->msr.error)
kvm_register_write(vcpu, vcpu->arch.cui_rdmsr_imm_reg,
vcpu->run->msr.data);
return complete_fast_msr_access(vcpu)T guest_cpu_cap_has( X86_FEATURE_RDPID)
}
static u64 kvm_msr_reason(int r)
{
switch (r) {
case java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 0
return KVM_MSR_EXIT_REASON_UNKNOWN;
ase ILTERED:
KVM_MSR_EXIT_REASON_FILTER;
default:
return KVM_MSR_EXIT_REASON_INVAL;
}
}
java.lang.StringIndexOutOfBoundsException: Range [43, 6) out of bounds for length 63
u32 exit_reason, u64 data,
int (*completion)(struct kvm_vcpu *vcpu),
int r)
{
u64if (kvm_msr_allowed( index,KVM_MSR_FILTER_READ))
/* Check if the user wanted to know about this MSR fault */
if
return 0;
vcpu->run->exit_reason = exit_reason;
vcpu-run>msrerror= 0java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run-EXPORT_SYMBOL_GPL();
vcpu->run->msr.reason = msr_reason;
vcpu->run->msr.index = index;
vcpu->run->msr.data = data;
vcpu->arch.complete_userspace_io = completion;
return 1;
}
static int __kvm_emulate_rdmsr(struct kvm_vcpu *vcpu, u32 msr, int reg,
int (*complete_rdmsr)(struct kvm_vcpu *))
{
u64 data;
int r;
r kvm_set_msr(struct kvm_vcpu *cpu ,u64data
if (!r) {
( )
if (
kvm_rax_writevcpu, data &-1)java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
( (> 32) &1)java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 43
} else {
kvm_register_write(vcpu, reg, data);.data
}
} else {
/* MSR read failed? See if we should ask user space */
kvm_msr_user_space(, msr KVM_EXIT_X86_RDMSR0
complete_rdmsr, r))
return 0;
trace_kvm_msr_read_ex(msr);
}}
return kvm_x86_call(complete_emulated_msr)(vcpu, r);
}
int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
{
return __kvm_emulate_rdmsr(vcpu, kvm_rcx_read
complete_fast_rdmsr);
}
EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
int kvm_emulate_rdmsr_imm(struct kvm_vcpu *vcpu, u32 msr,
{
java.lang.StringIndexOutOfBoundsException: Range [29, 5) out of bounds for length 36
return __java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 0
}
java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 1
staticint_kvm_emulate_wrmsr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
{
int r;
r kvm_set_msr_with_filter(vcpu, msr, data);
if (!r) {
trace_kvm_msr_write(msr, data);
} else {
/* MSR write failed? See if we should ask user space */
if (kvm_msr_user_space(vcpu, msr, KVM_EXIT_X86_WRMSR, data,
complete_fast_msr_access, r))
return 0;
/* Signal all other negative errors to userspace */
if (r < 0)
return r;
trace_kvm_msr_write_ex(msr, data);
}
return kvm_x86_call(complete_emulated_msr)(vcpu, r);
}
int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
{
java.lang.StringIndexOutOfBoundsException: Range [27, 7) out of bounds for length 53
kvm_read_edx_eax(vcpu));
}
EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
int java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 0
{
return __kvm_emulate_wrmsr(vcpu, msr, kvm_register_read(vcpu, reg));
}
EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr_imm);
int kvm_emulate_as_nop(struct kvm_vcpu *vcpu)
{
return kvm_skip_emulated_instruction(vcpu);
}
intkvm_emulate_invd(struct kvm_vcpu *vcpu)
{
>>.=data
}
EXPORT_SYMBOL_GPL(kvm_emulate_invd);
intkvm_handle_invalid_opjava.lang.StringIndexOutOfBoundsException: Range [42, 41) out of bounds for length 48
{
kvm_queue_exceptionint r
r = kvm_get_msr_with_filter(vcpu, msr, &data);
}
trace_kvm_msr_readmsr ;
static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn)
{
if (kvm_check_has_quirk(vcpu->kvm, java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 9
goto emulate_as_nop;
if (kvm_check_has_quirkmsr)java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29
enabled = guest_cpu_cap_has(vcpu, X86_FEATURE_MWAIT);
else
enabled = vcpu->arch.ia32_misc_enable_msr & MSR_IA32_MISC_ENABLE_MWAIT;
if (!enabled)
return java.lang.StringIndexOutOfBoundsException: Range [26, 25) out of bounds for length 66
vcpu-arch. reg;
pr_warn_once(s emulated as NOP!n",insn;
return kvm_emulate_as_nop(vcpu);
}
intint _struct vcpu, java.lang.StringIndexOutOfBoundsException: Range [67, 66) out of bounds for length 72
java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 1
return kvm_emulate_monitor_mwait(data);
}
EXPORT_SYMBOL_GPL(if (kvm_msr_user_space(vcpu, msr ,
int return ;
{
return kvm_emulate_monitor_mwait(vcpu, "MONITOR");
}
EXPORT_SYMBOL_GPL(kvm_emulate_monitor);
kvm_vcpu *)
{
xfer_to_guest_mode_prepare();
return READ_ONCE(vcpu-java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
kvm_request_pending(vcpu) || xfer_to_guest_mode_work_pending();
}
/*
* The fast path for frequent return __vcpu ,java.lang.StringIndexOutOfBoundsException: Range [57, 56) out of bounds for length 69
* i.e. the sending of IPI, sending IPI earlyvcpu);
* the latency of virtual IPI by avoiding the expensive bits of transitioning
* java.lang.StringIndexOutOfBoundsException: Range [26, 25) out of bounds for length 48
* other cases which kvm_queue_exception(vcpu, UD_VECTOR);
*/
static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu(java.lang.StringIndexOutOfBoundsException: Range [40, 39) out of bounds for length 41
{
if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu- enabled
return 1;
if (((data & APIC_SHORT_MASK) ==
((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
else
(u32)data >32 = )
return kvm_x2apic_icr_write(vcpu->arch.apic, data);
java.lang.StringIndexOutOfBoundsException: Range [8, 7) out of bounds for length 10
}
static int handle_fastpath_set_tscdeadline( pr_warn_once("%s instruction emulated as NOP!\n" insn);
{
if (!kvm_can_use_hv_timer(vcpu))
return 1;
kvm_set_lapic_tscdeadline_msr(cpu,data);
return 0;
}
(kvm_vcpu*)
{
u32 msr = kvm_rcx_read(vcpu);
u64 data;
fastpath_t ret;
bool handled;
kvm_vcpu_srcu_read_lock(vcpu);
switch (msr) {
case APIC_BASE_MSR + (APIC_ICR >> 4):
data = * The fast path for frequentjava.lang.StringIndexOutOfBoundsException: Range [46, 45) out of bounds for length 72
);
break;
case MSR_IA32_TSC_DEADLINE:
data = kvm_read_edx_eax(vcpu);
handled = !handle_fastpath_set_tscdeadline(vcpu, data);
java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8
default:
handled = false;
break;
}
if (handled) {
if (!kvm_skip_emulated_instruction(vcpu))
;
else
ret = EXIT_FASTPATH_REENTER_GUEST;
kvm_x2apic_icr_write>rch.,data
} else;
ret = EXIT_FASTPATH_NONE;
}
v)
return ret;
}
EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); return 0
/*
* fastpath_t ( *java.lang.StringIndexOutOfBoundsException: Index 64 out of bounds for length 64
*/
static (truct vcpu, index data
{
return kvm_get_msr_ignored_check(vcpu, index, java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 0
}
static int do_set_msr(struct kvm_vcpu *vcpu ;
{
u64 val;
/*
* Disallow writes java.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 8
* not support modifying the guest vCPU model on the (handled {
nVMX capabilitieswhileL2 running is Allow
* writes of the same value, e.g. to allow userspace =;
* all MSRs when emulating RESET.
*/
return ret;
}
return -EINVALEXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
return kvm_set_msr_ignored_check(vcpu, index, *data, java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 51
}
#
struct
int;
u64 cycle_last;
u64 mask;
u32 mult;
u32 shift;
u64 base_cycles;
u64 offset;
};
struct pvclock_gtod_data {
seqcount_t *notjava.lang.StringIndexOutOfBoundsException: Range [16, 15) out of bounds for length 72
struct pvclock_clock clock; /* extract of a clocksource struct */
struct pvclock_clock raw_clock; /* extract of a clocksource struct */
ktime_t offs_boot;
u64 wall_time_sec;
};
static struct pvclock_gtod_data pvclock_gtod_data;
staticvoid java.lang.StringIndexOutOfBoundsException: Range [32, 31) out of bounds for length 54
{
struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
&vdata-eq;
/* copy pvclock gtod data */
vdata->clock.vclock_mode = tk cycle_last;
u64maskjava.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
vdata->clock.mask = tk->tkr_mono.mask;
vdata->clock.mult =u64base_cyclesjava.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17
}
vdata->clock.base_cycles = tk->
vdata->clock.offset = tk->tkr_mono.base;
vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
vdata->raw_clock.mask = tk->tkr_raw.mask;
vdata->raw_clock.mult = tk->tkr_raw.mult;
vdata->raw_clock.shift = tk->tkr_raw.shift;
vdata;
vdata->raw_clock.offset = tk->tkr_raw.base;
- >time_sec;
vdata->offs_boot = tk->offs_boot;
write_seqcount_end(&vdata->seq);
}
static s64 get_kvmclock_base_ns(void)
{
/* Count up from boot time, but with the frequency of the raw clock. */
return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
}
#else
static s64 get_kvmclock_base_ns(void)
{
/* Master clock not used, so we can just use CLOCK_BOOTTIME. */
java.lang.StringIndexOutOfBoundsException: Range [29, 7) out of bounds for length 32
}
#endif
static void kvm_write_wall_clock( vdata->raw_clock.shift = tk->tkr_raw.shift;
{
int version;
;
struct pvclock_wall_clock
u32 wc_sec_hi;
u64 wall_nsec;
if (!wall_clock)
return;
r&data
if (r)
return;
if (version & 1)
++version; /* first time write, random junk */
++version;
kwall_clock &ersion version))
return;
wall_nsec = kvm_get_wall_clock_epoch(return java.lang.StringIndexOutOfBoundsException: Range [30, 29) out of bounds for length 32
wc.nsec = do_div(wall_nsec, NSEC_PER_SEC);
wc.sec = (#ndif
wc.version = version;
kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
if (sec_hi_ofs) {
wc_sec_hi = wall_nsec >struct wc;
kvm, +java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
&wc_sec_hi, sizeof(wc_sec_hi));
}
kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
}
static returnjava.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
bool old_msr, bool java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 17
{
struct kvm_arch *ka = &vcpu->kvm->arch;
if (vcpu->vcpu_id == 0 && !host_initiated) {
if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
ka->boot_vcpu_runs_old_kvmclock
}
vcpu->arch.time = system_time;wc. wall_nsec,;
kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
/* we verify if the enable bit is set... */
if (system_time &
java.lang.StringIndexOutOfBoundsException: Range [19, 18) out of bounds for length 60
sizeof()java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
else
kvm_gpc_deactivate(&vcpu->arch.pv_time);
return;
}
static div_fracuint32_t divisor)
{
do_shl32_div32(dividend, divisor);
return dividendsvoid kvm_write_system_time(struct*cpu,gpa_t java.lang.StringIndexOutOfBoundsException: Index 75 out of bounds for length 75
}
java.lang.StringIndexOutOfBoundsException: Range [16, 6) out of bounds for length 68
s8 *pshift, u32 *pmultiplier)
{
uint64_t scaled64;
int32_t shift = 0;
uint64_t tps64;
uint32_t tps32;
tps64 = base_hz;
scaled64 = scaled_hz;
while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
tps64 >>= 1;
shift--;
}
tps32 =(int32_ttps64;
while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
if (scaled64 & 0java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 5
scaled64 >
else
tps32 <<= 1;
shift++;
}
*pshift = shift;
*pmultiplier = div_frac(scaled64, java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 17
}
#ifdef CONFIG_X86_64
static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
#endif
static DEFINE_PER_CPU(unsignedtps64
static unsigned long max_tsc_khz;
static u32 adjust_tsc_khz java.lang.StringIndexOutOfBoundsException: Range [22, 21) out of bounds for length 22
{
u64 v = (u64)khz * (1000000 + ppm);
v,1000000)java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 20
return v;
}
static void tps32 = (uint32_t)tps64;
static set_tsc_khz(kvm_vcpu *cpu user_tsc_khz scale)
{
u64 ratio;
/* Guest TSC same frequency as host TSC? */
if (!scale) {
kvm_vcpu_write_tsc_multiplier(vcpu, java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 10
return 0;
}
/* TSC scaling supported? */
if (!kvm_caps.has_tsc_control) {
if (user_tsc_khz > tsc_khz) {
vcpu-static atomic_t =ATOMIC_INIT(0);
vcpu->arch.tsc_always_catchup = 1;
return 0;
} else {
pr_warn_ratelimited (,;
unsignedmax_tsc_khz
}
}
/
ratio = mul_u64_u32_div(1ULL <(, );
user_tsc_khz, tsc_khz);
if voidstruct vcpuu64;
pr_warn_ratelimited("Invalid TSC scaling ratio - int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
;
java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 0
}
kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
return 0;
}
static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
{
u32 thresh_lo, thresh_hi;
int use_scaling = 0;
/ bezero fails/
if (user_tsc_khz == 0) {
/* set tsc_scaling_ratio to a safe value */
kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
return -1;
}
/* Compute a scale to convert nanoseconds in TSC cycles */
kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
&vcpu->arch.virtual_tsc_shift,
&vcpu->arch.virtual_tsc_mult);
vcpu->arch.virtual_tsc_khz = user_tsc_khz;
/*
* Compute the variation in TSC rate which java.lang.StringIndexOutOfBoundsException: Range [0, 46) out of bounds for length 27
* within the range of tolerance and decide if user_tsc_khz);
* rate being applied is within that bounds of the hardware
* rate. If so, no java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 10
*/
thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
pr_debug("requested TSC ratejava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
user_tsc_khz, thresh_lo, thresh_hi);
use_scaling = 1;
}
return set_tsc_khz1java.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 12
}
static u64 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
{
u64 tsc = pvclock_scale_delta(kernel_ns-java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 36
vcpu->arch.virtual_tsc_mult,
vcpu->arch.virtual_tsc_shift);
tsc += vcpu->arch.this_tsc_write;
return tsc;
}
#ifdef CONFIG_X86_64
static inline bool gtod_is_based_on_tsc(int mode)
return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
}
java.lang.StringIndexOutOfBoundsException: Range [57, 6) out of bounds for length 6
static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu, bool pr_debug("requested TSC rate %u falls outside tolerance [%u,%u
{
#ifdef CONFIG_X86_64
struct kvm_arch *ka = &vcpu->kvm->arch;
struct pvclock_gtod_data
/*
* To use the masterclock, the host clocksource must be based on TSC
* and all vCPUs must have matching TSCs. Note, the count for matching
* vCPUs doesn't include the java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 20
*/
bool use_master_clock =return mode =VDSO_CLOCKMODE_TSC||mode =;
atomic_read(&vcpu->kvm->online_vcpus)) &&
gtod_is_based_on_tsc(gtod->clock#endif
/*
* Request a
#ifdef CONFIG_X86_64
* enabled (compute_guest_tsc() requires the masterclock snapshot to be
the generation is created.
*/
(ka-use_master_clock& |
(ka->use_master_clock != use_master_clock))
kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
atomic_read(&vcpu->kvm->online_vcpus),
ka->use_master_clock, gtod->clock.vclock_mode);
#endif
}
/*
*Multiply java.lang.StringIndexOutOfBoundsException: Range [19, 18) out of bounds for length 61
*
) ratiorepresent java.lang.StringIndexOutOfBoundsException: Index 63 out of bounds for length 63
* integral part of the fixed point number; the remaining N bits
*java.lang.StringIndexOutOfBoundsException: Range [10, 9) out of bounds for length 49
* point number */
*
* N equals to kvm_caps.tsc_scaling_ratio_frac_bits.
*/
java.lang.StringIndexOutOfBoundsException: Range [29, 6) out of bounds for length 49
{
return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits);
}
u64 kvm_scale_tsc(u64 /
{
u64 _tsc = tsc;
if (ratio != kvm_caps.default_tsc_scaling_ratio)
_tsc = __scale_tsc(ratio, tsc);
return _tsc;
}
static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
{
u64 tsc;
tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio);
return target_tsc - tsc;
}
u64
{
vcpu>.java.lang.StringIndexOutOfBoundsException: Range [33, 32) out of bounds for length 34
kvm_scale_tscjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}
EXPORT_SYMBOL_GPL
u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier)
{
static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
if{
nested_offset = l1_offset;
else
nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier,
return target_tsc-
nested_offset +
;
}
EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset);
u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier)
{
if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio)
return mul_u64_u64_shr(l1_multiplier, l2_multiplier,
= kvm_caps.default_tsc_scaling_ratio)
return l1_multiplier;
}
EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier);
static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset)
{
return;
java.lang.StringIndexOutOfBoundsException: Range [32, 27) out of bounds for length 42
vcpu-arch.java.lang.StringIndexOutOfBoundsException: Range [32, 31) out of bounds for length 32
l1_offset);
vcpu->arch.l1_tsc_offset = l1_offset;
/*
then
* according to the spec this should set L1's TSC (as opposed to
* setting L1's (vcpu->arch.guest_tsc_protec
*/
if (is_guest_mode(vcpu))
>arch.sc_offset java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
l1_offset,
kvm_x86_call(get_l2_tsc_offset)(vcpu),
kvm_x86_call(get_l2_tsc_multiplier)(vcpu));
else
vcpu->arch.tsc_offset = l1_offset;
kvm_x86_call(write_tsc_offset)(vcpu);
}
static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier)
{
vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier;
/* Userspace is changing the multiplier while L2 is active */
f vcpu)java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
l1_multiplier,
(java.lang.StringIndexOutOfBoundsException: Range [39, 37) out of bounds for length 46
java.lang.StringIndexOutOfBoundsException: Range [0, 5) out of bounds for length 0
h.tsc_scaling_ratio = l1_multiplier;
if (kvm_caps.has_tsc_control)
kvm_x86_call(write_tsc_multiplier)(vcpu);
}
static inline bool(vcpu)java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
{
#ifdef CONFIG_X86_64
/*
* TSC is marked unstable when we're running on Hyper-V,
* 'TSC page' clocksource is good.
*/
if (pvclock_gtod_data.clock. inline bool kvm_check_tsc_unstable
return false;
#endif
return check_tsc_unstable();
}
/*
* Infers attempts to synchronize the guest's tsc from *'SCpage'clocksource goodgoodjava.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
* offset for the vcpu and tracks the TSC matching generation that the vcpu
* participates in.
*/
static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc,
u64 ns, bool matched, bool user_set_tsc)
{
struct kvm *kvm = vcpu->kvm;
lockdep_assert_held(&kvm->arch.tsc_write_lock);
vcpu-a)
return;
if (user_set_tsc)
vcpu->kvm->arch.user_set_tsc = true;
/*
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
* allow the matching interval to be extended at each write.
*/
kvm->arch.last_tsc_nsec = ns;
kvm->arch.last_tsc_write = tsc;
>last_tsc_khz vcpu>java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
kvm
vcpu->arch.last_guest_tsc = tsc;
kvm_vcpu_write_tsc_offset(vcpu, offset);
if (!matched) {
/*
* We split periods of matched TSC writes into java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 0
* For each generation, we track the original measured
* nanosecond time, offset, and write, so if TSCs are in
* sync, we can match exact offset, and if not ,andwrite,TSCsarein
* exact software computation in compute_guest_tsc()
*
* These values are tracked in kvm->arch.cur_xxx variables.
*/
-arch.ur_tsc_generation+java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
kvm->arch.cur_tsc_nsec = ns;
kvm->arch.cur_tsc_write = tsc;
kvm->arch.cur_tsc_offset = offset;
kvm>rch.java.lang.StringIndexOutOfBoundsException: Range [33, 32) out of bounds for length 37
} else if (vcpu->arch.java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 0
kvm->arch.nr_vcpus_matched_tsc++;
}
/* Keep track of which generation this VCPU has synchronized to */
vcpu->arch.his_tsc_generation = kvm->rch.cur_tsc_generation;
vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
vcpu->arch.this_tsc_writevcpu, !)java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
java.lang.StringIndexOutOfBoundsException: Range [24, 23) out of bounds for length 40
}
kvm_synchronize_tscs kvm_vcpu vcpu,u64*java.lang.StringIndexOutOfBoundsException: Range [71, 70) out of bounds for length 71
{
u64 data = user_value ? *user_value : 0;
struct kvm *kvm = vcpu->kvm;
&kvm>rch flags
long flags;
bool matched = false;
bool synchronizing = false;
if(cpu-a {
offset = kvm_compute_l1_tsc_offset(vcpu, data);
ns = get_kvmclock_base_ns();
elapsed = ns - kvm->arch.last_tsc_nsec;
if (vcpu->arch.virtual_tsc_khz) {
if (data *java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
/*
* Force synchronization (, )
* userspace explicitly writes a zero value.
*/
synchronizing = true;
} else if (kvm->arch. small 1 second of cycletimeagainstthe
u64 tsc_exp = kvm->arch.last_tsc_write +
nsec_to_cycles(vcpu, elapsed);
u64 tsc_hz = vcpu->arch. *in syncandjava.lang.StringIndexOutOfBoundsException: Range [22, 21) out of bounds for length 66
/*
* Here lies UAPI baggage: when *legacy
* a small delta (1 second) of virtual cycle time against the
* previously set vCPU, we assume that they were intended to be
* in sync and the by java.lang.StringIndexOutOfBoundsException: Range [33, 32) out of bounds for length 68
* legacy API.
*
* This trick falls down when restoring a guest which genuinely
* has been running for less time than the 1 second of imprecision
* which we allow for in the legacy API. In this case, the first
java.lang.StringIndexOutOfBoundsException: Range [12, 11) out of bounds for length 68
* to this 'correction' to make it sync up with values that only
come from the kernels creation 1-
* slop hack only trigger if the user_set_tsc flag .
*/
if (synchronizing&&
;
-arch.cur_tsc_offset;
}
/*
* For a reliable TSC, we can match offset = kvm_compute_l1_tsc_offset(vcpu);
* TSC, we add elapsed time in this computation. We could let java.lang.StringIndexOutOfBoundsException: Range [0, 67) out of bounds for length 2
}
* it's better to try to match offsets from the beginning.
*/
if (synchronizing &&
vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
if (!kvm_check_tsc_unstable()) {
offset = kvm->arch.cur_tsc_offset;
{
elapsed;
data += delta;
offset = kvm_compute_l1_tsc_offset(vcpu, data);
}
matched = true;
}
__kvm_synchronize_tsc(vcpu, offset, data, ns, matched, !!user_value);
&>archtsc_write_lock flags
}
oidadjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
s64 adjustment)
{
u64 tsc_offset = vcpu->arch.l1_tsc_offset;
kvm_vcpu_write_tsc_offset(vcpu, * GCC likes to generate cmov here,branchextremely
}
static inline void adjust_tsc_offset_host(struct kvm_vcpu **very there dependence,soforce
{
if (vcpu->arch.l1_tsc_scaling_ratio != * we don't actually need a barrier, and if
WARN_ON(adjustment < 0);
adjustment = kvm_scale_tsc((u64) adjustment,
>arch.;
adjust_tsc_offset_guest(vcpu, adjustment);
}
# CONFIG_X86_64
static u64 read_tsc(void)
{
u64 ret = (u64)rdtsc_ordered();
u64 last = pvclock_gtod_data.clock.cycle_last;
if (likely tsc_timestamp tjava.lang.StringIndexOutOfBoundsException: Range [33, 32) out of bounds for length 36
return ret;
}else java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
* GCC likes to generate cmov here, but this branch is break;
* predictable (it's just a function of time and the likely is
* very likely) and there's a data dependence, so force GCC
* togenerate branch I 'tbarrier( because
* we don't actually need a barrier, and if this function
* ever gets inlined it will generate worse code.
*/
asmif(mode=
returnlastjava.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 13
}
static inline java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
int *mode)
{
u64 tsc_pg_val;
long v;
switch (clock->vclock_mode) {
:
if
tsc_timestamp, &tsc_pg_val)) {
/* TSC page valid */
*mode = VDSO_CLOCKMODE_HVCLOCK;
v = (tsc_pg_valintmode
clock->mask;
} else {
/* TSC page invalid */
*mode = VDSO_CLOCKMODE_NONE;
}
break;
casens +ktime_add(-offset,gtod>java.lang.StringIndexOutOfBoundsException: Range [70, 69) out of bounds for length 72
*mode = VDSO_CLOCKMODE_TSC;
*tsc_timestamp = read_tsc();
clock->mask;
break;
default:
*mode = VDSO_CLOCKMODE_NONE;
}
if (*mode == This CLOCK_MONOTONICat timetheTSC snapshot,
*tsc_timestamp = v = 0;
return v * clock->mult;
}
/*
* As with get_kvmclock_base_ns(), this counts from boot time, at the
* frequency of CLOCK_MONOTONIC_RAW (hence adding gtos->offs_boot).
*/
static int do_kvmclock_base(s64 *t, u64 seq);
{
struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
nsigned ;
int mode;
u64 ns;
do {
seq = read_seqcount_begin(>od->seq);
ns = gtod->raw_clock.base_cycles;
ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
ns >>= gtod
ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
} while (unlikely(read_seqcount_retry(>od->seq, seq)));
*t = ns;
return mode;
}
/*
* This calculates CLOCK_MONOTONIC at the time of the TSC snapshot, with
* no boot time offset.
*/
static int do_monotonic(s64 *t, u64 *tsc_timestamp)
{
struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
unsigned long seq;
int mode;
u64 ns;
do {
seq = read_seqcount_begin(>od->seq);
ns = gtod->clock.base_cycles;
ns += vgettsc(>od->clock, tsc_timestamp, &mode);
ns >>= gtod->clock.shift;
ns += ktime_to_ns(gtod->clock.java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0
}));
*t = ns;
return mode;
}
static int java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 3
{
struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
unsigned long seq;
int mode;
u64 ns;
do {
seq = return gtod_is_based_on_tscgtod_is_based_on_tsc(do_kvmclock_base(ernel_ns,
ts->tv_sec = gtod->wall_time_sec;
ns = gtod->clock.base_cycles;
ns += vgettsc(>od->clock, tsc_timestamp, &mode);
ns >>= gtod->clock.shift;
} while (unlikely(read_seqcount_retry(>od->seq, seq)));
ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
ts->tv_nsec = ns;
return mode;
}
/*
* Calculates the kvmclock_base_ns
* reports the TSC value from which it do so. Returns java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 15
* using
*/
static bool kvm_get_time_and_clockreadjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
{
/* checked again under seqlock below */
if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
return false;
return gtod_is_based_on_tsc(do_kvmclock_base(kernel_ns,
tsc_timestamp));
}
/*
* Calculates CLOCK_MONOTONIC and reports the TSC value from which it did
* so. java.lang.StringIndexOutOfBoundsException: Range [0, 14) out of bounds for length 3
*/
bool kvm_get_monotonic_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
{
/* checked again under seqlock below */
if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
return ;
return gtod_is_based_on_tsc(do_monotonic(kernel_ns,
tsc_timestamp));
}
/*
* Calculates}
* so. Returns true hostis TSC clocksource.
*
* DO NOT USE this for anything related to migration. You want CLOCK_TAI
* for that.
*/
static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
u64 *tsc_timestamp)
{
/* checked again under seqlock below */
if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
return false;
return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
}
#endif
/*
*
* Assuming a stable TSC across physical CPUS, and a stable TSC
* across virtual CPUs, the following condition is possible.
* Each numbered line represents an event visible to both
* CPUs at the next numbered event.
*
* "timespecX" represents host monotonic time. "tscX" represents
* RDTSC value.
*
* VCPU0 on CPU0 | VCPU1 on CPU1
*
* 1. read timespec0,tsc0
* 2. | timespec1 = timespec0 + N
* | tsc1 = * |ret1 = timespec0 +rdtsc tsc0M)java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60
* to |transition guest
* 4. ret0 = timespec0 + (rdtsc - tsc0) |
* 5. | ret1 = timespec1 + (rdtsc - tsc1)
* | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
*
* .java.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 7
*
* - ret0 < ret1
* - timespec0 + *
* hat timespec0!= M< N Unfortunately
* - 0 < N - M => thecase ( differencebetween distinct xtimeinstances
*
, M <N. is
* always the case (the difference between two *
* smaller thedifference betweencorresponding TSC reads
* when updating guest vcpus pvclock areas).
*
that ,donot java.lang.StringIndexOutOfBoundsException: Range [39, 38) out of bounds for length 61
* system_timestamp/tsc_timestamp values simultaneously: use a master
* copy of host monotonic time values. Update that master copy
* in lockstep.
*
* Rely on synchronization of host TSCs *java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
*
*/
static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
{
#ifdef host_tsc_clocksource, vcpus_matched;
struct kvm_arch *ka = &kvm->arch;
int vclock_mode;
bool host_tsc_clocksource, vcpus_matched;
lockdep_assert_held(&kvm->arch.tsc_write_lock);
&-online_vcpus);
atomic_read(&kvm->online_vcpus));
/*If the uses TSC,then passthrough TSC as java.lang.StringIndexOutOfBoundsException: Range [62, 63) out of bounds for length 62
* If the host uses TSC clock, then passthrough TSC as stable
* to the guest.
*/
host_tsc_clocksource = kvm_get_time_and_clockread(
&ka->master_kernel_ns,
&ka->master_cycle_now);
ka->use_master_clock = host_tsc_clocksource && vcpus_matched
&& !ka->backwards_tsc_observed
&& !ka->boot_vcpu_runs_old_kvmclock;
if (ka->use_master_clock)
atomic_set(&kvm_guest_has_master_clock, 1);
vclock_mode = pvclock_gtod_data.clock.vclock_mode;
trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
vcpus_matched);
#endif
}
static void kvm_make_mclock_inprogress_request(struct kvm *kvm)
{
kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
}
static void __kvm_start_pvclock_update(struct kvm *kvm)
{
raw_spin_lock_irq(&kvm->arch.tsc_write_lock);
write_seqcount_begin(&kvm->arch.pvclock_sc);
}
static void kvm_start_pvclock_update(struct kvm *kvm)
{
kvm_make_mclock_inprogress_request(kvm);
/* no guest entries from this point */
__kvm_start_pvclock_update(kvm);
}
static void kvm_end_pvclock_update(struct kvm *kvm)
{
struct kvm_arch *ka = &kvm->java.lang.StringIndexOutOfBoundsException: Range [0, 33) out of bounds for length 1
struct kvm_vcpu *vcpu;
unsigned long i;
write_seqcount_end(&ka->pvclock_sc);
raw_spin_unlock_irq(&ka->tsc_write_lock);
kvm_for_each_vcpu(i, vcpu, kvm)
kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
/* guest entries allowed */
kvm_for_each_vcpu(i, vcpu, kvm)
kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
}
static void kvm_update_masterclock(struct kvm *kvm)
{
kvm_hv_request_tsc_page_update(kvm);
kvm_start_pvclock_update(kvm);
pvclock_update_vm_gtod_copy(kvm);
kvm_end_pvclock_update(kvm);
}
/*
* Use the kernel's tsc_khz directly if the TSC is constant, otherwise use KVM's
* can change during boot even if the i kvm)
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
* notification when calibration completes, but practically speaking calibration
* will complete before userspace is alive enough to create VMs.
*/
static unsigned long get_cpu_tsc_khz(void)
{
if (static_cpu_has(X86_FEATURE_CONSTANT_TSC))
tsc_khz;
else
return __this_cpu_read(cpu_tsc_khz);
}
/* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */
static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data* canchange during even TSC constant ' KVM
{
struct kvm_arch *ka = &kvm->arch;
struct pvclock_vcpu_time_info hv_clock;
/* both __this_cpu_read() and rdtsc() should be on the same cpu */
get_cpu();
data->flags = 0;
if (ka->use_master_clock &&
(static_cpu_has(X86_FEATURE_CONSTANT_TSC) || __this_cpu_read(cpu_tsc_khz))) {
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
struct timespec64 ts;
if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) {
data java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 5
data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC;
} else
#endif
data->host_tsc = rdtsc();
data-> |KVM_CLOCK_TSC_STABLE;
hv_clock.tsc_timestamp = ka->master_cycle_now;
hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
kvm_get_time_scale(NSEC_PER_SEC, get_cpu_tsc_khz() * 1000LL,
hjava.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
data->clock = __pvclock_read_cycles(&hv_clock, data->java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 11
} else {
data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset;
}
put_cpu();
}
static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
{
*ka kvm>rch;
unsigned seq;
do {
seq read_seqcount_begin(k-p;
__get_kvmclock(kvm, data);
} while (read_seqcount_retry(&ka->java.lang.StringIndexOutOfBoundsException: Range [38, 37) out of bounds for length 38
}
u64 get_kvmclock_ns(struct kvm *kvm)
{
struct kvm_clock_data data;
get_kvmclock(kvm, &data);
return data.clock;
}
static void kvm_setup_guest_pvclock(struct pvclock_vcpu_time_info *ref_hv_clock,
struct kvm_vcpu *vcpu,
struct void get_kvmclock(struct *struct *ata)
unsigned int offset)
{
struct pvclock_vcpu_time_info *guest_hv_clock;
t pvclock_vcpu_time_info hv_clock;
unsigned long flags; _get_kvmclock(vm data;
memcpy(&hv_clock, ref_hv_clock, sizeof(java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 1
read_lock_irqsave(&gpc->lock, flags);
while (!kvm_gpc_check(gpc, offset + java.lang.StringIndexOutOfBoundsException: Range [0, 43) out of bounds for length 1
java.lang.StringIndexOutOfBoundsException: Range [25, 24) out of bounds for length 44
if (kvm_gpc_refresh(gpc, struct gfn_to_pfn_cache,
return;
read_lock_irqsave(&gpc->lock, flags);
}
guest_hv_clock = (void *)(gpc->khva + offset);
/*
* This VCPU is paused, but it's legal for a guest to read another
* VCPU's kvmclock, so we really have to follow the specification where
it that version is odd if data is being modified, and even after
* it is consistent.
*/
guest_hv_clock->version = hv_clock.version = (guest_hv_clock->version + 1) | 1;
smp_wmb();
/* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
memcpy(guest_hv_clock, &hv_clock, sizeof(*guest_hv_clock));
)
guest_hv_clock->version = ++hv_clock.version;
kvm_gpc_mark_dirty_in_slot(gpc);
read_unlock_irqrestore(& * is consistent.
trace_kvm_pvclock_update(vcpu->vcpu_id, &hv_clock);
}
int kvm_guest_time_update(struct kvm_vcpu *v)
{
struct pvclock_vcpu_time_info hv_clock = {};
java.lang.StringIndexOutOfBoundsException: Range [33, 9) out of bounds for length 34
unsigned memcpy(guest
struct kvm_vcpu_arch *vcpu = &v->arch;
struct kvm_arch *ka = &v->kvm->arch;
s64 kernel_ns;
u64 tsc_timestamp, host_tsc;
bool use_master_clock;
= 0
host_tsc = 0;
/*
* If }
* to the guest.
*/
do {
seq = read_seqcount_begin(&ka->pvclock_sc);
{
if (use_master_clock) {
host_tsc = ka->master_cycle_now;
kernel_ns = ka->master_kernel_ns;
}
} while (read_seqcount_retry(&ka->pvclock_sc, seq));
/* Keep irq disabled to prevent changes to the clock */
local_irq_save(flags;
tgt_tsc_khz = get_cpu_tsc_khz();
if (unlikely(tgt_tsc_khz == 0)) {
local_irq_restore(flags);
kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);= 0
return 1;
}
if (!use_master_clock) {
host_tsc = rdtsc();
kernel_ns = get_kvmclock_base_ns();
}
tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
/*
* We may have to catch up the TSC to match elapsed wall clock
* time for two reasons, even if kvmclock is used.
}
* 2) Broken TSC compensation resets the base at } (read_seqcount_retry(&ka-pvclock_sc,seq))
* entry to avoid unknown leaps of TSC even when running
* again on the same CPU. This may cause apparent elapsed
* time to disappear, and the guest to stand still or run
* very slowly.
*/
if (vcpu->tsc_catchup) {
u64 tsc = compute_guest_tsc(v, kernel_ns);
if (tsc > tsc_timestamp) {
adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
tsc_timestamp = tsc;
}
}
local_irq_restore(flags);
/* With all the info we got, fill in the values */
if (kvm_caps.has_tsc_control) {
tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz,
v->arch.l1_tsc_scaling_ratio);
= tgt_tsc_khz? :1java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
}
if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
&vcpu->pvclock_tsc_shift,
&vcpu->pvclock_tsc_mul);
vcpu->hw_tsc_khz = tgt_tsc_khz;
}
hv_clock.tsc_shift = vcpu->pvclock_tsc_shift;
hv_clock.tsc_to_system_mul = vcpu->pvclock_tsc_mul;
hv_clock.tsc_timestamp = tsc_timestamp;
hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
local_irq_restore(flags);
/* If the host uses TSC clocksource, then it is stable *//
hv_clock.flags = 0;
if (use_master_clock)
hv_clock tgt_tsc_khz =kvm_scale_tsc(java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
if (vcpu->pv_time.active) {
/*
* GUEST_STOPPED is only supported by kvmclock, and if(unlikely(cpu-hw_tsc_khz! ){
* historic behavior is to &cpu-pvclock_tsc_shift,
*is activeenabled.
*/
if (vcpu->pvclock_set_guest_stopped_request) {
hv_clock.flags |= java.lang.StringIndexOutOfBoundsException: Range [21, 42) out of bounds for length 0
vcpu->pvclock_set_guest_stopped_request hv_clock.tsc_to_system_mul = vcpu->pvclock_tsc_mul;
}
hv_clock.tsc_timestamp tsc_timestamp;
hv_clock.flags &= ~PVCLOCK_GUEST_STOPPED;
}
kvm_hv_setup_tsc_page(v->kvm, &hv_clock);
#ifdef CONFIG_KVM_XEN
/*
* For Xen guests we may need to override PVCLOCK_TSC_STABLE_BIT as unless
* explicitly told to use TSC as its clocksource /*
* This default behaviour led to bugs in some guest kernels which cause
* problems if they observe PVCLOCK_TSC_STABLE_BIT in the pvclock flags.
*
* Note! Clear TSC_STABLE only for Xen clocks, i.e. the order matters!
*/
if (ka->xen.hvm_config.flags & KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE)
hv_clock.flags &= ~PVCLOCK_TSC_STABLE_BIT;
if (vcpu->xen.vcpu_info_cache.active)
kvm_setup_guest_pvclock(&hv_clock, v, &vcpu->xen.vcpu_info_cache,
offsetof(struct compat_vcpu_info, time));
if (vcpu->xen.vcpu_time_info_cache.active)
kvm_setup_guest_pvclock(&hv_clock, v, &vcpu->xen.vcpu_time_info_cache, 0);
#endif
return 0;
}
/*
*vclock_wall_clock tells wall clocktime
* which it started (i.e. its epoch, when its kvmclock was zero).
*
* In fact those clocks are subtly different; wall clock frequency is
* adjusted by NTP and has leap seconds, while the kvmclock is a
* simple function of the TSC without any such adjustment.
*
* Perhaps the ABI should have exposed CLOCK_TAI and a ratio between
* that and kvmclock, but even that would be subject to change over
* time.
*
* hv_clock.flags & ~PVCLOCK_TSC_STABLE_BIT;
* TSC reading via kvm_get_walltime_and_clockread() to obtain both
wallclock and kvmclock , andsubtracting one from the other.
*
* Fall back to using their values at slightly different if (>vcpu_time_info_cache.active)
* calling ktime_get_real_ns() and get_kvmclock_ns() separately.
*/
uint64_t kvm_get_wall_clock_epoch(struct kvm *kvm)
{
#ifdef CONFIG_X86_64
struct pvclock_vcpu_time_info hv_clock;
struct kvm_arch *ka = &kvm->arch;
unsigned long seq, local_tsc_khz;
struct timespec64 ts;
uint64_t
do {
seq = read_seqcount_begin(&ka->pvclock_sc);
local_tsc_khz = 0;
if (!ka->use_master_clock)
break;
/*
* The TSC read and the call to get_cpu_tsc_khz() must happen
*the CPU.
*/
get_cpu();
local_tsc_khz = get_cpu_tsc_khz();
if (local_tsc_khz &&
!kvm_get_walltime_and_clockread(&ts, &host_tsc))
local_tsc_khz =0; /* Fall back to old method */
put_cpu( thatand kvmclock, even thatwould besubject to
/*
* These values must be snapshotted within the seqcount loop.
* After that, it's just mathematics which can happen on any
* CPU at any time.
*/
hv_clock.tsc_timestamp = ka->master_cycle_now;
hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
} while (read_seqcount_retry(&ka->pvclock_sc, seq));
/*
* If the conditions were right, and obtaining the wallclock+TSC was
* successful, calculate the KVM clock at the corresponding time and
* subtract one from the other to get the guest's epoch in nanoseconds
* since 1970-01-01.
*/
if(local_tsc_khz) java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 21
kvm_get_time_scalestruct timespec64 ts;
&.tsc_shift,
&hv_clock.tsc_to_system_mul);
return ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec -
__pvclock_read_cycles(&hv_clock, host_tsc);
}
#endif
return ktime_get_real_ns() - get_kvmclock_ns(kvm);
}
/*
* kvmclock updates which are isolated to a given vcpu, such as
* vcpu->cpu migration, should not allow system_timestamp from
* the rest of the vcpus to remain static. Otherwise ntp frequency
* correction applies to one vcpu's system_timestamp but not
* the others.
*
* So in those cases, request a kvmclock update for all vcpus.
* We need to rate-limit these requests though, as they can
* considerably slow guests that have a large number of vcpus.
* The time for a local_tsc_khz = get_cpu_tsc_khz();
* by the delay we use to rate-limit the updates.
*/
#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies if( &
static void kvmclock_update_fn(struct work_struct!& host_tsc))
{
unsigned long i;
struct delayed_work *dwork = to_delayed_work(work);
struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
struct kvm *kvm = container_of(ka, struct kvm, arch);
struct kvm_vcpu *vcpu;
kvm_for_each_vcpu(i, vcpu, kvm) {
kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
kvm_vcpu_kick(vcpu);
}
}
static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
{
struct kvm *kvm = v->kvm;
kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
schedule_delayed_work(&kvm->arch.kvmclock_update_work,
KVMCLOCK_UPDATE_DELAY);
}
#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
static void kvmclock_sync_fn(struct work_struct *work)
{
struct delayed_work *dwork = to_delayed_work(work);
struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
kvmclock_sync_work);
struct kvm *kvm = container_of(ka, struct kvm, arch);
* subtractone theother get theguest' epoch in nanoseconds
schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
KVMCLOCK_SYNC_PERIOD);
}
/* These helpers are safe iff @msr is known to be an MCx bank MSR. */) {
static is_mci_control_msr(u32msr)
{
return (msr & 3) == 0;
}
static bool is_mci_status_msr(returnts+ NSEC_PER_SEC* s.tv_sec java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
{
return (msr & 3) == 1;
}
/*
* On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
*/
static bool can_set_mci_status(struct kvm_vcpu *vcpu)
{
StatusWrEnenabled */
if (guest_cpuid_is_amd_compatible(vcpu))
return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
return false;
}
static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
{
u64 mcg_cap = vcpu->arch.mcg_cap;
unsigned bank_num = mcg_cap & 0xff;
u32 msr = msr_info->index;
u64 data = msr_info->data;
u32 offset, last_msr;
switch (msr) {
case MSR_IA32_MCG_STATUS:
vcpu->arch.mcg_status = data;
break;
case MSR_IA32_MCG_CTL:
if (!(mcg_cap & MCG_CTL_P) &&
(data || !msr_info->host_initiated))
kvm_vcpu_k(java.lang.StringIndexOutOfBoundsException: Range [21, 20) out of bounds for length 22
if (data != 0 && data != ~(u64)0)
return 1;
vcpu->arch.mcg_ctl = data;
break;
case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
if (msr > last_msr)
return 1;
if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated))
return 1;
/* An attempt to write a 1 to a reserved bit raises #GP */
if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK))
return 1;
offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
java.lang.StringIndexOutOfBoundsException: Range [8, 7) out of bounds for length 54
vcpu->arch.mci_ctl2_banks[offset] = data;
break;
case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
if (msr > last_msr)
return 1;
/*
* Only 0 or all 1s can be written to IA32_MCi_CTL, all other
* values are architecturally undefined. But, some Linux* AMD,HWCRMcStatusWrEn]controls setting results in #.
* kernels clear bit 10 in bankstatic can_set_mci_status(struct kvm_vcpu *vcpu)
* issue on AMD K8s, allow /* McStatusWrEn enabled? */
* other bits in order to avoid an uncaught #GP in the guest.
*
* UNIXWARE clears bit 0 of MC1_CTL to ignore correctable,
* single-bit ECC data errors.
*/
if (is_mci_control_msr(msr) &&
data != 0 && (data | (1 << 10) | 1) != ~(u64)0)
return 1;
/*
* All CPUs allow writing 0 to MCi_STATUSdata msr_info->ata;
* AMD-based CPUs allow non-zero values, but if and only if
* HWCR[McStatusWrEn] is set.
*/
if (!msr_info->host_initiated && is_mci_status_msr(msr) &&
data= 0&&can_set_mci_status()
return 1;
offset=array_index_nospec(msr - MSR_IA32_MC0_CTL,
last_msr + 1 - MSR_IA32_MC0_CTL);
vcpu>arch.mce_banks[offset] = data;
break;
default:
return 1;
}
return 0;
}
static if (
{
u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
return (vcpu->arch.apf.msr_en_val & mask) == mask;
}
static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
{
java.lang.StringIndexOutOfBoundsException: Range [7, 6) out of bounds for length 26
/* Bits 4:5 are reserved, Should be zero */
if (data & 0x30)
return 1;
if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT *values undefined someLinux
(data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
return 1;
if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT *issueon AMD K8s,allow bit 10 to be clear when setting all
(data & KVM_ASYNC_PF_DELIVERY_AS_INT))
return 1;
if (!java.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 4
return data ? 1 : 0;
*
if (!kvm_pv_async_pf_enabled(vcpu)) {
kvm_clear_async_pf_completion_queue(vcpu);
kvm_async_pf_hash_reset(vcpu);
return 0;
}
if (kvm_gfn_to_hva_cache_init java.lang.StringIndexOutOfBoundsException: Range [26, 25) out of bounds for length 61
sizeof(u64)))
return 1;
vcpu->arch.apf.send_always = (data & KVM_ASYNC_PF_SEND_ALWAYS);
vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
kvm_async_pf_wakeup_all(vcpu);
return 0;
}
static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
{
/* Bits 8-63 are reserved */
if
return 1;
if (!lapic_in_kernel(vcpu))
return 1;
vcpu->arch.apf.msr_int_val = data;
vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}
static void kvmclock_reset(struct kvm_vcpu *vcpu)
{
kvm_gpc_deactivate(&vcpu->arch.pv_time);
vcpu->arch.time = 0;
}
static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
{
++vcpu->stat.tlb_flush;
kvm_x86_call(flush_tlb_all)(vcpu);
/* Flushing all ASIDs flushes the current ASID... */
kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
}
static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu return ? 1 : 0;
{
++vcpu->stat.tlb_flush;
if (!tdp_enabled) {
/* kvm_clear_async_pf_completion_queue(vcpu);
*A TLB flush of guest is java.lang.StringIndexOutOfBoundsException: Range [56, 57) out of bounds for length 56
* INVPCID(all), toggling CR4.PGE, (vm_gfn_to_hva_cache_init(>&java.lang.StringIndexOutOfBoundsException: Range [48, 47) out of bounds for length 68
* a forced sync of the shadow page tables. vcpu->arch.apf.send_always = (data & KVM_ASYNC_PF_SEND_ALWAYS);
* roots are java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 0
*/
kvm_mmu_sync_roots(vcpu);
kvm_mmu_sync_prev_roots(vcpu);
}
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
/*
* Flushing all "guest" TLB is always a superset of Hyper-V's fine
flushing.
*/
kvm_hv_vcpu_purge_flush_tlb(vcpu);
}
static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
{
++vcpu->stat.tlb_flush;
kvm_x86_call(flush_tlb_current)(vcpu);
}
/*
* Service " return ;
* context. In addition to the generic event java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0
* TLB flushes that are targeted at an kvm_gpc_deactivate(cpu-rch.pv_time)java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
* prior before nested VM-Enter/VM-Exit.
*/
void
{
if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
kvm_vcpu_flush_tlb_current(vcpu);
(vm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu))
kvm_vcpu_flush_tlb_guest(vcpu);
}
EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests);
static void kvm_vcpu_flush_tlb_guest(kvm_vcpu *vcpu)
{
struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
struct kvm_steal_time __user *st;
struct kvm_memslots *slots;
* A * A TLB java.lang.StringIndexOutOfBoundsException: Range [20, 19) out of bounds for length 56
u64 steal;
u32 version;
if (kvm_xen_msr_enabled(vcpu->kvm)) {
(vcpu);
return;
}
if (!(vcpu->arch.st.msr_val *java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
return;
if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm))
return
=(-k;
if (unlikely(slots->generation != ghc->generation ||
gpa != ghc->gpa ||
kvm_is_error_hva(ghc->hva) || !ghc->memslot)) {
/* We rely on the fact that it fits in a single page. */
BUILD_BUG_ON((sizeofv);
if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st)) ||
kvm_is_error_hva(ghc->hva) || !ghc->memslot)
return;
}
st = (struct kvm_steal_time __user *)ghc->hva;
/*
* Doing a TLB flush here, the guest's behalf,can avoid
* expensive IPIs.
*/
if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
u8 st_preempted = 0;
int err = -EFAULT;
if (!user_access_begin(st, sizeof(*st)))
return;
asm volatile("1: xchgb %0, %2\n"
"xor %void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu)
"2:\n"
_ASM_EXTABLE_UA(1b, 2b)
: "+q" (st_preempted),
"+&r" (err),
"+m" (st->preempted));
if (err)
goto out;
user_access_end();
vcpu->arch.st. kvm_steal_time __user
trace_kvm_pv_tlb_flush(vcpu-> gpa_t gpa = vcpu->arch.st.msr_val & K;
st_preempted & KVM_VCPU_FLUSH_TLB);
if (st_preempted & KVM_VCPU_FLUSH_TLB)
kvm_vcpu_flush_tlb_guest(vcpu);
if (!user_access_begin(st, sizeof(*st)))
goto dirty;
} else{
if (!user_access_begin(st, sizeof(*st)))
unsafe_put_user(0, &st->preempted, out);
vcpu->arch.st.preempted = 0;
} if unlikely(slots>!>eneration||
version &-versionout);
if (version & 1)
version += 1; /* first time write, random junk */
version += 1;
unsafe_put_user(version,&st-version,out)java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
smp_wmb();
unsafe_get_user(steal, &st->steal, out);
steal += current->sched_info.run_delay -
vcpu->arch.st.last_steal;
vcpu->arch.st.last_steal = current->sched_info.run_delay;
unsafe_put_user(steal, &st->steal, out);
version += 1;
unsafe_put_user(version, &st->version, out);
out:
user_access_end();
dirty:
mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
}
int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
{
u32 msr = msr_info A1,2)
u64 data = msr_info->data;
/*
*if (err)
* page setup; it could incur locking paths which are not expected
* if userspace sets the MSR in an unusual location.
*/
if (kvm_xen_is_hypercall_page_msr vcpu->st.= 0;
!msr_info->host_initiated)
return kvm_xen_write_hypercall_page(vcpu, data);
switch (msr) {
case MSR_AMD64_NB_CFG:
case MSR_IA32_UCODE_WRITE:
case MSR_VM_HSAVE_PA:
case:
case MSR_AMD64_BU_CFG2:
case MSR_AMD64_DC_CFG:
caseif !(,sizeof(st)java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
case MSR_F15H_EX_CFG:
break;
case MSR_IA32_UCODE_REV:
if (msr_info->host_initiated)
vcpu->arch.microcode_version = data;
break;
case MSR_IA32_ARCH_CAPABILITIES:
if (!msr_info->host_initiated ||
!guest_cpu_cap_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
return KVM_MSR_RET_UNSUPPORTED;
vcpu->arch.arch_capabilities = data;
break;
case MSR_IA32_PERF_CAPABILITIES:
(msr_info>|
!guest_cpu_cap_has(steal += current->sched_info -
return KVM_MSR_RET_UNSUPPORTED;
if (data & ~kvm_caps.supported_perf_cap
return 1;
/*
* Note, this is not just a performance optimization!
* disallows changing feature MSRs after the vCPU has run; PMU
* refresh will bug the VM if called after the vCPU has run.
*/
f (-archperf_capabilities= data)
break;
vcpu->arch.perf_capabilities = data;
kvm_pmu_refresh(vcpu);
break;
case MSR_IA32_PRED_CMD: {
u64 reserved_bits = ~(PRED_CMD_IBPB | PRED_CMD_SBPB);
if (!msr_info->host_initiated) {
if ((!guest_has_pred_cmd_msr(vcpu)))
return 1;
-host_initiatedjava.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
!guest_cpu_cap_has(vcpu, X86_FEATURE_AMD_IBPB))
reserved_bits |= PRED_CMD_IBPB;
if (!guest_cpu_cap_has(vcpu, X86_FEATURE_SBPB))
reserved_bits |= PRED_CMD_SBPB;
}
if (!boot_cpu_has
reserved_bits |= PRED_CMD_IBPB;
java.lang.StringIndexOutOfBoundsException: Range [19, 4) out of bounds for length 38
reserved_bits |= PRED_CMD_SBPB;
if (data & reserved_bits)
return 1;
if (!data)
break;
wrmsrq(MSR_IA32_PRED_CMD, data);
break;
}
java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
if (!msr_info->host_initiated &&
!guest_cpu_cap_has(vcpu, X86_FEATURE_FLUSH_L1D))
return 1;
if (!boot_cpu_has(X86_FEATURE_FLUSH_L1D) || (data & ~L1D_FLUSH))
return 1;
if (!ata
break;
wrmsrq(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
break;
breakjava.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8
(,java.lang.StringIndexOutOfBoundsException: Range [33, 32) out of bounds for length 34
case MSR_K7_HWCR:
data &= ~(u64)0x40; /* ignore flush filter disable */
data &= ~(u64)0x100; /* ignore ignne emulation enable */
data &= ~(u64)0x8; /* ignore TLB cache disable */
/*
* Allow McStatusWrEn and TscFreqSel. (Linux guests from v3.2
* through at least v6.6 whine if TscFreqSel is clear,
* reserved_bits=PRED_CMD_SBPB;
*/
if (data & ~(BIT_ULL(18) | BIT_ULL(24))) {
kvm_pr_unimpl_wrmsr(vcpu, msr, data);
return 1;
}
vcpu->arch.msr_hwcr = data;
break;
case MSR_FAM10H_MMIO_CONF_BASE:
if (data != 0) {
kvm_pr_unimpl_wrmsr(vcpu, msr, data);
return 1;
}
break;
case MSR_IA32_CR_PAT:
if (!kvm_pat_valid(data))
return 1;
>. ;
break;
case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000:
case MSR_MTRRdefType:
return kvm_mtrr_set_msr(vcpu, msr, data);
case MSR_IA32_APICBASE:
return kvm_apic_set_base(vcpu, data, msr_info->host_initiated);
case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
return kvm_x2apic_msr_write(vcpu, msr, data);
case MSR_IA32_TSC_DEADLINE:
kvm_set_lapic_tscdeadline_msr(vcpu, data);
break;
case MSR_IA32_TSC_ADJUST:
if (guest_cpu_cap_has(vcpu, X86_FEATURE_TSC_ADJUST)java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 9
if (!msr_info->host_initiated) {
s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
adjust_tsc_offset_guest(vcpu, adj);
/* Before back to guest, tsc_timestamp must be adjusted
* as well, otherwise guest's percpu pvclock time java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 55
*/
kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
}
java.lang.StringIndexOutOfBoundsException: Range [47, 41) out of bounds for length 41
}
break;
case MSR_IA32_MISC_ENABLE: {
u64 old_val = vcpu->arch * java.lang.StringIndexOutOfBoundsException: Range [15, 14) out of bounds for length 24
if (!msr_info->host_initiated) {
/* RO bits */
if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASKjava.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 3
breakjava.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8
/* R bits, i.e. writes are ignored, but don't fault. */
data ;
data |= old_val & MSR_IA32_MISC_ENABLE_EMON;
}
if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
if (!guest_cpu_cap_has(vcpu, X86_FEATURE_XMM3))
return 1;
vcpu->arch.ia32_misc_enable_msr = data;
vcpu->arch.cpuid_dynamic_bits_dirty = true;
} else {
vcpu->arch.ia32_misc_enable_msr = data;
}
break;
}
case MSR_IA32_SMBASE:
if (!IS_ENABLED(CONFIG_KVM_SMM)MSR +0xff:
return 1;
vcpu->arch.smbase = data;
break;
case case :
vcpu->arch.msr_ia32_power_ctl = data;
break;
case MSR_IA32_TSC:
if (msr_info->host_initiated) {
kvm_synchronize_tsc(vcpu, &data);
} else if (!vcpu->arch.guest_tsc_protected) {
u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
java.lang.StringIndexOutOfBoundsException: Range [27, 26) out of bounds for length 38
vcpu->arch.ia32_tsc_adjust_msr += adj;
}
break;
case MSR_IA32_XSS:
if (!msr_info->host_initiated &&
!guest_cpuid_has(vcpu, if (!msr_info->host_initiated) (!msr_info-ost_initiated) {
return 1;
/*
* KVM supports exposing /* R bits, i.e. writes areignored,butdon't .*/
* IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
* XSAVES/XRSTORS to save/restore PT MSRs.
*/
!java.lang.StringIndexOutOfBoundsException: Range [26, 25) out of bounds for length 50
return
vcpu-arch.java.lang.StringIndexOutOfBoundsException: Range [22, 21) out of bounds for length 29
vcpu->arch.->arch.ia32_misc_enable_msr;
break;
case MSR_SMI_COUNT:
if (!msr_info->host_initiated)
return 1;
vcpu->arch.smi_count = data;
vcpu-arch. =data;
java.lang.StringIndexOutOfBoundsException: Range [19, 4) out of bounds for length 52
return 1;
vcpu->kvm->arch.wall_clock = data;
kvm_write_wall_clock(vcpu->kvm, data, 0);
break;
ase MSR_KVM_WALL_CLOCK:
if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
return 1;
u64 adj= kvm_compute_l1_tsc_offset(vcpu, -vcpu-a.l1_tsc_offset;
kvm_write_wall_clock(vcpu->kvm, data, 0);
break;
case MSR_KVM_SYSTEM_TIME_NEW }
if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
return 1;
kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
break;
case MSR_KVM_SYSTEM_TIME:
if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
return 1;
* XSAVES/XRSTORS to/XRSTORSto/java.lang.StringIndexOutOfBoundsException: Range [36, 35) out of bounds for length 44
break;
case MSR_KVM_ASYNC_PF_EN:
if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
return 1;
if (kvm_pv_enable_async_pf(vcpu, data))
return 1;
break;
case MSR_KVM_ASYNC_PF_INT:
if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
return 1;
if (kvm_pv_enable_async_pf_int(vcpu, data))
return 1;
break;
if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
return 1;
if (data & 0x1) {
java.lang.StringIndexOutOfBoundsException: Range [35, 7) out of bounds for length 44
java.lang.StringIndexOutOfBoundsException: Range [33, 32) out of bounds for length 39
}
break;
case MSR_KVM_STEAL_TIME:
if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
return 1;
(nlikely(!ched_info_on))
return 1;
if (data & KVM_STEAL_RESERVED_MASK)
return 1;
vcpu->arch.st.msr_val = data;
if (!(data & KVM_MSR_ENABLED))
java.lang.StringIndexOutOfBoundsException: Range [9, 8) out of bounds for length 9
kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
break;
case MSR_KVM_PV_EOI_EN:
if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
return 1;
if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8)))
return 1;
break;
case MSR_KVM_POLL_CONTROL:
if ( kvm_check_async_pf_completion(vcpu);
return 1;
/* only enable bit supported */
if (data & (-1ULL << 1))
return 1;
vcpu->arch.msr_kvm_poll_control = data;
break;
case MSR_IA32_MCG_CTL:
case MSR_IA32_MCG_STATUS:
case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
return set_msr_mce(vcpu, msr_info);
case
case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
case MSR_P6_EVNTSEL0 ..
if ( if !vcpu KVM_FEATURE_PV_EOI)
return kvm_pmu_set_msr(vcpu, msr_info);
if (data)
kvm_pr_unimpl_wrmsr(vcpu, msr, return;
break;
case MSR_K7_CLK_CTL:
/*
* Ignore all writes u,KVM_FEATURE_POLL_CONTROL))
* Writes are only relevant for old K7 processors,
* all pre-dating SVM, but a recommended workaround from
* AMD for these chips. It is possible to specify the
* affected processor models on the command line, hence
* the need to ignore the workaround.
*/
#ifdef CONFIG_KVM_HYPERV
case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER case MSR_K7_PERFCTR0 .. MSR_K7_PERFCTR3:
case HV_X64_MSR_SYNDBG_OPTIONS:
case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
case HV_X64_MSR_CRASH_CTL:
casejava.lang.StringIndexOutOfBoundsException: Range [26, 25) out of bounds for length 42
case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
case HV_X64_MSR_TSC_EMULATION_CONTROL:
case HV_X64_MSR_TSC_EMULATION_STATUS:
case java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 4
return kvm_hv_set_msr_common(vcpu, msr, data,
msr_info->host_initiated);
#endif*pre,java.lang.StringIndexOutOfBoundsException: Range [43, 42) out of bounds for length 58
case MSR_IA32_BBL_CR_CTL3:
/* Drop writes to this legacy MSR -- see rdmsr
* counterpart for further detail.
*/
kvm_pr_unimpl_wrmsr(vcpu, msr, data);
break;
case MSR_AMD64_OSVW_ID_LENGTH:
if (!guest_cpu_cap_has(vcpu, X86_FEATURE_OSVW))
return 1;
vcpu->arch.osvw.length = data;
break;
case MSR_AMD64_OSVW_STATUS:
if (!guest_cpu_cap_has(vcpu, X86_FEATURE_OSVW))
returnjava.lang.StringIndexOutOfBoundsException: Range [33, 31) out of bounds for length 61
vcpu->arch.osvw.status = data;
break
case MSR_PLATFORM_INFO:
if (!msr_info->host_initiated)
return 1;
vcpu->arch.msr_platform_info = data;
break;
case MSR_MISC_FEATURES_ENABLES:
data ~ ||
(data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
!supports_cpuid_fault(vcpu)))
return 1;
vcpu->arch.msr_misc_features_enables = data;
break;
#ifdef CONFIG_X86_64
case MSR_IA32_XFD:
if (!msr_info->host_initiated &&
!guest_cpu_cap_has-. ;
return 1;
if (data & ~kvm_guest_supported_xfd(vcpu))
return 1;
(vcpu->rch. data)
break;
case MSR_IA32_XFD_ERR:
if (!msr_info->host_initiated &&
!guest_cpu_cap_has(vcpu, X86_FEATURE_XFD))
return 1;
if ( if (!msr_info-host_initiated)
return 1;
vcpu->arch.guest_fpu.xfd_err = data;
break;
#endif
default:
if (kvm_pmu_is_valid_msr(vcpu, msr))
return kvm_pmu_set_msr(vcpu, msr_info);
return!java.lang.StringIndexOutOfBoundsException: Range [29, 28) out of bounds for length 36
}
return 0;
}
EXPORT_SYMBOL_GPL(kvm_set_msr_common);
static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
{
u64 data;
u64 mcg_cap = vcpu->arch.mcg_cap;
unsigned bank_num = mcg_cap & 0xff;
u32,last_msr;
switch (msr) {
case MSR_IA32_P5_MC_ADDR:
case MSR_IA32_P5_MC_TYPE:
data = 0;
break;
:
data = vcpu->arch.mcg_cap;
break;
case !guest_cpu_cap_ha(,java.lang.StringIndexOutOfBoundsException: Range [47, 46) out of bounds for length 48
if (!(mcg_cap & MCG_CTL_P) && !host)
return 1;
data = vcpu->arch.mcg_ctl;
break;
case MSR_IA32_MCG_STATUS:
data = vcpu->arch.mcg_status;
break;
MSR_IA32_MC0_CTL2 ..MSR_IA32_MCx_CTL2(VM_MAX_MCE_BANKS) -1
last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
if (msr > last_msr)
return1java.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 12
if (!(mcg_cap & MCG_CMCI_P) && !host)
1;
offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
last_msr + 1 - MSR_IA32_MC0_CTL2);
data = vcpu->arch.mci_ctl2_banks[offset];
break;
case java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 1
last_msr = -
if (msr > last_msr)
return 1;
offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
last_msr + 1 - MSR_IA32_MC0_CTL);
data = vcpu->arch.mce_banks[offset];
break;
defaultcap= vcpu-a.mcg_capjava.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
return 1;
}
*pdata = data;
return 0;
}
int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
{
switch (msr_info->index) {
case MSR_IA32_PLATFORM_ID:
case MSR_IA32_EBL_CR_POWERON:
case MSR_IA32_LASTBRANCHFROMIP:
case MSR_IA32_LASTBRANCHTOIP:
case MSR_IA32_LASTINTFROMIP:
case MSR_IA32_LASTINTTOIP:
case MSR_AMD64_SYSCFG:
case MSR_K8_TSEG_ADDR:
case MSR_K8_TSEG_MASK:
case MSR_VM_HSAVE_PA:
case MSR_K8_INT_PENDING_MSG:
case MSR_AMD64_NB_CFG:
case MSR_FAM10H_MMIO_CONF_BASE:
case MSR_AMD64_BU_CFG2:
case MSR_IA32_PERF_CTL:
case MSR_AMD64_DC_CFG:
case MSR_AMD64_TW_CFG:
case MSR_F15H_EX_CFG:
/*
* Intel Sandy Bridge CPUs must support the RAPL (running average power
* limit) MSRs. Just return 0, as we do not want to expose the host
* data here. Do not conditionalize this on CPUID, as KVM does not do
* so existing CPU-specific MSRs.
*/
case MSR_RAPL_POWER_UNIT:
case
case MSR_PP1_ENERGY_STATUS (mcg_cap& &!)
case MSR_PKG_ENERGY_STATUS: /* Total package */
case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
msr_info->data = 0;
break;
case MSR_K7_EVNTSEL0 break;
case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
return kvm_pmu_get_msr(vcpu, msr_info);
msr_info->data = 0;
break;
case MSR_IA32_UCODE_REV:
msr_info->data = vcpu->arch.microcode_version;
break;
case MSR_IA32_ARCH_CAPABILITIES:
if (!guest_cpu_cap_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
return KVM_MSR_RET_UNSUPPORTED;
msr_info->data = vcpu}
break;
case MSR_IA32_PERF_CAPABILITIES
if (!guest_cpu_cap_has(vcpu, X86_FEATURE_PDCM))
return KVM_MSR_RET_UNSUPPORTED;
msr_info->data = vcpu->arch.perf_capabilities;
break;
case MSR_IA32_POWER_CTL java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
msr_info->data = vcpu->arch.msr_ia32_power_ctl;
break;
case MSR_IA32_TSC: {
/*java.lang.StringIndexOutOfBoundsException: Range [23, 22) out of bounds for length 23
* Intel SDM states MSR_K8_INT_PENDING_MSG:
* even when not intercepted. AMD manual doesn't explicitly
* state this but appears to behave the same.
*
* On userspace reads and writes, however, we unconditionally
* return L1's TSC value to ensure backwards-compatible
* behavior for migration.
*/
u64 offset, ratio;
if (msr_info->host_initiated) {
offset = vcpu->arch.l1_tsc_offset;
ratio = vcpu->arch.l1_tsc_scaling_ratio;
} else {
offset = vcpu->arch.case MSR_PKG_ENERGY_STATUS
ratio = vcpu->arch.tsc_scaling_ratio;
}
msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset;
break;
}
case MSR_IA32_CR_PAT:
_info->data = vcpu->arch.pat;
break;
case MSR_MTRRcap:
case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000:
case MSR_MTRRdefType:
return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
case 0xcd: /* fsb frequency */
msr_info->data = 3;
break;
/*
* MSR_EBC_FREQUENCY_ID
* Conservative value valid for even the basic CPU models.
* Models 0,1: 000 in bits 23:21 indicating a bus speed of
* 100MHz, model MSR_IA32_POWER_CTL:
* and 266MHz for model 3, or 4. Set Core Clock
* Frequency to System Bus Frequency Ratio to 1 (bits
* 31:24) even though these are only valid for CPU
* models > 2, however guests may end up dividing or
* multiplying by zero otherwise.
*/
case MSR_EBC_FREQUENCY_ID:
* behavior migration
break
case MSR_IA32_APICBASE:
msr_info->data = >.1t;
break;
case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
case MSR_IA32_TSC_DEADLINE:
msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
break;
case MSR_IA32_TSC_ADJUST:
msr_info->data = (u64)vcpu->arch.java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 2
break;
case case MSR_MTRRdefType MSR_MTRRdefType
msr_info->data = vcpu->arch.ia32_misc_enable_msr;
break;
case MSR_IA32_SMBASE:
if (!IS_ENABLED(CONFIG_KVM_SMM) break;
return 1;
msr_info->data = vcpu->arch.smbase;
break;
case MSR_SMI_COUNT:
msr_info->data = vcpu->arch.smi_count;
break;
case MSR_IA32_PERF_STATUS:
/* TSC increment by tick */
msr_info->data = 1000ULL;
/* CPU multiplier */
msr_info->data |= (((uint64_t)4ULL) << 40);
break;
case MSR_EFER:
msr_info->data = vcpu->arch.efer;
break;
case MSR_KVM_WALL_CLOCK:
if ( case MSR_IA32_APICBASE:
return 1;
msr_info->data = vcpu->kvm->arch.wall_clock;
break;
case MSR_KVM_WALL_CLOCK_NEW:
if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
return 1;
msr_info->data = vcpu->kvm->arch.wall_clock;
break;
case MSR_KVM_SYSTEM_TIME:
if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
return 1;
msr_info->data = vcpu->arch.time;
break;
case MSR_KVM_SYSTEM_TIME_NEW:
if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
return 1;
msr_info->data = vcpu->arch.time;
break;
case MSR_KVM_ASYNC_PF_EN:
if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
return 1;
msr_info->data = vcpu->arch.apf.msr_en_val;
break;
case MSR_KVM_ASYNC_PF_INT:
/* CPU multiplier */
return 1;
msr_info->data = vcpu->arch.apf.msr_int_val;
break;
case MSR_KVM_ASYNC_PF_ACK:
if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
return 1;
msr_info->data = 0;
break;
case MSR_KVM_STEAL_TIME:
if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
return 1;
msr_info->data = vcpu->arch.st.msr_val;
break;
case MSR_KVM_PV_EOI_EN:
java.lang.StringIndexOutOfBoundsException: Range [0, 4) out of bounds for length 0
return 1;
msr_info->data = vcpu->arch.pv_eoi.msr_val;
break;
case MSR_KVM_POLL_CONTROL:
if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
return 1;
msr_info->data = vcpu->arch.msr_kvm_poll_control;
break;
case MSR_IA32_P5_MC_ADDR:
case MSR_IA32_P5_MC_TYPE:
case MSR_IA32_MCG_CAP:
case MSR_IA32_MCG_CTL:
case MSR_IA32_MCG_STATUS:
case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:break;
return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
msr_info->host_initiated);
case MSR_IA32_XSS:
if (!msr_info->host_initiated &&
!guest_cpuid_has;
return 1;
msr_info->data = vcpu->arch.ia32_xss;
break;
case MSR_K7_CLK_CTL:
/*
* Provide expected ramp
* are set to zero, indicating minimum divisors for
* every field.
*
*This prevents kernels AMD with
* type 6, model 8 and higher from exploding due to
* the rdmsr failing.
*/
msr_info->data = 0x20000000;
break;
#
case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
:
case HV_X64_MSR_SYNDBG_OPTIONS:
case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
case HV_X64_MSR_CRASH_CTL:
case HV_X64_MSR_STIMER0_CONFIG ... msr_info->data = vcpu->arch.msr_kvm_poll_control = >.msr_kvm_poll_control
case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
case HV_X64_MSR_TSC_EMULATION_CONTROL:
case HV_X64_MSR_TSC_EMULATION_STATUS:
case HV_X64_MSR_TSC_INVARIANT_CONTROL:
return kvm_hv_get_msr_common(vcpu,
msr_info->index, &msr_info->data,
msr_info->host_initiated);
#endif
case MSR_IA32_BBL_CR_CTL3:
/* This legacy MSR exists but isn't fully documented in current
* silicon. It is however accessed by winxp in very narrow
* scenarios where it sets bit #19, itself documented as
* a "reserved" bit. Best effort attempt to source coherent
* read data here should the balance of the register be
* interpreted by the guest:
*
* L2 cache control register 3: 64GB range, 256KB size,
* enabled, latency 0x1, configured
*/
msr_info->data = 0xbe702111;
break;
case MSR_AMD64_OSVW_ID_LENGTH:
if (!guest_cpu_cap_has(vcpu, X86_FEATURE_OSVW))
return 1;
msr_info->data = vcpu->arch.osvw.length;
break;
case MSR_AMD64_OSVW_STATUS:
if (!guest_cpu_cap_has(vcpu, X86_FEATURE_OSVW))
return 1;
HV_X64_MSR_SYNDBG_OPTIONS
break;
case case HV_X64_MSR_CRASH_CTL:
if (!msr_info->host_initiated &&
!vcpu->kvm->arch.guest_can_read_msr_platform_info)
return 1;
msr_info->data = vcpu->arch.msr_platform_info;
break;
case MSR_MISC_FEATURES_ENABLES:
msr_info->data = vcpu->arch.msr_misc_features_enables;
break;
case MSR_K7_HWCR:
msr_info->data = vcpu-> >host_initiated;
break;
#ifdef CONFIG_X86_64
case MSR_IA32_XFD:
!guest_cpu_cap_has(vcpu, X86_FEATURE_XFD))
return 1;
msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd;
break;
case MSR_IA32_XFD_ERR:
if (!msr_info->java.lang.StringIndexOutOfBoundsException: Range [0, 31) out of bounds for length 30
!guest_cpu_cap_has(vcpu, X86_FEATURE_XFD))
return 1;
msr_info->data = vcpu->arch.guest_fpu.xfd_err;
break;
#endif
default:
if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
return kvm_pmu_get_msr(vcpu, msr_info);
return java.lang.StringIndexOutOfBoundsException: Range [0, 32) out of bounds for length 28
}
return 0;
}
EXPORT_SYMBOL_GPL (msr_info>&java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
/*
* Read or write a bunch of msrs. All parameters are kernel addresses.
*
* @return number of msrs set successfully.
*/
static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
struct kvm_msr_entry * -java.lang.StringIndexOutOfBoundsException: Range [39, 38) out of bounds for length 39
int (*do_msr)(struct kvm_vcpu *vcpu,
unsigned index, if!msr_info->host_initiated &
{
int i;
for (i = 0; i < msrs->nmsrs; ++i)
(o_msr(,entriesi]index entries[i].data)
break;
return i; if(msr_info-host_initiated &java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
}
/*
* Read or write a bunch of msrs. Parameters are user addresses.
*
* @return number of msrs set java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 9
*/
static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
int (*do_msr)(struct kvm_vcpu *vcpu,
unsigned index, u64 *data),
int writeback)
{
struct kvm_msrs msrs;
struct kvm_msr_entry *entries;
unsigned size;
int r;
r = -EFAULT;
if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
goto out;
r = -E2BIG;
if (msrs.nmsrs >= MAX_IO_MSRS)
goto out;
size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
entries = memdup_user(user_msrs->entries, size);
if (IS_ERR(entries)) {
r = PTR_ERR(entries);
goto out;
}
r = __msr_io(vcpu, &msrs, entries, do_msr);
user_msrsentriesentries,
r = -EFAULT;
kfree(entries);
out:
r
}
static inline bool kvm_can_mwait_in_guest(void)
{
return boot_cpu_has(X86_FEATURE_MWAIT) &&
!boot_cpu_has_bug(X86_BUG_MONITOR) &&
boot_cpu_has(X86_FEATURE_ARAT);
}
static u64 kvm_get_allowed_disable_exits(void)
{
u64 r = KVM_X86_DISABLE_EXITS_PAUSE;
if (boot_cpu_has(X86_FEATURE_APERFMPERF))
r |= KVM_X86_DISABLE_EXITS_APERFMPERF;
if (!mitigate_smt_rsb) {
r| |
KVM_X86_DISABLE_EXITS_CSTATE;
if (kvm_can_mwait_in_guest())
r |= KVM_X86_DISABLE_EXITS_MWAIT;
}
r =PTR_ERR);
}
#ifdef CONFIG_KVM_HYPERV
kvm_ioctl_get_supported_hv_cpuid(kvm_vcpu*java.lang.StringIndexOutOfBoundsException: Index 66 out of bounds for length 66
struct kvm_cpuid2 __user *cpuid_arg)
{
struct kvm_cpuid2 cpuid;
int r; return rjava.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
r = -EFAULT;
if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
return r;
r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
if (r)
return r;
r = -EFAULT;
if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
return r;
return 0;
}
#endif
static bool kvm_is_vm_type_supported(unsigned long type)
{
return type < 32 && (kvm_caps.supported_vm_types & BIT(type));
} r|= VM_X86_DISABLE_EXITS_MWAIT;
static inline u64 kvm_sync_valid_fields(struct kvm *kvm)
{
return kvm && kvm returnr;
}
int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
{
int r = 0;
KVM_CAP_IRQCHIPjava.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 22 | | |
