// SPDX-License-Identifier: GPL-2.0-only /* arch/sparc64/kernel/traps.c * * Copyright ( C ) 1995 , 1997 , 2008 , 2009 , 2012 David S . Miller ( davem @ davemloft . net ) * Copyright ( C ) 1997 , 1999 , 2000 Jakub Jelinek ( jakub @ redhat . com ) /* * I like traps on v9 , : ) ) ) ) #include <linux/cpu.h>#include <linux/extable.h>#include <linux/sched/mm.h>#include <linux/sched/debug.h>#include <linux/linkage.h>#include <linux/kernel.h>#include <linux/signal.h>#include <linux/smp.h>#include <linux/mm.h>#include <linux/init.h>#include <linux/kallsyms.h>#include <linux/kdebug.h>#include <linux/ftrace.h>#include <linux/reboot.h>#include <linux/gfp.h>#include <linux/context_tracking.h>#include <asm /smp.h>#include <asm /delay.h>#include <asm /ptrace.h>#include <asm /oplib.h>#include <asm /page.h>#include <asm /unistd.h>#include <linux/uaccess.h>#include <asm /fpumacro.h>#include <asm /lsu.h>#include <asm /dcu.h>#include <asm /estate.h>#include <asm /chafsr.h>#include <asm /sfafsr.h>#include <asm /psrcompat.h>#include <asm /processor.h>#include <asm /timer.h>#include <asm /head.h>#include <asm /prom.h>#include <asm /memctrl.h>#include <asm /cacheflush.h>#include <asm /setup.h>#include "entry.h" #include "kernel.h" #include "kstack.h" /* When an irrecoverable trap occurs at tl > 0, the trap entry * code logs the trap state registers at every level in the trap * stack . It is found at ( pt_regs + sizeof ( pt_regs ) ) and the layout * is as follows : struct tl1_traplog {struct {unsigned long tstate;unsigned long tpc;unsigned long tnpc;unsigned long tt;4 ];unsigned long tl;static void dump_tl1_traplog(struct tl1_traplog *p)int i, limit;"TRAPLOG: Error at trap level 0x%lx, " "dumping track stack.\n" , p->tl);2 : 4 ;for (i = 0 ; i < limit; i++) {"TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] " "TNPC[%016lx] TT[%lx]\n" ,1 ,"TRAPLOG: TPC<%pS>\n" , (void *) p->trapstack[i].tpc);void bad_trap(struct pt_regs *regs, long lvl)char buffer[36 ];if (notify_die(DIE_TRAP, "bad trap" , regs,0 , lvl, SIGTRAP) == NOTIFY_STOP)return ;if (lvl < 0 x100) {"Bad hw trap %lx at tl0\n" , lvl);0 x100;if (regs->tstate & TSTATE_PRIV) {"Kernel bad sw trap %lx" , lvl);if (test_thread_flag(TIF_32BIT)) {0 xffffffff;0 xffffffff;void __user *)regs->tpc, lvl);void bad_trap_tl1(struct pt_regs *regs, long lvl)char buffer[36 ];if (notify_die(DIE_TRAP_TL1, "bad trap tl1" , regs,0 , lvl, SIGTRAP) == NOTIFY_STOP)return ;struct tl1_traplog *)(regs + 1 ));"Bad trap %lx at tl>0" , lvl);#ifdef CONFIG_DEBUG_BUGVERBOSEvoid do_BUG(const char *file, int line)1 );"kernel BUG at %s:%d!\n" , file, line);#endif static DEFINE_SPINLOCK(dimm_handler_lock);static dimm_printer_t dimm_handler;static int sprintf_dimm(int synd_code, unsigned long paddr, char *buf, int buflen)unsigned long flags;int ret = -ENODEV;if (dimm_handler) {else if (tlb_type == spitfire) {if (prom_getunumber(synd_code, paddr, buf, buflen) == -1 )else 0 ;else return ret;int register_dimm_printer(dimm_printer_t func)unsigned long flags;int ret = 0 ;if (!dimm_handler)else return ret;void unregister_dimm_printer(dimm_printer_t func)unsigned long flags;if (dimm_handler == func)void spitfire_insn_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)enum ctx_state prev_state = exception_enter();if (notify_die(DIE_TRAP, "instruction access exception" , regs,0 , 0 x8, SIGTRAP) == NOTIFY_STOP)goto out;if (regs->tstate & TSTATE_PRIV) {"spitfire_insn_access_exception: SFSR[%016lx] " "SFAR[%016lx], going.\n" , sfsr, sfar);"Iax" , regs);if (test_thread_flag(TIF_32BIT)) {0 xffffffff;0 xffffffff;void __user *)regs->tpc);void spitfire_insn_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1" , regs,0 , 0 x8, SIGTRAP) == NOTIFY_STOP)return ;struct tl1_traplog *)(regs + 1 ));void sun4v_insn_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)unsigned short type = (type_ctx >> 16 );unsigned short ctx = (type_ctx & 0 xffff);if (notify_die(DIE_TRAP, "instruction access exception" , regs,0 , 0 x8, SIGTRAP) == NOTIFY_STOP)return ;if (regs->tstate & TSTATE_PRIV) {"sun4v_insn_access_exception: ADDR[%016lx] " "CTX[%04x] TYPE[%04x], going.\n" ,"Iax" , regs);if (test_thread_flag(TIF_32BIT)) {0 xffffffff;0 xffffffff;void __user *) addr);void sun4v_insn_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1" , regs,0 , 0 x8, SIGTRAP) == NOTIFY_STOP)return ;struct tl1_traplog *)(regs + 1 ));static bool is_no_fault_exception(struct pt_regs *regs)unsigned char asi;if (get_user(insn, (u32 __user *)regs->tpc) == -EFAULT)return false ;/* * Must do a little instruction decoding here in order to * decide on a course of action . The bits of interest are : * insn [ 31 : 30 ] = op , where 3 indicates the load / store group * insn [ 24 : 19 ] = op3 , which identifies individual opcodes * insn [ 13 ] indicates an immediate offset * op3 [ 4 ] = 1 identifies alternate space instructions * op3 [ 5 : 4 ] = 3 identifies floating point instructions * op3 [ 2 ] = 1 identifies stores * See " Opcode Maps " in the appendix of any Sparc V9 * architecture spec for full details . if ((insn & 0 xc0800000) == 0 xc0800000) { /* op=3, op3[4]=1 */ if (insn & 0 x2000) /* immediate offset */ 24 ); /* saved %asi */ else 5 ); /* immediate asi */ if ((asi & 0 xf6) == ASI_PNF) {if (insn & 0 x200000) /* op3[2], stores */ return false ;if (insn & 0 x1000000) /* op3[5:4]=3 (fp) */ else return true ;return false ;void spitfire_data_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)enum ctx_state prev_state = exception_enter();if (notify_die(DIE_TRAP, "data access exception" , regs,0 , 0 x30, SIGTRAP) == NOTIFY_STOP)goto out;if (regs->tstate & TSTATE_PRIV) {/* Test if this comes from uaccess places. */ const struct exception_table_entry *entry;if (entry) {/* Ouch, somebody is trying VM hole tricks on us... */ #ifdef DEBUG_EXCEPTIONS"Exception: PC<%016lx> faddr<UNKNOWN>\n" , regs->tpc);"EX_TABLE: insn<%016lx> fixup<%016lx>\n" ,#endif 4 ;goto out;/* Shit... */ "spitfire_data_access_exception: SFSR[%016lx] " "SFAR[%016lx], going.\n" , sfsr, sfar);"Dax" , regs);if (is_no_fault_exception(regs))return ;void __user *)sfar);void spitfire_data_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)if (notify_die(DIE_TRAP_TL1, "data access exception tl1" , regs,0 , 0 x30, SIGTRAP) == NOTIFY_STOP)return ;struct tl1_traplog *)(regs + 1 ));void sun4v_data_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)unsigned short type = (type_ctx >> 16 );unsigned short ctx = (type_ctx & 0 xffff);if (notify_die(DIE_TRAP, "data access exception" , regs,0 , 0 x8, SIGTRAP) == NOTIFY_STOP)return ;if (regs->tstate & TSTATE_PRIV) {/* Test if this comes from uaccess places. */ const struct exception_table_entry *entry;if (entry) {/* Ouch, somebody is trying VM hole tricks on us... */ #ifdef DEBUG_EXCEPTIONS"Exception: PC<%016lx> faddr<UNKNOWN>\n" , regs->tpc);"EX_TABLE: insn<%016lx> fixup<%016lx>\n" ,#endif 4 ;return ;"sun4v_data_access_exception: ADDR[%016lx] " "CTX[%04x] TYPE[%04x], going.\n" ,"Dax" , regs);if (test_thread_flag(TIF_32BIT)) {0 xffffffff;0 xffffffff;if (is_no_fault_exception(regs))return ;/* MCD (Memory Corruption Detection) disabled trap (TT=0x19) in HV * is vectored thorugh data access exception trap with fault type * set to HV_FAULT_TYPE_MCD_DIS . Check for MCD disabled trap . * Accessing an address with invalid ASI for the address , for * example setting an ADI tag on an address with ASI_MCD_PRIMARY * when TTE . mcd is not set for the VA , is also vectored into * kerbel by HV as data access exception with fault type set to * HV_FAULT_TYPE_INV_ASI . switch (type) {case HV_FAULT_TYPE_INV_ASI:void __user *)addr);break ;case HV_FAULT_TYPE_MCD_DIS:void __user *)addr);break ;default :void __user *)addr);break ;void sun4v_data_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long if (notify_die(DIE_TRAP_TL1, "data access exception tl1" , regs,0 , 0 x8, SIGTRAP) == NOTIFY_STOP)return ;struct tl1_traplog *)(regs + 1 ));#ifdef CONFIG_PCI#include "pci_impl.h" #endif /* When access exceptions happen, we must do this. */ static void spitfire_clean_and_reenable_l1_caches(void )unsigned long va;if (tlb_type != spitfire)/* Clean 'em. */ for (va = 0 ; va < (PAGE_SIZE << 1 ); va += 32 ) {0 x0);0 x0);/* Re-enable in LSU. */ "flush %%g6\n\t" "membar #Sync\n\t" "stxa %0, [%%g0] %1\n\t" "membar #Sync" /* no outputs */ "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |"i" (ASI_LSU_CONTROL)"memory" );static void spitfire_enable_estate_errors(void )"stxa %0, [%%g0] %1\n\t" "membar #Sync" /* no outputs */ "r" (ESTATE_ERR_ALL),"i" (ASI_ESTATE_ERROR_EN));static char ecc_syndrome_table[] = {0 x4c, 0 x40, 0 x41, 0 x48, 0 x42, 0 x48, 0 x48, 0 x49,0 x43, 0 x48, 0 x48, 0 x49, 0 x48, 0 x49, 0 x49, 0 x4a,0 x44, 0 x48, 0 x48, 0 x20, 0 x48, 0 x39, 0 x4b, 0 x48,0 x48, 0 x25, 0 x31, 0 x48, 0 x28, 0 x48, 0 x48, 0 x2c,0 x45, 0 x48, 0 x48, 0 x21, 0 x48, 0 x3d, 0 x04, 0 x48,0 x48, 0 x4b, 0 x35, 0 x48, 0 x2d, 0 x48, 0 x48, 0 x29,0 x48, 0 x00, 0 x01, 0 x48, 0 x0a, 0 x48, 0 x48, 0 x4b,0 x0f, 0 x48, 0 x48, 0 x4b, 0 x48, 0 x49, 0 x49, 0 x48,0 x46, 0 x48, 0 x48, 0 x2a, 0 x48, 0 x3b, 0 x27, 0 x48,0 x48, 0 x4b, 0 x33, 0 x48, 0 x22, 0 x48, 0 x48, 0 x2e,0 x48, 0 x19, 0 x1d, 0 x48, 0 x1b, 0 x4a, 0 x48, 0 x4b,0 x1f, 0 x48, 0 x4a, 0 x4b, 0 x48, 0 x4b, 0 x4b, 0 x48,0 x48, 0 x4b, 0 x24, 0 x48, 0 x07, 0 x48, 0 x48, 0 x36,0 x4b, 0 x48, 0 x48, 0 x3e, 0 x48, 0 x30, 0 x38, 0 x48,0 x49, 0 x48, 0 x48, 0 x4b, 0 x48, 0 x4b, 0 x16, 0 x48,0 x48, 0 x12, 0 x4b, 0 x48, 0 x49, 0 x48, 0 x48, 0 x4b,0 x47, 0 x48, 0 x48, 0 x2f, 0 x48, 0 x3f, 0 x4b, 0 x48,0 x48, 0 x06, 0 x37, 0 x48, 0 x23, 0 x48, 0 x48, 0 x2b,0 x48, 0 x05, 0 x4b, 0 x48, 0 x4b, 0 x48, 0 x48, 0 x32,0 x26, 0 x48, 0 x48, 0 x3a, 0 x48, 0 x34, 0 x3c, 0 x48,0 x48, 0 x11, 0 x15, 0 x48, 0 x13, 0 x4a, 0 x48, 0 x4b,0 x17, 0 x48, 0 x4a, 0 x4b, 0 x48, 0 x4b, 0 x4b, 0 x48,0 x49, 0 x48, 0 x48, 0 x4b, 0 x48, 0 x4b, 0 x1e, 0 x48,0 x48, 0 x1a, 0 x4b, 0 x48, 0 x49, 0 x48, 0 x48, 0 x4b,0 x48, 0 x08, 0 x0d, 0 x48, 0 x02, 0 x48, 0 x48, 0 x49,0 x03, 0 x48, 0 x48, 0 x49, 0 x48, 0 x4b, 0 x4b, 0 x48,0 x49, 0 x48, 0 x48, 0 x49, 0 x48, 0 x4b, 0 x10, 0 x48,0 x48, 0 x14, 0 x4b, 0 x48, 0 x4b, 0 x48, 0 x48, 0 x4b,0 x49, 0 x48, 0 x48, 0 x49, 0 x48, 0 x4b, 0 x18, 0 x48,0 x48, 0 x1c, 0 x4b, 0 x48, 0 x4b, 0 x48, 0 x48, 0 x4b,0 x4a, 0 x0c, 0 x09, 0 x48, 0 x0e, 0 x48, 0 x48, 0 x4b,0 x0b, 0 x48, 0 x48, 0 x4b, 0 x48, 0 x4b, 0 x4b, 0 x4astatic char *syndrome_unknown = "<Unknown>" ;static void spitfire_log_udb_syndrome(unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long bit)unsigned short scode;char memmod_str[64 ], *p;if (udbl & bit) {0 xff];if (sprintf_dimm(scode, afar, memmod_str, sizeof (memmod_str)) < 0 )else "CPU[%d]: UDBL Syndrome[%x] " "Memory Module \" %s\"\n" ,if (udbh & bit) {0 xff];if (sprintf_dimm(scode, afar, memmod_str, sizeof (memmod_str)) < 0 )else "CPU[%d]: UDBH Syndrome[%x] " "Memory Module \" %s\"\n" ,static void spitfire_cee_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, int tl1, struct pt_regs *regs)"CPU[%d]: Correctable ECC Error " "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx] TL>1[%d]\n" ,/* We always log it, even if someone is listening for this * trap . "Correctable ECC Error" , regs,0 , TRAP_TYPE_CEE, SIGTRAP);/* The Correctable ECC Error trap does not disable I/D caches. So * we only have to restore the ESTATE Error Enable register . static void spitfire_ue_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long tt, int tl1, struct pt_regs *regs)"CPU[%d]: Uncorrectable Error AFSR[%lx] " "AFAR[%lx] UDBL[%lx] UDBH[%ld] TT[%lx] TL>1[%d]\n" ,/* XXX add more human friendly logging of the error status * XXX as is implemented for cheetah /* We always log it, even if someone is listening for this * trap . "Uncorrectable Error" , regs,0 , tt, SIGTRAP);if (regs->tstate & TSTATE_PRIV) {if (tl1)struct tl1_traplog *)(regs + 1 ));"UE" , regs);/* XXX need more intelligent processing here, such as is implemented * XXX for cheetah errors , in fact if the E - cache still holds the * XXX line with bad parity this will loop if (test_thread_flag(TIF_32BIT)) {0 xffffffff;0 xffffffff;void *)0 );void spitfire_access_error(struct pt_regs *regs, unsigned long status_encoded, unsigned long unsigned long afsr, tt, udbh, udbl;int tl1;1 : 0 ;#ifdef CONFIG_PCIif (tt == TRAP_TYPE_DAE &&1 ;4 ;return ;#endif if (afsr & SFAFSR_UE)if (tt == TRAP_TYPE_CEE) {/* Handle the case where we took a CEE trap, but ACK'd * only the UE state in the UDB error registers . if (afsr & SFAFSR_UE) {if (udbh & UDBE_CE) {"stxa %0, [%1] %2\n\t" "membar #Sync" /* no outputs */ "r" (udbh & UDBE_CE),"r" (0 x0), "i" (ASI_UDB_ERROR_W));if (udbl & UDBE_CE) {"stxa %0, [%1] %2\n\t" "membar #Sync" /* no outputs */ "r" (udbl & UDBE_CE),"r" (0 x18), "i" (ASI_UDB_ERROR_W));int cheetah_pcache_forced_on;void cheetah_enable_pcache(void )unsigned long dcr;"CHEETAH: Enabling P-Cache on cpu %d.\n" ,"ldxa [%%g0] %1, %0" "=r" (dcr)"i" (ASI_DCU_CONTROL_REG));"stxa %0, [%%g0] %1\n\t" "membar #Sync" /* no outputs */ "r" (dcr), "i" (ASI_DCU_CONTROL_REG));/* Cheetah error trap handling. */ static unsigned long ecache_flush_physbase;static unsigned long ecache_flush_linesize;static unsigned long ecache_flush_size;/* This table is ordered in priority of errors and matches the * AFAR overwrite policy as well . struct afsr_error_table {unsigned long mask;const char *name;static const char CHAFSR_PERR_msg[] ="System interface protocol error" ;static const char CHAFSR_IERR_msg[] ="Internal processor error" ;static const char CHAFSR_ISAP_msg[] ="System request parity error on incoming address" ;static const char CHAFSR_UCU_msg[] ="Uncorrectable E-cache ECC error for ifetch/data" ;static const char CHAFSR_UCC_msg[] ="SW Correctable E-cache ECC error for ifetch/data" ;static const char CHAFSR_UE_msg[] ="Uncorrectable system bus data ECC error for read" ;static const char CHAFSR_EDU_msg[] ="Uncorrectable E-cache ECC error for stmerge/blkld" ;static const char CHAFSR_EMU_msg[] ="Uncorrectable system bus MTAG error" ;static const char CHAFSR_WDU_msg[] ="Uncorrectable E-cache ECC error for writeback" ;static const char CHAFSR_CPU_msg[] ="Uncorrectable ECC error for copyout" ;static const char CHAFSR_CE_msg[] ="HW corrected system bus data ECC error for read" ;static const char CHAFSR_EDC_msg[] ="HW corrected E-cache ECC error for stmerge/blkld" ;static const char CHAFSR_EMC_msg[] ="HW corrected system bus MTAG ECC error" ;static const char CHAFSR_WDC_msg[] ="HW corrected E-cache ECC error for writeback" ;static const char CHAFSR_CPC_msg[] ="HW corrected ECC error for copyout" ;static const char CHAFSR_TO_msg[] ="Unmapped error from system bus" ;static const char CHAFSR_BERR_msg[] ="Bus error response from system bus" ;static const char CHAFSR_IVC_msg[] ="HW corrected system bus data ECC error for ivec read" ;static const char CHAFSR_IVU_msg[] ="Uncorrectable system bus data ECC error for ivec read" ;static struct afsr_error_table __cheetah_error_table[] = {/* These two do not update the AFAR. */ 0 , NULL },static const char CHPAFSR_DTO_msg[] ="System bus unmapped error for prefetch/storequeue-read" ;static const char CHPAFSR_DBERR_msg[] ="System bus error for prefetch/storequeue-read" ;static const char CHPAFSR_THCE_msg[] ="Hardware corrected E-cache Tag ECC error" ;static const char CHPAFSR_TSCE_msg[] ="SW handled correctable E-cache Tag ECC error" ;static const char CHPAFSR_TUE_msg[] ="Uncorrectable E-cache Tag ECC error" ;static const char CHPAFSR_DUE_msg[] ="System bus uncorrectable data ECC error due to prefetch/store-fill" ;static struct afsr_error_table __cheetah_plus_error_table[] = {/* These two do not update the AFAR. */ 0 , NULL },static const char JPAFSR_JETO_msg[] ="System interface protocol error, hw timeout caused" ;static const char JPAFSR_SCE_msg[] ="Parity error on system snoop results" ;static const char JPAFSR_JEIC_msg[] ="System interface protocol error, illegal command detected" ;static const char JPAFSR_JEIT_msg[] ="System interface protocol error, illegal ADTYPE detected" ;static const char JPAFSR_OM_msg[] ="Out of range memory error has occurred" ;static const char JPAFSR_ETP_msg[] ="Parity error on L2 cache tag SRAM" ;static const char JPAFSR_UMS_msg[] ="Error due to unsupported store" ;static const char JPAFSR_RUE_msg[] ="Uncorrectable ECC error from remote cache/memory" ;static const char JPAFSR_RCE_msg[] ="Correctable ECC error from remote cache/memory" ;static const char JPAFSR_BP_msg[] ="JBUS parity error on returned read data" ;static const char JPAFSR_WBP_msg[] ="JBUS parity error on data for writeback or block store" ;static const char JPAFSR_FRC_msg[] ="Foreign read to DRAM incurring correctable ECC error" ;static const char JPAFSR_FRU_msg[] ="Foreign read to DRAM incurring uncorrectable ECC error" ;static struct afsr_error_table __jalapeno_error_table[] = {/* These two do not update the AFAR. */ 0 , NULL },static struct afsr_error_table *cheetah_error_table;static unsigned long cheetah_afsr_errors;struct cheetah_err_info *cheetah_error_log;static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)struct cheetah_err_info *p;int cpu = smp_processor_id();if (!cheetah_error_log)return NULL;2 );if ((afsr & CHAFSR_TL1) != 0 UL)return p;extern unsigned int tl0_icpe[], tl1_icpe[];extern unsigned int tl0_dcpe[], tl1_dcpe[];extern unsigned int tl0_fecc[], tl1_fecc[];extern unsigned int tl0_cee[], tl1_cee[];extern unsigned int tl0_iae[], tl1_iae[];extern unsigned int tl0_dae[], tl1_dae[];extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];void __init cheetah_ecache_flush_init(void )unsigned long largest_size, smallest_linesize, order, ver;int i, sz;/* Scan all cpu device tree nodes, note two values: * 1 ) largest E - cache size * 2 ) smallest E - cache line size 0 UL;0 UL;for (i = 0 ; i < NR_CPUS; i++) {unsigned long val;if (!val)continue ;if (val > largest_size)if (val < smallest_linesize)if (largest_size == 0 UL || smallest_linesize == ~0 UL) {"cheetah_ecache_flush_init: Cannot probe cpu E-cache " "parameters.\n" );2 * largest_size);if (ecache_flush_physbase == ~0 UL) {"cheetah_ecache_flush_init: Cannot find %ld byte " "contiguous physical memory.\n" ,/* Now allocate error trap reporting scoreboard. */ 2 * sizeof (struct cheetah_err_info));for (order = 0 ; order < NR_PAGE_ORDERS; order++) {if ((PAGE_SIZE << order) >= sz)break ;struct cheetah_err_info *)if (!cheetah_error_log) {"cheetah_ecache_flush_init: Failed to allocate " "error logging scoreboard (%d bytes).\n" , sz);0 , PAGE_SIZE << order);/* Mark all AFSRs as invalid so that the trap handler will * log new new information there . for (i = 0 ; i < 2 * NR_CPUS; i++)"rdpr %%ver, %0" : "=r" (ver));if ((ver >> 32 ) == __JALAPENO_ID ||32 ) == __SERRANO_ID) {0 ];else if ((ver >> 32 ) == 0 x003e0015) {0 ];else {0 ];/* Now patch trap tables. */ 8 * 4 ));8 * 4 ));8 * 4 ));8 * 4 ));8 * 4 ));8 * 4 ));8 * 4 ));8 * 4 ));if (tlb_type == cheetah_plus) {8 * 4 ));8 * 4 ));8 * 4 ));8 * 4 ));static void cheetah_flush_ecache(void )unsigned long flush_base = ecache_flush_physbase;unsigned long flush_linesize = ecache_flush_linesize;unsigned long flush_size = ecache_flush_size;"1: subcc %0, %4, %0\n\t" " bne,pt %%xcc, 1b\n\t" " ldxa [%2 + %0] %3, %%g0\n\t" "=&r" (flush_size)"0" (flush_size), "r" (flush_base),"i" (ASI_PHYS_USE_EC), "r" (flush_linesize));static void cheetah_flush_ecache_line(unsigned long physaddr)unsigned long alias;8 UL - 1 UL);1 UL) - 1 UL)));1 UL);"ldxa [%0] %2, %%g0\n\t" "ldxa [%1] %2, %%g0\n\t" "membar #Sync" /* no outputs */ "r" (physaddr), "r" (alias),"i" (ASI_PHYS_USE_EC));/* Unfortunately, the diagnostic access to the I-cache tags we need to * use to clear the thing interferes with I - cache coherency transactions . * * So we must only flush the I - cache when it is disabled . static void __cheetah_flush_icache(void )unsigned int icache_size, icache_line_size;unsigned long addr;/* Clear the valid bits in all the tags. */ for (addr = 0 ; addr < icache_size; addr += icache_line_size) {"stxa %%g0, [%0] %1\n\t" "membar #Sync" /* no outputs */ "r" (addr | (2 << 3 )),"i" (ASI_IC_TAG));static void cheetah_flush_icache(void )unsigned long dcu_save;/* Save current DCU, disable I-cache. */ "ldxa [%%g0] %1, %0\n\t" "or %0, %2, %%g1\n\t" "stxa %%g1, [%%g0] %1\n\t" "membar #Sync" "=r" (dcu_save)"i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)"g1" );/* Restore DCU register */ "stxa %0, [%%g0] %1\n\t" "membar #Sync" /* no outputs */ "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));static void cheetah_flush_dcache(void )unsigned int dcache_size, dcache_line_size;unsigned long addr;for (addr = 0 ; addr < dcache_size; addr += dcache_line_size) {"stxa %%g0, [%0] %1\n\t" "membar #Sync" /* no outputs */ "r" (addr), "i" (ASI_DCACHE_TAG));/* In order to make the even parity correct we must do two things. * First , we clear DC_data_parity and set DC_utag to an appropriate value . * Next , we clear out all 32 - bytes of data for that line . Data of * all - zero + tag parity value of zero = = correct parity . static void cheetah_plus_zap_dcache_parity(void )unsigned int dcache_size, dcache_line_size;unsigned long addr;for (addr = 0 ; addr < dcache_size; addr += dcache_line_size) {unsigned long tag = (addr >> 14 );unsigned long line;"membar #Sync\n\t" "stxa %0, [%1] %2\n\t" "membar #Sync" /* no outputs */ "r" (tag), "r" (addr),"i" (ASI_DCACHE_UTAG));for (line = addr; line < addr + dcache_line_size; line += 8 )"membar #Sync\n\t" "stxa %%g0, [%0] %1\n\t" "membar #Sync" /* no outputs */ "r" (line),"i" (ASI_DCACHE_DATA));/* Conversion tables used to frob Cheetah AFSR syndrome values into * something palatable to the memory controller driver get_unumber * routine . #define MT0 137 #define MT1 138 #define MT2 139 #define NONE 254 #define MTC0 140 #define MTC1 141 #define MTC2 142 #define MTC3 143 #define C0 128 #define C1 129 #define C2 130 #define C3 131 #define C4 132 #define C5 133 #define C6 134 #define C7 135 #define C8 136 #define M2 144 #define M3 145 #define M4 146 #define M 147 static unsigned char cheetah_ecc_syntab[] = {/*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M, /*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16, /*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10, /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M, /*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6, /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4, /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4, /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3, /*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5, /*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M, /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2, /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3, /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M, /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3, /*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M, /*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M, /*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4, /*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M, /*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2, /*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M, /*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4, /*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3, /*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3, /*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2, /*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4, /*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M, /*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3, /*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M, /*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3, /*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M, /*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M, /*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M static unsigned char cheetah_mtag_syntab[] = {/* Return the highest priority error conditon mentioned. */ static inline unsigned long cheetah_get_hipri(unsigned long afsr)unsigned long tmp = 0 ;int i;for (i = 0 ; cheetah_error_table[i].mask; i++) {if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0 UL)return tmp;return tmp;static const char *cheetah_get_string(unsigned long bit)int i;for (i = 0 ; cheetah_error_table[i].mask; i++) {if ((bit & cheetah_error_table[i].mask) != 0 UL)return cheetah_error_table[i].name;return "???" ;static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,unsigned long afsr, unsigned long afar, int recoverable)unsigned long hipri;char unum[256 ];"%s" "ERROR(%d): Cheetah error trap taken afsr[%016lx] afar[%016lx] TL1(%d)\n" ,1 : 0 );"%s" "ERROR(%d): TPC[%lx] TNPC[%lx] O7[%lx] TSTATE[%lx]\n" ,"%s" "ERROR(%d): " ,"TPC<%pS>\n" , (void *) regs->tpc);"%s" "ERROR(%d): M_SYND(%lx), E_SYND(%lx)%s%s\n" ,", Multiple Errors" : "" ,", Privileged" : "" );"%s" "ERROR(%d): Highest priority error (%016lx) \" %s\"\n" ,/* Try to get unumber if relevant. */ #define ESYND_ERRORS (CHAFSR_IVC | CHAFSR_IVU | \#define MSYND_ERRORS (CHAFSR_EMC | CHAFSR_EMU)if (afsr & ESYND_ERRORS) {int syndrome;int ret;sizeof (unum));if (ret != -1 )"%s" "ERROR(%d): AFAR E-syndrome [%s]\n" ,else if (afsr & MSYND_ERRORS) {int syndrome;int ret;sizeof (unum));if (ret != -1 )"%s" "ERROR(%d): AFAR M-syndrome [%s]\n" ,/* Now dump the cache snapshots. */ "%s" "ERROR(%d): D-cache idx[%x] tag[%016llx] utag[%016llx] stag[%016llx]\n" ,int ) info->dcache_index,"%s" "ERROR(%d): D-cache data0[%016llx] data1[%016llx] data2[%016llx] data3[%016llx]\n" ,0 ],1 ],2 ],3 ]);"%s" "ERROR(%d): I-cache idx[%x] tag[%016llx] utag[%016llx] stag[%016llx] " "u[%016llx] l[%016llx]\n" ,int ) info->icache_index,"%s" "ERROR(%d): I-cache INSN0[%016llx] INSN1[%016llx] INSN2[%016llx] INSN3[%016llx]\n" ,0 ],1 ],2 ],3 ]);"%s" "ERROR(%d): I-cache INSN4[%016llx] INSN5[%016llx] INSN6[%016llx] INSN7[%016llx]\n" ,4 ],5 ],6 ],7 ]);"%s" "ERROR(%d): E-cache idx[%x] tag[%016llx]\n" ,int ) info->ecache_index, info->ecache_tag);"%s" "ERROR(%d): E-cache data0[%016llx] data1[%016llx] data2[%016llx] data3[%016llx]\n" ,0 ],1 ],2 ],3 ]);while (afsr != 0 UL) {unsigned long bit = cheetah_get_hipri(afsr);"%s" "ERROR: Multiple-error (%016lx) \" %s\"\n" ,if (!recoverable)"ERROR: This condition is not recoverable.\n" );static int cheetah_recheck_errors(struct cheetah_err_info *logp)unsigned long afsr, afar;int ret = 0 ;"ldxa [%%g0] %1, %0\n\t" "=r" (afsr)"i" (ASI_AFSR));if ((afsr & cheetah_afsr_errors) != 0 ) {if (logp != NULL) {"ldxa [%%g0] %1, %0\n\t" "=r" (afar)"i" (ASI_AFAR));1 ;"stxa %0, [%%g0] %1\n\t" "membar #Sync\n\t" "r" (afsr), "i" (ASI_AFSR));return ret;void cheetah_fecc_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)struct cheetah_err_info local_snapshot, *p;int recoverable;/* Flush E-cache */ if (!p) {"ERROR: Early Fast-ECC error afsr[%016lx] afar[%016lx]\n" ,"ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n" ,/* Grab snapshot of logged error. */ sizeof (local_snapshot));/* If the current trap snapshot does not match what the * trap handler passed along into our args , big trouble . * In such a case , mark the local copy as invalid . * * Else , it matches and we mark the afsr in the non - local * copy as invalid so we may log new error traps there . if (p->afsr != afsr || p->afar != afar)else /* Re-enable I-cache/D-cache */ "ldxa [%%g0] %0, %%g1\n\t" "or %%g1, %1, %%g1\n\t" "stxa %%g1, [%%g0] %0\n\t" "membar #Sync" /* no outputs */ "i" (ASI_DCU_CONTROL_REG),"i" (DCU_DC | DCU_IC)"g1" );/* Re-enable error reporting */ "ldxa [%%g0] %0, %%g1\n\t" "or %%g1, %1, %%g1\n\t" "stxa %%g1, [%%g0] %0\n\t" "membar #Sync" /* no outputs */ "i" (ASI_ESTATE_ERROR_EN),"i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)"g1" );/* Decide if we can continue after handling this trap and * logging the error . 1 ;if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))0 ;/* Re-check AFSR/AFAR. What we are looking for here is whether a new * error was logged while we had error reporting traps disabled . if (cheetah_recheck_errors(&local_snapshot)) {unsigned long new_afsr = local_snapshot.afsr;/* If we got a new asynchronous error, die... */ if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |0 ;/* Log errors. */ if (!recoverable)"Irrecoverable Fast-ECC error trap.\n" );/* Flush E-cache to kick the error trap handlers out. */ /* Try to fix a correctable error by pushing the line out from * the E - cache . Recheck error reporting registers to see if the * problem is intermittent . static int cheetah_fix_ce(unsigned long physaddr)unsigned long orig_estate;unsigned long alias1, alias2;int ret;/* Make sure correctable error traps are disabled. */ "ldxa [%%g0] %2, %0\n\t" "andn %0, %1, %%g1\n\t" "stxa %%g1, [%%g0] %2\n\t" "membar #Sync" "=&r" (orig_estate)"i" (ESTATE_ERROR_CEEN),"i" (ASI_ESTATE_ERROR_EN)"g1" );/* We calculate alias addresses that will force the * cache line in question out of the E - cache . Then * we bring it back in with an atomic instruction so * that we get it in some modified / exclusive state , * then we displace it again to try and get proper ECC * pushed back into the system . 8 UL - 1 UL);1 ) - 1 )));1 );"ldxa [%0] %3, %%g0\n\t" "ldxa [%1] %3, %%g0\n\t" "casxa [%2] %3, %%g0, %%g0\n\t" "ldxa [%0] %3, %%g0\n\t" "ldxa [%1] %3, %%g0\n\t" "membar #Sync" /* no outputs */ "r" (alias1), "r" (alias2),"r" (physaddr), "i" (ASI_PHYS_USE_EC));/* Did that trigger another error? */ if (cheetah_recheck_errors(NULL)) {/* Try one more time. */ "ldxa [%0] %1, %%g0\n\t" "membar #Sync" "r" (physaddr), "i" (ASI_PHYS_USE_EC));if (cheetah_recheck_errors(NULL))2 ;else 1 ;else {/* No new error, intermittent problem. */ 0 ;/* Restore error enables. */ "stxa %0, [%%g0] %1\n\t" "membar #Sync" "r" (orig_estate), "i" (ASI_ESTATE_ERROR_EN));return ret;/* Return non-zero if PADDR is a valid physical memory address. */ static int cheetah_check_main_memory(unsigned long paddr)unsigned long vaddr = PAGE_OFFSET + paddr;if (vaddr > (unsigned long ) high_memory)return 0 ;return kern_addr_valid(vaddr);void cheetah_cee_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)struct cheetah_err_info local_snapshot, *p;int recoverable, is_memory;if (!p) {"ERROR: Early CEE error afsr[%016lx] afar[%016lx]\n" ,"ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n" ,/* Grab snapshot of logged error. */ sizeof (local_snapshot));/* If the current trap snapshot does not match what the * trap handler passed along into our args , big trouble . * In such a case , mark the local copy as invalid . * * Else , it matches and we mark the afsr in the non - local * copy as invalid so we may log new error traps there . if (p->afsr != afsr || p->afar != afar)else if (is_memory && (afsr & CHAFSR_CE) != 0 UL) {/* XXX Might want to log the results of this operation * XXX somewhere . . . - DaveM int flush_all, flush_line;0 ;if ((afsr & CHAFSR_EDC) != 0 UL) {if ((afsr & cheetah_afsr_errors) == CHAFSR_EDC)1 ;else 1 ;else if ((afsr & CHAFSR_CPC) != 0 UL) {if ((afsr & cheetah_afsr_errors) == CHAFSR_CPC)1 ;else 1 ;/* Trap handler only disabled I-cache, flush it. */ /* Re-enable I-cache */ "ldxa [%%g0] %0, %%g1\n\t" "or %%g1, %1, %%g1\n\t" "stxa %%g1, [%%g0] %0\n\t" "membar #Sync" /* no outputs */ "i" (ASI_DCU_CONTROL_REG),"i" (DCU_IC)"g1" );if (flush_all)else if (flush_line)/* Re-enable error reporting */ "ldxa [%%g0] %0, %%g1\n\t" "or %%g1, %1, %%g1\n\t" "stxa %%g1, [%%g0] %0\n\t" "membar #Sync" /* no outputs */ "i" (ASI_ESTATE_ERROR_EN),"i" (ESTATE_ERROR_CEEN)"g1" );/* Decide if we can continue after handling this trap and * logging the error . 1 ;if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))0 ;/* Re-check AFSR/AFAR */ void ) cheetah_recheck_errors(&local_snapshot);/* Log errors. */ if (!recoverable)"Irrecoverable Correctable-ECC error trap.\n" );void cheetah_deferred_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)struct cheetah_err_info local_snapshot, *p;int recoverable, is_memory;#ifdef CONFIG_PCI/* Check for the special PCI poke sequence. */ if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {/* Re-enable I-cache/D-cache */ "ldxa [%%g0] %0, %%g1\n\t" "or %%g1, %1, %%g1\n\t" "stxa %%g1, [%%g0] %0\n\t" "membar #Sync" /* no outputs */ "i" (ASI_DCU_CONTROL_REG),"i" (DCU_DC | DCU_IC)"g1" );/* Re-enable error reporting */ "ldxa [%%g0] %0, %%g1\n\t" "or %%g1, %1, %%g1\n\t" "stxa %%g1, [%%g0] %0\n\t" "membar #Sync" /* no outputs */ "i" (ASI_ESTATE_ERROR_EN),"i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)"g1" );void ) cheetah_recheck_errors(NULL);1 ;4 ;4 ;return ;#endif if (!p) {"ERROR: Early deferred error afsr[%016lx] afar[%016lx]\n" ,"ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n" ,/* Grab snapshot of logged error. */ sizeof (local_snapshot));/* If the current trap snapshot does not match what the * trap handler passed along into our args , big trouble . * In such a case , mark the local copy as invalid . * * Else , it matches and we mark the afsr in the non - local * copy as invalid so we may log new error traps there . if (p->afsr != afsr || p->afar != afar)else int flush_all, flush_line;0 ;if ((afsr & CHAFSR_EDU) != 0 UL) {if ((afsr & cheetah_afsr_errors) == CHAFSR_EDU)1 ;else 1 ;else if ((afsr & CHAFSR_BERR) != 0 UL) {if ((afsr & cheetah_afsr_errors) == CHAFSR_BERR)1 ;else 1 ;/* Re-enable I/D caches */ "ldxa [%%g0] %0, %%g1\n\t" "or %%g1, %1, %%g1\n\t" "stxa %%g1, [%%g0] %0\n\t" "membar #Sync" /* no outputs */ "i" (ASI_DCU_CONTROL_REG),"i" (DCU_IC | DCU_DC)"g1" );if (flush_all)else if (flush_line)/* Re-enable error reporting */ "ldxa [%%g0] %0, %%g1\n\t" "or %%g1, %1, %%g1\n\t" "stxa %%g1, [%%g0] %0\n\t" "membar #Sync" /* no outputs */ "i" (ASI_ESTATE_ERROR_EN),"i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)"g1" );/* Decide if we can continue after handling this trap and * logging the error . 1 ;if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))0 ;/* Re-check AFSR/AFAR. What we are looking for here is whether a new * error was logged while we had error reporting traps disabled . if (cheetah_recheck_errors(&local_snapshot)) {unsigned long new_afsr = local_snapshot.afsr;/* If we got a new asynchronous error, die... */ if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |0 ;/* Log errors. */ /* "Recoverable" here means we try to yank the page from ever * being newly used again . This depends upon a few things : * 1 ) Must be main memory , and AFAR must be valid . * 2 ) If we trapped from user , OK . * 3 ) Else , if we trapped from kernel we must find exception * table entry ( ie . we have to have been accessing user * space ) . * * If AFAR is not in main memory , or we trapped from kernel * and cannot find an exception table entry , it is unacceptable * to try and continue . if (recoverable && is_memory) {if ((regs->tstate & TSTATE_PRIV) == 0 UL) {/* OK, usermode access. */ 1 ;else {const struct exception_table_entry *entry;if (entry) {/* OK, kernel access to userspace. */ 1 ;else {/* BAD, privileged state is corrupted. */ 0 ;if (recoverable) {if (pfn_valid(afar >> PAGE_SHIFT))else 0 ;/* Only perform fixup if we still have a * recoverable condition . if (recoverable) {4 ;else {0 ;if (!recoverable)"Irrecoverable deferred error trap.\n" );/* Handle a D/I cache parity error trap. TYPE is encoded as: * * Bit0 : 0 = dcache , 1 = icache * Bit1 : 0 = recoverable , 1 = unrecoverable * * The hardware has disabled both the I - cache and D - cache in * the % dcr register . void cheetah_plus_parity_error(int type, struct pt_regs *regs)if (type & 0 x1)else /* Re-enable I-cache/D-cache */ "ldxa [%%g0] %0, %%g1\n\t" "or %%g1, %1, %%g1\n\t" "stxa %%g1, [%%g0] %0\n\t" "membar #Sync" /* no outputs */ "i" (ASI_DCU_CONTROL_REG),"i" (DCU_DC | DCU_IC)"g1" );if (type & 0 x2) {"CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n" ,0 x1) ? 'I' : 'D' ,"TPC<%pS>\n" , (void *) regs->tpc);"Irrecoverable Cheetah+ parity error." );"CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n" ,0 x1) ? 'I' : 'D' ,"TPC<%pS>\n" , (void *) regs->tpc);struct sun4v_error_entry {/* Unique error handle */ /*0x00*/u64 err_handle; /* %stick value at the time of the error */ /*0x08*/u64 err_stick; /*0x10*/u8 reserved_1[3]; /* Error type */ /*0x13*/u8 err_type; #define SUN4V_ERR_TYPE_UNDEFINED 0 #define SUN4V_ERR_TYPE_UNCORRECTED_RES 1 #define SUN4V_ERR_TYPE_PRECISE_NONRES 2 #define SUN4V_ERR_TYPE_DEFERRED_NONRES 3 #define SUN4V_ERR_TYPE_SHUTDOWN_RQST 4 #define SUN4V_ERR_TYPE_DUMP_CORE 5 #define SUN4V_ERR_TYPE_SP_STATE_CHANGE 6 #define SUN4V_ERR_TYPE_NUM 7 /* Error attributes */ /*0x14*/u32 err_attrs; #define SUN4V_ERR_ATTRS_PROCESSOR 0 x00000001#define SUN4V_ERR_ATTRS_MEMORY 0 x00000002#define SUN4V_ERR_ATTRS_PIO 0 x00000004#define SUN4V_ERR_ATTRS_INT_REGISTERS 0 x00000008#define SUN4V_ERR_ATTRS_FPU_REGISTERS 0 x00000010#define SUN4V_ERR_ATTRS_SHUTDOWN_RQST 0 x00000020#define SUN4V_ERR_ATTRS_ASR 0 x00000040#define SUN4V_ERR_ATTRS_ASI 0 x00000080#define SUN4V_ERR_ATTRS_PRIV_REG 0 x00000100#define SUN4V_ERR_ATTRS_SPSTATE_MSK 0 x00000600#define SUN4V_ERR_ATTRS_MCD 0 x00000800#define SUN4V_ERR_ATTRS_SPSTATE_SHFT 9 #define SUN4V_ERR_ATTRS_MODE_MSK 0 x03000000#define SUN4V_ERR_ATTRS_MODE_SHFT 24 #define SUN4V_ERR_ATTRS_RES_QUEUE_FULL 0 x80000000#define SUN4V_ERR_SPSTATE_FAULTED 0 #define SUN4V_ERR_SPSTATE_AVAILABLE 1 #define SUN4V_ERR_SPSTATE_NOT_PRESENT 2 #define SUN4V_ERR_MODE_USER 1 #define SUN4V_ERR_MODE_PRIV 2 /* Real address of the memory region or PIO transaction */ /*0x18*/u64 err_raddr; /* Size of the operation triggering the error, in bytes */ /*0x20*/u32 err_size; /* ID of the CPU */ /*0x24*/u16 err_cpu; /* Grace periof for shutdown, in seconds */ /*0x26*/u16 err_secs; /* Value of the %asi register */ /*0x28*/u8 err_asi; /*0x29*/u8 reserved_2; /* Value of the ASR register number */ /*0x2a*/u16 err_asr; #define SUN4V_ERR_ASR_VALID 0 x8000/*0x2c*/u32 reserved_3; /*0x30*/u64 reserved_4; /*0x38*/u64 reserved_5; static atomic_t sun4v_resum_oflow_cnt = ATOMIC_INIT(0 );static atomic_t sun4v_nonresum_oflow_cnt = ATOMIC_INIT(0 );static const char *sun4v_err_type_to_str(u8 type)static const char *types[SUN4V_ERR_TYPE_NUM] = {"undefined" ,"uncorrected resumable" ,"precise nonresumable" ,"deferred nonresumable" ,"shutdown request" ,"dump core" ,"SP state change" ,if (type < SUN4V_ERR_TYPE_NUM)return types[type];return "unknown" ;static void sun4v_emit_err_attr_strings(u32 attrs)static const char *attr_names[] = {"processor" ,"memory" ,"PIO" ,"int-registers" ,"fpu-registers" ,"shutdown-request" ,"ASR" ,"ASI" ,"priv-reg" ,static const char *sp_states[] = {"sp-faulted" ,"sp-available" ,"sp-not-present" ,"sp-state-reserved" ,static const char *modes[] = {"mode-reserved0" ,"user" ,"priv" ,"mode-reserved1" ,int i;for (i = 0 ; i < ARRAY_SIZE(attr_names); i++) {if (attrs & (1 U << i)) {const char *s = attr_names[i];"%s " , s);"%s " , sp_states[sp_state]);"%s " , modes[mode]);if (attrs & SUN4V_ERR_ATTRS_RES_QUEUE_FULL)"res-queue-full " );/* When the report contains a real-address of "-1" it means that the * hardware did not provide the address . So we compute the effective * address of the load or store instruction at regs - > tpc and report * that . Usually when this happens it ' s a PIO and in such a case we * are using physical addresses with bypass ASIs anyways , so what we * report here is exactly what we want . static void sun4v_report_real_raddr(const char *pfx, struct pt_regs *regs)unsigned int insn;if (!(regs->tstate & TSTATE_PRIV))return ;unsigned int *) regs->tpc;0 );"%s: insn effective address [0x%016llx]\n" ,static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent,int cpu, const char *pfx, atomic_t *ocnt)int cnt;"%s: Reporting on cpu %d\n" , pfx, cpu);"%s: TPC [0x%016lx] <%pS>\n" ,void *) regs->tpc);"%s: RAW [%016llx:%016llx:%016llx:%016llx\n" ,0 ], raw_ptr[1 ], raw_ptr[2 ], raw_ptr[3 ]);"%s: %016llx:%016llx:%016llx:%016llx]\n" ,4 ], raw_ptr[5 ], raw_ptr[6 ], raw_ptr[7 ]);"%s: handle [0x%016llx] stick [0x%016llx]\n" ,"%s: type [%s]\n" , pfx, sun4v_err_type_to_str(ent->err_type));"%s: attrs [0x%08x] < " , pfx, attrs);">\n" );/* Various fields in the error report are only valid if * certain attribute bits are set . if (attrs & (SUN4V_ERR_ATTRS_MEMORY |"%s: raddr [0x%016llx]\n" , pfx, ent->err_raddr);if (ent->err_raddr == ~(u64)0 )if (attrs & (SUN4V_ERR_ATTRS_MEMORY | SUN4V_ERR_ATTRS_ASI))"%s: size [0x%x]\n" , pfx, ent->err_size);if (attrs & (SUN4V_ERR_ATTRS_PROCESSOR |"%s: cpu[%u]\n" , pfx, ent->err_cpu);if (attrs & SUN4V_ERR_ATTRS_ASI)"%s: asi [0x%02x]\n" , pfx, ent->err_asi);if ((attrs & (SUN4V_ERR_ATTRS_INT_REGISTERS |0 )"%s: reg [0x%04x]\n" ,if ((cnt = atomic_read(ocnt)) != 0 ) {0 );"%s: Queue overflowed %d times.\n" ,/* Handle memory corruption detected error which is vectored in * through resumable error trap . static void do_mcd_err(struct pt_regs *regs, struct sun4v_error_entry ent)if (notify_die(DIE_TRAP, "MCD error" , regs, 0 , 0 x34,return ;if (regs->tstate & TSTATE_PRIV) {/* MCD exception could happen because the task was * running a system call with MCD enabled and passed a * non - versioned pointer or pointer with bad version * tag to the system call . In such cases , hypervisor * places the address of offending instruction in the * resumable error report . This is a deferred error , * so the read / write that caused the trap was potentially * retired long time back and we may have no choice * but to send SIGSEGV to the process . const struct exception_table_entry *entry;if (entry) {/* Looks like a bad syscall parameter */ #ifdef DEBUG_EXCEPTIONS"Exception: PC<%016lx> faddr<UNKNOWN>\n" ,"EX_TABLE: insn<%016lx> fixup<%016lx>\n" ,#endif 4 ;return ;/* Send SIGSEGV to the userspace process with the right signal * code void __user *)ent.err_raddr);/* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate. * Log the event and clear the first word of the entry . void sun4v_resum_error(struct pt_regs *regs, unsigned long offset)enum ctx_state prev_state = exception_enter();struct sun4v_error_entry *ent, local_copy;struct trap_per_cpu *tb;unsigned long paddr;int cpu;sizeof (struct sun4v_error_entry));/* We have a local copy now, so release the entry. */ 0 ;if (local_copy.err_type == SUN4V_ERR_TYPE_SHUTDOWN_RQST) {/* We should really take the seconds field of * the error report and use it for the shutdown * invocation , but for now do the same thing we * do for a DS shutdown request . "Shutdown request, %u seconds...\n" ,true );goto out;/* If this is a memory corruption detected error vectored in * by HV through resumable error trap , call the handler if (local_copy.err_attrs & SUN4V_ERR_ATTRS_MCD) {return ;"RESUMABLE ERROR" ,/* If we try to printk() we'll probably make matters worse, by trying * to retake locks this cpu already holds or causing more errors . So * just bump a counter , and we ' ll report these counter bumps above . void sun4v_resum_overflow(struct pt_regs *regs)/* Given a set of registers, get the virtual addressi that was being accessed * by the faulting instructions at tpc . static unsigned long sun4v_get_vaddr(struct pt_regs *regs)unsigned int insn;if (!copy_from_user(&insn, (void __user *)regs->tpc, 4 )) {return compute_effective_address(regs, insn,25 ) & 0 x1f);return 0 ;/* Attempt to handle non-resumable errors generated from userspace. * Returns true if the signal was handled , false otherwise . static bool sun4v_nonresum_error_user_handled(struct pt_regs *regs,struct sun4v_error_entry *ent)unsigned int attrs = ent->err_attrs;if (attrs & SUN4V_ERR_ATTRS_MEMORY) {unsigned long addr = ent->err_raddr;if (addr == ~(u64)0 ) {/* This seems highly unlikely to ever occur */ "SUN4V NON-RECOVERABLE ERROR: Memory error detected in unknown location!\n" );else {unsigned long page_cnt = DIV_ROUND_UP(ent->err_size,/* Break the unfortunate news. */ "SUN4V NON-RECOVERABLE ERROR: Memory failed at %016lX\n" ,"SUN4V NON-RECOVERABLE ERROR: Claiming %lu ages.\n" ,while (page_cnt-- > 0 ) {if (pfn_valid(addr >> PAGE_SHIFT))return true ;if (attrs & SUN4V_ERR_ATTRS_PIO) {void __user *)sun4v_get_vaddr(regs));return true ;/* Default to doing nothing */ return false ;/* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate. * Log the event , clear the first word of the entry , and die . void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset)struct sun4v_error_entry *ent, local_copy;struct trap_per_cpu *tb;unsigned long paddr;int cpu;sizeof (struct sun4v_error_entry));/* We have a local copy now, so release the entry. */ 0 ;if (!(regs->tstate & TSTATE_PRIV) &&/* DON'T PANIC: This userspace error was handled. */ return ;#ifdef CONFIG_PCI/* Check for the special PCI poke sequence. */ if (pci_poke_in_progress && pci_poke_cpu == cpu) {1 ;4 ;4 ;return ;#endif "NON-RESUMABLE ERROR" ,"Non-resumable error." );/* If we try to printk() we'll probably make matters worse, by trying * to retake locks this cpu already holds or causing more errors . So * just bump a counter , and we ' ll report these counter bumps above . void sun4v_nonresum_overflow(struct pt_regs *regs)/* XXX Actually even this can make not that much sense. Perhaps * XXX we should just pull the plug and panic directly from here ? static void sun4v_tlb_error(struct pt_regs *regs)"TLB/TSB error" , regs);unsigned long sun4v_err_itlb_vaddr;unsigned long sun4v_err_itlb_ctx;unsigned long sun4v_err_itlb_pte;unsigned long sun4v_err_itlb_error;void sun4v_itlb_error_report(struct pt_regs *regs, int tl)struct tl1_traplog *)(regs + 1 ));"SUN4V-ITLB: Error at TPC[%lx], tl %d\n" ,"SUN4V-ITLB: TPC<%pS>\n" , (void *) regs->tpc);"SUN4V-ITLB: O7[%lx]\n" , regs->u_regs[UREG_I7]);"SUN4V-ITLB: O7<%pS>\n" ,void *) regs->u_regs[UREG_I7]);"SUN4V-ITLB: vaddr[%lx] ctx[%lx] " "pte[%lx] error[%lx]\n" ,unsigned long sun4v_err_dtlb_vaddr;unsigned long sun4v_err_dtlb_ctx;unsigned long sun4v_err_dtlb_pte;unsigned long sun4v_err_dtlb_error;void sun4v_dtlb_error_report(struct pt_regs *regs, int tl)struct tl1_traplog *)(regs + 1 ));"SUN4V-DTLB: Error at TPC[%lx], tl %d\n" ,"SUN4V-DTLB: TPC<%pS>\n" , (void *) regs->tpc);"SUN4V-DTLB: O7[%lx]\n" , regs->u_regs[UREG_I7]);"SUN4V-DTLB: O7<%pS>\n" ,void *) regs->u_regs[UREG_I7]);"SUN4V-DTLB: vaddr[%lx] ctx[%lx] " "pte[%lx] error[%lx]\n" ,void hypervisor_tlbop_error(unsigned long err, unsigned long op)"SUN4V: TLB hv call error %lu for op %lu\n" ,void hypervisor_tlbop_error_xcall(unsigned long err, unsigned long op)"SUN4V: XCALL TLB hv call error %lu for op %lu\n" ,static void do_fpe_common(struct pt_regs *regs)if (regs->tstate & TSTATE_PRIV) {4 ;else {unsigned long fsr = current_thread_info()->xfsr[0 ];int code;if (test_thread_flag(TIF_32BIT)) {0 xffffffff;0 xffffffff;if ((fsr & 0 x1c000) == (1 << 14 )) {if (fsr & 0 x10)else if (fsr & 0 x08)else if (fsr & 0 x04)else if (fsr & 0 x02)else if (fsr & 0 x01)void __user *)regs->tpc);void do_fpieee(struct pt_regs *regs)enum ctx_state prev_state = exception_enter();if (notify_die(DIE_TRAP, "fpu exception ieee" , regs,0 , 0 x24, SIGFPE) == NOTIFY_STOP)goto out;void do_fpother(struct pt_regs *regs)enum ctx_state prev_state = exception_enter();struct fpustate *f = FPUSTATE;int ret = 0 ;if (notify_die(DIE_TRAP, "fpu exception other" , regs,0 , 0 x25, SIGFPE) == NOTIFY_STOP)goto out;switch ((current_thread_info()->xfsr[0 ] & 0 x1c000)) {case (2 << 14 ): /* unfinished_FPop */ case (3 << 14 ): /* unimplemented_FPop */ false );break ;if (ret)goto out;void do_tof(struct pt_regs *regs)enum ctx_state prev_state = exception_enter();if (notify_die(DIE_TRAP, "tagged arithmetic overflow" , regs,0 , 0 x26, SIGEMT) == NOTIFY_STOP)goto out;if (regs->tstate & TSTATE_PRIV)"Penguin overflow trap from kernel mode" , regs);if (test_thread_flag(TIF_32BIT)) {0 xffffffff;0 xffffffff;void __user *)regs->tpc);void do_div0(struct pt_regs *regs)enum ctx_state prev_state = exception_enter();if (notify_die(DIE_TRAP, "integer division by zero" , regs,0 , 0 x28, SIGFPE) == NOTIFY_STOP)goto out;if (regs->tstate & TSTATE_PRIV)"TL0: Kernel divide by zero." , regs);if (test_thread_flag(TIF_32BIT)) {0 xffffffff;0 xffffffff;void __user *)regs->tpc);static void instruction_dump(unsigned int *pc)int i;if ((((unsigned long ) pc) & 3 ))return ;"Instruction DUMP:" );for (i = -3 ; i < 6 ; i++)"%c%08x%c" ,i?' ' :'<' ,pc[i],i?' ' :'>' );"\n" );static void user_instruction_dump(unsigned int __user *pc)int i;unsigned int buf[9 ];if ((((unsigned long ) pc) & 3 ))return ;if (copy_from_user(buf, pc - 3 , sizeof (buf)))return ;"Instruction DUMP:" );for (i = 0 ; i < 9 ; i++)"%c%08x%c" ,i==3 ?' ' :'<' ,buf[i],i==3 ?' ' :'>' );"\n" );void show_stack(struct task_struct *tsk, unsigned long *_ksp, const char *loglvl)unsigned long fp, ksp;struct thread_info *tp;int count = 0 ;#ifdef CONFIG_FUNCTION_GRAPH_TRACERint graph = 0 ;#endif unsigned long ) _ksp;if (!tsk)if (ksp == 0 UL) {if (tsk == current)asm ("mov %%fp, %0" : "=r" (ksp));else if (tp == current_thread_info())"%sCall Trace:\n" , loglvl);do {struct sparc_stackf *sf;struct pt_regs *regs;unsigned long pc;if (!kstack_valid(tp, fp))break ;struct sparc_stackf *) fp;struct pt_regs *) (sf + 1 );if (kstack_is_trap_frame(tp, regs)) {if (!(regs->tstate & TSTATE_PRIV))break ;else {unsigned long )sf->fp + STACK_BIAS;#ifdef CONFIG_FUNCTION_GRAPH_TRACERif ((pc + 8 UL) == (unsigned long ) &return_to_handler) {struct ftrace_ret_stack *ret_stack;if (ret_stack) {#endif while (++count < 16 );static inline struct reg_window *kernel_stack_up(struct reg_window *rw)unsigned long fp = rw->ins[6 ];if (!fp)return NULL;return (struct reg_window *) (fp + STACK_BIAS);void __noreturn die_if_kernel(char *str, struct pt_regs *regs)static int die_counter;int count = 0 ;/* Amuse the user. */ " \\|/ ____ \\|/\n" " \" @'/ .. \\`@\"\n" " /_| \\__/ |_\\\n" " \\__U_/\n" );"%s(%d): %s [#%d]\n" , current->comm, task_pid_nr(current), str, ++die_counter);0 , 255 , SIGSEGV);"flushw" );if (regs->tstate & TSTATE_PRIV) {struct thread_info *tp = current_thread_info();struct reg_window *rw = (struct reg_window *)/* Stop the back trace when we hit userland or we * find some badly aligned kernel stack . while (rw &&30 &&unsigned long ) rw)) {"Caller[%016lx]: %pS\n" , rw->ins[7 ],void *) rw->ins[7 ]);unsigned int *) regs->tpc);else {if (test_thread_flag(TIF_32BIT)) {0 xffffffff;0 xffffffff;unsigned int __user *) regs->tpc);if (panic_on_oops)"Fatal exception" );#define VIS_OPCODE_MASK ((0 x3 << 30 ) | (0 x3f << 19 ))#define VIS_OPCODE_VAL ((0 x2 << 30 ) | (0 x36 << 19 ))void do_illegal_instruction(struct pt_regs *regs)enum ctx_state prev_state = exception_enter();unsigned long pc = regs->tpc;unsigned long tstate = regs->tstate;if (notify_die(DIE_TRAP, "illegal instruction" , regs,0 , 0 x10, SIGILL) == NOTIFY_STOP)goto out;if (tstate & TSTATE_PRIV)"Kernel illegal instruction" , regs);if (test_thread_flag(TIF_32BIT))if (get_user(insn, (u32 __user *) pc) != -EFAULT) {if ((insn & 0 xc1ffc000) == 0 x81700000) /* POPC */ { if (handle_popc(insn, regs))goto out;else if ((insn & 0 xc1580000) == 0 xc1100000) /* LDQ/STQ */ { if (handle_ldf_stq(insn, regs))goto out;else if (tlb_type == hypervisor) {if ((insn & VIS_OPCODE_MASK) == VIS_OPCODE_VAL) {if (!vis_emul(regs, insn))goto out;else {struct fpustate *f = FPUSTATE;/* On UltraSPARC T2 and later, FPU insns which * are not implemented in HW signal an illegal * instruction trap and do not set the FP Trap * Trap in the % fsr to unimplemented_FPop . if (do_mathemu(regs, f, true ))goto out;void __user *)pc);void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)enum ctx_state prev_state = exception_enter();if (notify_die(DIE_TRAP, "memory address unaligned" , regs,0 , 0 x34, SIGSEGV) == NOTIFY_STOP)goto out;if (regs->tstate & TSTATE_PRIV) {unsigned int *)regs->tpc));goto out;if (is_no_fault_exception(regs))return ;void __user *)sfar);void sun4v_do_mna(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)if (notify_die(DIE_TRAP, "memory address unaligned" , regs,0 , 0 x34, SIGSEGV) == NOTIFY_STOP)return ;if (regs->tstate & TSTATE_PRIV) {unsigned int *)regs->tpc));return ;if (is_no_fault_exception(regs))return ;void __user *) addr);/* sun4v_mem_corrupt_detect_precise() - Handle precise exception on an ADI * tag mismatch . * * ADI version tag mismatch on a load from memory always results in a * precise exception . Tag mismatch on a store to memory will result in * precise exception if MCDPER or PMCDPER is set to 1 . void sun4v_mem_corrupt_detect_precise(struct pt_regs *regs, unsigned long addr,unsigned long context)if (notify_die(DIE_TRAP, "memory corruption precise exception" , regs,0 , 0 x8, SIGSEGV) == NOTIFY_STOP)return ;if (regs->tstate & TSTATE_PRIV) {/* MCD exception could happen because the task was running * a system call with MCD enabled and passed a non - versioned * pointer or pointer with bad version tag to the system * call . const struct exception_table_entry *entry;if (entry) {/* Looks like a bad syscall parameter */ #ifdef DEBUG_EXCEPTIONS"Exception: PC<%016lx> faddr<UNKNOWN>\n" ,"EX_TABLE: insn<%016lx> fixup<%016lx>\n" ,#endif 4 ;return ;"%s: ADDR[%016lx] CTX[%lx], going.\n" ,"MCD precise" , regs);if (test_thread_flag(TIF_32BIT)) {0 xffffffff;0 xffffffff;void __user *)addr);void do_privop(struct pt_regs *regs)enum ctx_state prev_state = exception_enter();if (notify_die(DIE_TRAP, "privileged operation" , regs,0 , 0 x11, SIGILL) == NOTIFY_STOP)goto out;if (test_thread_flag(TIF_32BIT)) {0 xffffffff;0 xffffffff;void __user *)regs->tpc);void do_privact(struct pt_regs *regs)/* Trap level 1 stuff or other traps we should never see... */ void do_cee(struct pt_regs *regs)"TL0: Cache Error Exception" , regs);void do_div0_tl1(struct pt_regs *regs)struct tl1_traplog *)(regs + 1 ));"TL1: DIV0 Exception" , regs);void do_fpieee_tl1(struct pt_regs *regs)struct tl1_traplog *)(regs + 1 ));"TL1: FPU IEEE Exception" , regs);void do_fpother_tl1(struct pt_regs *regs)struct tl1_traplog *)(regs + 1 ));"TL1: FPU Other Exception" , regs);void do_ill_tl1(struct pt_regs *regs)struct tl1_traplog *)(regs + 1 ));"TL1: Illegal Instruction Exception" , regs);void do_irq_tl1(struct pt_regs *regs)struct tl1_traplog *)(regs + 1 ));"TL1: IRQ Exception" , regs);void do_lddfmna_tl1(struct pt_regs *regs)struct tl1_traplog *)(regs + 1 ));"TL1: LDDF Exception" , regs);void do_stdfmna_tl1(struct pt_regs *regs)struct tl1_traplog *)(regs + 1 ));"TL1: STDF Exception" , regs);void do_paw(struct pt_regs *regs)"TL0: Phys Watchpoint Exception" , regs);void do_paw_tl1(struct pt_regs *regs)struct tl1_traplog *)(regs + 1 ));"TL1: Phys Watchpoint Exception" , regs);void do_vaw(struct pt_regs *regs)"TL0: Virt Watchpoint Exception" , regs);void do_vaw_tl1(struct pt_regs *regs)struct tl1_traplog *)(regs + 1 ));"TL1: Virt Watchpoint Exception" , regs);void do_tof_tl1(struct pt_regs *regs)struct tl1_traplog *)(regs + 1 ));"TL1: Tag Overflow Exception" , regs);void do_getpsr(struct pt_regs *regs)4 ;if (test_thread_flag(TIF_32BIT)) {0 xffffffff;0 xffffffff;0 };struct trap_per_cpu trap_block[NR_CPUS];/* This can get invoked before sched_init() so play it super safe * and use hard_smp_processor_id ( ) . void notrace init_cur_cpu_trap(struct thread_info *t)int cpu = hard_smp_processor_id();struct trap_per_cpu *p = &trap_block[cpu];0 ;extern void thread_info_offsets_are_bolixed_dave(void );extern void trap_per_cpu_offsets_are_bolixed_dave(void );extern void tsb_config_offsets_are_bolixed_dave(void );/* Only invoked on boot processor. */ void __init trap_init(void )/* Compile time sanity check. */ struct thread_info, task) ||struct thread_info, flags) ||struct thread_info, cpu) ||struct thread_info, fpsaved) ||struct thread_info, ksp) ||struct thread_info,struct thread_info, kregs) ||struct thread_info, utraps) ||struct thread_info,struct thread_info,struct thread_info, gsr) ||struct thread_info, xfsr) ||struct thread_info,struct thread_info, new_child) ||struct thread_info,struct thread_info,struct thread_info, fpregs) ||64 - 1 )));struct trap_per_cpu,struct trap_per_cpu, pgd_paddr)) ||struct trap_per_cpu, cpu_mondo_pa)) ||struct trap_per_cpu, dev_mondo_pa)) ||struct trap_per_cpu, resum_mondo_pa)) ||struct trap_per_cpu, resum_kernel_buf_pa)) ||struct trap_per_cpu, nonresum_mondo_pa)) ||struct trap_per_cpu, nonresum_kernel_buf_pa)) ||struct trap_per_cpu, fault_info)) ||struct trap_per_cpu, cpu_mondo_block_pa)) ||struct trap_per_cpu, cpu_list_pa)) ||struct trap_per_cpu, tsb_huge)) ||struct trap_per_cpu, tsb_huge_temp)) ||struct trap_per_cpu, irq_worklist_pa)) ||struct trap_per_cpu, cpu_mondo_qmask)) ||struct trap_per_cpu, dev_mondo_qmask)) ||struct trap_per_cpu, resum_qmask)) ||struct trap_per_cpu, nonresum_qmask)) ||struct trap_per_cpu, __per_cpu_base)));struct tsb_config, tsb)) ||struct tsb_config, tsb_rss_limit)) ||struct tsb_config, tsb_nentries)) ||struct tsb_config, tsb_reg_val)) ||struct tsb_config, tsb_map_vaddr)) ||struct tsb_config, tsb_map_pte)));/* Attach to the address space of init_task. On SMP we * do this in smp . c : smp_callin for other cpus .
Messung V0.5 in Prozent C=94 H=92 G=92
¤ Dauer der Verarbeitung: 0.49 Sekunden
(vorverarbeitet am 2026-09-29)
¤ *© Formatika GbR, Deutschland
