// SPDX-License-Identifier: GPL-2.0 /* Performance event support for sparc64. * * Copyright ( C ) 2009 , 2010 David S . Miller < davem @ davemloft . net > * * This code is based almost entirely upon the x86 perf event * code , which is : * * Copyright ( C ) 2008 Thomas Gleixner < tglx @ linutronix . de > * Copyright ( C ) 2008 - 2009 Red Hat , Inc . , Ingo Molnar * Copyright ( C ) 2009 Jaswinder Singh Rajput * Copyright ( C ) 2009 Advanced Micro Devices , Inc . , Robert Richter * Copyright ( C ) 2008 - 2009 Red Hat , Inc . , Peter Zijlstra #include <linux/perf_event.h>#include <linux/kprobes.h>#include <linux/ftrace.h>#include <linux/kernel.h>#include <linux/kdebug.h>#include <linux/mutex.h>#include <asm /stacktrace.h>#include <asm /cpudata.h>#include <linux/uaccess.h>#include <linux/atomic.h>#include <linux/sched/clock.h>#include <asm /nmi.h>#include <asm /pcr.h>#include <asm /cacheflush.h>#include "kernel.h" #include "kstack.h" /* Two classes of sparc64 chips currently exist. All of which have * 32 - bit counters which can generate overflow interrupts on the * transition from 0 xffffffff to 0 . * * All chips upto and including SPARC - T3 have two performance * counters . The two 32 - bit counters are accessed in one go using a * single 64 - bit register . * * On these older chips both counters are controlled using a single * control register . The only way to stop all sampling is to clear * all of the context ( user , supervisor , hypervisor ) sampling enable * bits . But these bits apply to both counters , thus the two counters * can ' t be enabled / disabled individually . * * Furthermore , the control register on these older chips have two * event fields , one for each of the two counters . It ' s thus nearly * impossible to have one counter going while keeping the other one * stopped . Therefore it is possible to get overflow interrupts for * counters not currently " in use " and that condition must be checked * in the overflow interrupt handler . * * So we use a hack , in that we program inactive counters with the * " sw_count0 " and " sw_count1 " events . These count how many times * the instruction " sethi % hi ( 0 xfc000 ) , % g0 " is executed . It ' s an * unusual way to encode a NOP and therefore will not trigger in * normal code . * * Starting with SPARC - T4 we have one control register per counter . * And the counters are stored in individual registers . The registers * for the counters are 64 - bit but only a 32 - bit counter is * implemented . The event selections on SPARC - T4 lack any * restrictions , therefore we can elide all of the complicated * conflict resolution code we have for SPARC - T3 and earlier chips . #define MAX_HWEVENTS 4 #define MAX_PCRS 4 #define MAX_PERIOD ((1 UL << 32 ) - 1 )#define PIC_UPPER_INDEX 0 #define PIC_LOWER_INDEX 1 #define PIC_NO_INDEX -1 struct cpu_hw_events {/* Number of events currently scheduled onto this cpu. * This tells how many entries in the arrays below * are valid . int n_events;/* Number of new events added since the last hw_perf_disable(). * This works because the perf event layer always adds new * events inside of a perf_ { disable , enable } ( ) sequence . int n_added;/* Array of events current scheduled on this cpu. */ struct perf_event *event[MAX_HWEVENTS];/* Array of encoded longs, specifying the %pcr register * encoding and the mask of PIC counters this even can * be scheduled on . See perf_event_encode ( ) et al . unsigned long events[MAX_HWEVENTS];/* The current counter index assigned to an event. When the * event hasn ' t been programmed into the cpu yet , this will * hold PIC_NO_INDEX . The event - > hw . idx value tells us where * we ought to schedule the event . int current_idx[MAX_HWEVENTS];/* Software copy of %pcr register(s) on this cpu. */ /* Enabled/disable state. */ int enabled;unsigned int txn_flags;static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1 , };/* An event map describes the characteristics of a performance * counter event . In particular it gives the encoding as well as * a mask telling which counters the event can be measured on . * * The mask is unused on SPARC - T4 and later . struct perf_event_map {#define PIC_NONE 0 x00#define PIC_UPPER 0 x01#define PIC_LOWER 0 x02/* Encode a perf_event_map entry into a long. */ static unsigned long perf_event_encode(const struct perf_event_map *pmap)return ((unsigned long ) pmap->encoding << 16 ) | pmap->pic_mask;static u8 perf_event_get_msk(unsigned long val)return val & 0 xff;static u64 perf_event_get_enc(unsigned long val)return val >> 16 ;#define C(x) PERF_COUNT_HW_CACHE_## x#define CACHE_OP_UNSUPPORTED 0 xfffe#define CACHE_OP_NONSENSE 0 xfffftypedef struct perf_event_map cache_map_tstruct sparc_pmu {const struct perf_event_map *(*event_map)(int );const cache_map_t *cache_map;int max_events;int );void (*write_pmc)(int , u64);int upper_shift;int lower_shift;int event_mask;int user_bit;int priv_bit;int hv_bit;int irq_bit;int upper_nop;int lower_nop;unsigned int flags;#define SPARC_PMU_ALL_EXCLUDES_SAME 0 x00000001#define SPARC_PMU_HAS_CONFLICTS 0 x00000002int max_hw_events;int num_pcrs;int num_pic_regs;static u32 sparc_default_read_pmc(int idx)0 );if (idx == PIC_UPPER_INDEX)32 ;return val & 0 xffffffff;static void sparc_default_write_pmc(int idx, u64 val)0 ;if (idx == PIC_UPPER_INDEX)32 ;0 xffffffff) << shift;0 );0 , pic);static const struct perf_event_map ultra3_perfmon_event_map[] = {0 x0000, PIC_UPPER | PIC_LOWER },0 x0001, PIC_UPPER | PIC_LOWER },0 x0009, PIC_LOWER },0 x0009, PIC_UPPER },static const struct perf_event_map *ultra3_event_map(int event_id)return &ultra3_perfmon_event_map[event_id];static const cache_map_t ultra3_cache_map = {0 x09, PIC_LOWER, },0 x09, PIC_UPPER, },0 x0a, PIC_LOWER },0 x0a, PIC_UPPER },0 x09, PIC_LOWER, },0 x09, PIC_UPPER, },0 x0c, PIC_LOWER, },0 x0c, PIC_UPPER, },0 x0c, PIC_LOWER },0 x0c, PIC_UPPER },0 x12, PIC_UPPER, },0 x11, PIC_UPPER, },static const struct sparc_pmu ultra3_pmu = {11 ,4 ,0 x3f,0 x1c,0 x14,2 ,1 ,1 ,/* Niagara1 is very limited. The upper PIC is hard-locked to count * only instructions , so it is free running which creates all kinds of * problems . Some hardware designs make one wonder if the creator * even looked at how this stuff gets used by software . static const struct perf_event_map niagara1_perfmon_event_map[] = {0 x00, PIC_UPPER },0 x00, PIC_UPPER },0 , PIC_NONE },0 x03, PIC_LOWER },static const struct perf_event_map *niagara1_event_map(int event_id)return &niagara1_perfmon_event_map[event_id];static const cache_map_t niagara1_cache_map = {0 x03, PIC_LOWER, },0 x03, PIC_LOWER, },0 x00, PIC_UPPER },0 x02, PIC_LOWER, },0 x07, PIC_LOWER, },0 x07, PIC_LOWER, },0 x05, PIC_LOWER, },0 x04, PIC_LOWER, },static const struct sparc_pmu niagara1_pmu = {0 ,4 ,0 x7,0 x0,0 x0,2 ,1 ,1 ,static const struct perf_event_map niagara2_perfmon_event_map[] = {0 x02ff, PIC_UPPER | PIC_LOWER },0 x02ff, PIC_UPPER | PIC_LOWER },0 x0208, PIC_UPPER | PIC_LOWER },0 x0302, PIC_UPPER | PIC_LOWER },0 x0201, PIC_UPPER | PIC_LOWER },0 x0202, PIC_UPPER | PIC_LOWER },static const struct perf_event_map *niagara2_event_map(int event_id)return &niagara2_perfmon_event_map[event_id];static const cache_map_t niagara2_cache_map = {0 x0208, PIC_UPPER | PIC_LOWER, },0 x0302, PIC_UPPER | PIC_LOWER, },0 x0210, PIC_UPPER | PIC_LOWER, },0 x0302, PIC_UPPER | PIC_LOWER, },0 x02ff, PIC_UPPER | PIC_LOWER, },0 x0301, PIC_UPPER | PIC_LOWER, },0 x0208, PIC_UPPER | PIC_LOWER, },0 x0330, PIC_UPPER | PIC_LOWER, },0 x0210, PIC_UPPER | PIC_LOWER, },0 x0320, PIC_UPPER | PIC_LOWER, },0 x0b08, PIC_UPPER | PIC_LOWER, },0 xb04, PIC_UPPER | PIC_LOWER, },static const struct sparc_pmu niagara2_pmu = {19 ,6 ,0 xfff,0 x30,0 x220,0 x220,2 ,1 ,1 ,static const struct perf_event_map niagara4_perfmon_event_map[] = {26 << 6 ) },3 << 6 ) | 0 x3f },3 << 6 ) | 0 x04 },16 << 6 ) | 0 x07 },4 << 6 ) | 0 x01 },25 << 6 ) | 0 x0f },static const struct perf_event_map *niagara4_event_map(int event_id)return &niagara4_perfmon_event_map[event_id];static const cache_map_t niagara4_cache_map = {3 << 6 ) | 0 x04 },16 << 6 ) | 0 x07 },3 << 6 ) | 0 x08 },16 << 6 ) | 0 x07 },3 << 6 ) | 0 x3f },11 << 6 ) | 0 x03 },3 << 6 ) | 0 x04 },3 << 6 ) | 0 x08 },17 << 6 ) | 0 x3f },6 << 6 ) | 0 x3f },static u32 sparc_vt_read_pmc(int idx)return val & 0 xffffffff;static void sparc_vt_write_pmc(int idx, u64 val)/* ensure ov and ntc are reset */ 0 xffffffff);static const struct sparc_pmu niagara4_pmu = {5 ,5 ,0 x7ff,/* We explicitly don't support hypervisor tracing. The T4 * generates the overflow event for precise events via a trap * which will not be generated ( ie . it ' s completely lost ) if * we happen to be in the hypervisor when the event triggers . * Essentially , the overflow event reporting is completely * unusable when you have hypervisor mode tracing enabled . 0 ,0 ,0 ,0 ,4 ,4 ,4 ,static const struct sparc_pmu sparc_m7_pmu = {5 ,5 ,0 x7ff,/* We explicitly don't support hypervisor tracing. */ 0 ,0 ,0 ,0 ,4 ,4 ,4 ,static const struct sparc_pmu *sparc_pmu __read_mostly;static u64 event_encoding(u64 event_id, int idx)if (idx == PIC_UPPER_INDEX)else return event_id;static u64 mask_for_index(int idx)return event_encoding(sparc_pmu->event_mask, idx);static u64 nop_for_index(int idx)return event_encoding(idx == PIC_UPPER_INDEX ?static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)int pcr_index = 0 ;if (sparc_pmu->num_pcrs > 1 )static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)int pcr_index = 0 ;if (sparc_pmu->num_pcrs > 1 )static u64 sparc_perf_event_update(struct perf_event *event,struct hw_perf_event *hwc, int idx)int shift = 64 - 32 ;if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,goto again;return new_raw_count;static int sparc_perf_event_set_period(struct perf_event *event,struct hw_perf_event *hwc, int idx)int ret = 0 ;/* The period may have been changed by PERF_EVENT_IOC_PERIOD */ if (unlikely(period != hwc->last_period))if (unlikely(left <= -period)) {1 ;if (unlikely(left <= 0 )) {1 ;if (left > MAX_PERIOD)0 xffffffff);return ret;static void read_in_all_counters(struct cpu_hw_events *cpuc)int i;for (i = 0 ; i < cpuc->n_events; i++) {struct perf_event *cp = cpuc->event[i];if (cpuc->current_idx[i] != PIC_NO_INDEX &&if (cp->hw.state & PERF_HES_STOPPED)/* On this PMU all PICs are programmed using a single PCR. Calculate * the combined control register value . * * For such chips we require that all of the events have the same * configuration , so just fetch the settings from the first entry . static void calculate_single_pcr(struct cpu_hw_events *cpuc)int i;if (!cpuc->n_added)goto out;/* Assign to counters all unassigned events. */ for (i = 0 ; i < cpuc->n_events; i++) {struct perf_event *cp = cpuc->event[i];struct hw_perf_event *hwc = &cp->hw;int idx = hwc->idx;if (cpuc->current_idx[i] != PIC_NO_INDEX)continue ;0 ] &= ~mask_for_index(idx);if (hwc->state & PERF_HES_ARCH) {0 ] |= nop_for_index(idx);else {0 ] |= event_encoding(enc, idx);0 ;0 ] |= cpuc->event[0 ]->hw.config_base;static void sparc_pmu_start(struct perf_event *event, int flags);/* On this PMU each PIC has its own PCR control register. */ static void calculate_multiple_pcrs(struct cpu_hw_events *cpuc)int i;if (!cpuc->n_added)goto out;for (i = 0 ; i < cpuc->n_events; i++) {struct perf_event *cp = cpuc->event[i];struct hw_perf_event *hwc = &cp->hw;int idx = hwc->idx;if (cpuc->current_idx[i] != PIC_NO_INDEX)continue ;if (cp->hw.state & PERF_HES_ARCH)continue ;for (i = 0 ; i < cpuc->n_events; i++) {struct perf_event *cp = cpuc->event[i];int idx = cp->hw.idx;/* If performance event entries have been added, move existing events * around ( if necessary ) and then assign new entries to counters . static void update_pcrs_for_enable(struct cpu_hw_events *cpuc)if (cpuc->n_added)if (sparc_pmu->num_pcrs == 1 ) {else {static void sparc_pmu_enable(struct pmu *pmu)struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);int i;if (cpuc->enabled)return ;1 ;if (cpuc->n_events)for (i = 0 ; i < sparc_pmu->num_pcrs; i++)static void sparc_pmu_disable(struct pmu *pmu)struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);int i;if (!cpuc->enabled)return ;0 ;0 ;for (i = 0 ; i < sparc_pmu->num_pcrs; i++) {static int active_event_index(struct cpu_hw_events *cpuc,struct perf_event *event)int i;for (i = 0 ; i < cpuc->n_events; i++) {if (cpuc->event[i] == event)break ;return cpuc->current_idx[i];static void sparc_pmu_start(struct perf_event *event, int flags)struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);int idx = active_event_index(cpuc, event);if (flags & PERF_EF_RELOAD) {0 ;static void sparc_pmu_stop(struct perf_event *event, int flags)struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);int idx = active_event_index(cpuc, event);if (!(event->hw.state & PERF_HES_STOPPED)) {if (!(event->hw.state & PERF_HES_UPTODATE) && (flags & PERF_EF_UPDATE)) {static void sparc_pmu_del(struct perf_event *event, int _flags)struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);unsigned long flags;int i;for (i = 0 ; i < cpuc->n_events; i++) {if (event == cpuc->event[i]) {/* Absorb the final count and turn off the * event . /* Shift remaining entries down into * the existing slot . while (++i < cpuc->n_events) {1 ] = cpuc->event[i];1 ] = cpuc->events[i];1 ] =break ;static void sparc_pmu_read(struct perf_event *event)struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);int idx = active_event_index(cpuc, event);struct hw_perf_event *hwc = &event->hw;static atomic_t active_events = ATOMIC_INIT(0 );static DEFINE_MUTEX(pmc_grab_mutex);static void perf_stop_nmi_watchdog(void *unused)struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);int i;for (i = 0 ; i < sparc_pmu->num_pcrs; i++)static void perf_event_grab_pmc(void )if (atomic_inc_not_zero(&active_events))return ;if (atomic_read(&active_events) == 0 ) {if (atomic_read(&nmi_active) > 0 ) {1 );0 );static void perf_event_release_pmc(void )if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) {if (atomic_read(&nmi_active) == 0 )1 );static const struct perf_event_map *sparc_map_cache_event(u64 config)unsigned int cache_type, cache_op, cache_result;const struct perf_event_map *pmap;if (!sparc_pmu->cache_map)return ERR_PTR(-ENOENT);0 ) & 0 xff;if (cache_type >= PERF_COUNT_HW_CACHE_MAX)return ERR_PTR(-EINVAL);8 ) & 0 xff;if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)return ERR_PTR(-EINVAL);16 ) & 0 xff;if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)return ERR_PTR(-EINVAL);if (pmap->encoding == CACHE_OP_UNSUPPORTED)return ERR_PTR(-ENOENT);if (pmap->encoding == CACHE_OP_NONSENSE)return ERR_PTR(-EINVAL);return pmap;static void hw_perf_event_destroy(struct perf_event *event)/* Make sure all events can be scheduled into the hardware at * the same time . This is simplified by the fact that we only * need to support 2 simultaneous HW events . * * As a side effect , the evts [ ] - > hw . idx values will be assigned * on success . These are pending indexes . When the events are * actually programmed into the chip , these values will propagate * to the per - cpu cpuc - > current_idx [ ] slots , see the code in * maybe_change_configuration ( ) for details . static int sparc_check_constraints(struct perf_event **evts,unsigned long *events, int n_ev)0 , msk1 = 0 ;int idx0 = 0 ;/* This case is possible when we are invoked from * hw_perf_group_sched_in ( ) . if (!n_ev)return 0 ;if (n_ev > sparc_pmu->max_hw_events)return -1 ;if (!(sparc_pmu->flags & SPARC_PMU_HAS_CONFLICTS)) {int i;for (i = 0 ; i < n_ev; i++)return 0 ;0 ]);if (n_ev == 1 ) {if (msk0 & PIC_LOWER)1 ;goto success;2 );1 ]);/* If both events can go on any counter, OK. */ if (msk0 == (PIC_UPPER | PIC_LOWER) &&goto success;/* If one event is limited to a specific counter, * and the other can go on both , OK . if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) &&if (msk0 & PIC_LOWER)1 ;goto success;if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&if (msk1 & PIC_UPPER)1 ;goto success;/* If the events are fixed to different counters, OK. */ if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) ||if (msk0 & PIC_LOWER)1 ;goto success;/* Otherwise, there is a conflict. */ return -1 ;0 ]->hw.idx = idx0;if (n_ev == 2 )1 ]->hw.idx = idx0 ^ 1 ;return 0 ;static int check_excludes(struct perf_event **evts, int n_prev, int n_new)int eu = 0 , ek = 0 , eh = 0 ;struct perf_event *event;int i, n, first;if (!(sparc_pmu->flags & SPARC_PMU_ALL_EXCLUDES_SAME))return 0 ;if (n <= 1 )return 0 ;1 ;for (i = 0 ; i < n; i++) {if (first) {0 ;else if (event->attr.exclude_user != eu ||return -EAGAIN;return 0 ;static int collect_events(struct perf_event *group, int max_count,struct perf_event *evts[], unsigned long *events,int *current_idx)struct perf_event *event;int n = 0 ;if (!is_software_event(group)) {if (n >= max_count)return -1 ;if (!is_software_event(event) &&if (n >= max_count)return -1 ;return n;static int sparc_pmu_add(struct perf_event *event, int ef_flags)struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);int n0, ret = -EAGAIN;unsigned long flags;if (n0 >= sparc_pmu->max_hw_events)goto out;if (!(ef_flags & PERF_EF_START))/* * If group events scheduling transaction was started , * skip the schedulability test here , it will be performed * at commit time ( - > commit_txn ) as a whole if (cpuc->txn_flags & PERF_PMU_TXN_ADD)goto nocheck;if (check_excludes(cpuc->event, n0, 1 ))goto out;if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1 ))goto out;0 ;return ret;static int sparc_pmu_event_init(struct perf_event *event)struct perf_event_attr *attr = &event->attr;struct perf_event *evts[MAX_HWEVENTS];struct hw_perf_event *hwc = &event->hw;unsigned long events[MAX_HWEVENTS];int current_idx_dmy[MAX_HWEVENTS];const struct perf_event_map *pmap;int n;if (atomic_read(&nmi_active) < 0 )return -ENODEV;/* does not support taken branch sampling */ if (has_branch_stack(event))return -EOPNOTSUPP;switch (attr->type) {case PERF_TYPE_HARDWARE:if (attr->config >= sparc_pmu->max_events)return -EINVAL;break ;case PERF_TYPE_HW_CACHE:if (IS_ERR(pmap))return PTR_ERR(pmap);break ;case PERF_TYPE_RAW:break ;default :return -ENOENT;if (pmap) {else {/* * User gives us " ( encoding < < 16 ) | pic_mask " for * PERF_TYPE_RAW events . /* We save the enable bits in the config_base. */ if (!attr->exclude_user)if (!attr->exclude_kernel)if (!attr->exclude_hv)0 ;if (event->group_leader != event) {1 ,if (n < 0 )return -EINVAL;if (check_excludes(evts, n, 1 ))return -EINVAL;if (sparc_check_constraints(evts, events, n + 1 ))return -EINVAL;/* Try to do all error checking before this point, as unwinding * state after grabbing the PMC is difficult . if (!hwc->sample_period) {return 0 ;/* * Start group events scheduling transaction * Set the flag to make pmu : : enable ( ) not perform the * schedulability test , it will be performed at commit time static void sparc_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);/* txn already in flight */ if (txn_flags & ~PERF_PMU_TXN_ADD)return ;/* * Stop group events scheduling transaction * Clear the flag and pmu : : enable ( ) will perform the * schedulability test . static void sparc_pmu_cancel_txn(struct pmu *pmu)struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);unsigned int txn_flags;/* no txn in flight */ 0 ;if (txn_flags & ~PERF_PMU_TXN_ADD)return ;/* * Commit group events scheduling transaction * Perform the group schedulability test as a whole * Return 0 if success static int sparc_pmu_commit_txn(struct pmu *pmu)struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);int n;if (!sparc_pmu)return -EINVAL;/* no txn in flight */ if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {0 ;return 0 ;if (check_excludes(cpuc->event, 0 , n))return -EINVAL;if (sparc_check_constraints(cpuc->event, cpuc->events, n))return -EAGAIN;0 ;return 0 ;static struct pmu pmu = {void perf_event_print_debug(void )unsigned long flags;int cpu, i;if (!sparc_pmu)return ;"\n" );for (i = 0 ; i < sparc_pmu->num_pcrs; i++)"CPU#%d: PCR%d[%016llx]\n" ,for (i = 0 ; i < sparc_pmu->num_pic_regs; i++)"CPU#%d: PIC%d[%016llx]\n" ,static int __kprobes perf_event_nmi_handler(struct notifier_block *self,unsigned long cmd, void *__args)struct die_args *args = __args;struct perf_sample_data data;struct cpu_hw_events *cpuc;struct pt_regs *regs;int i;if (!atomic_read(&active_events))return NOTIFY_DONE;switch (cmd) {case DIE_NMI:break ;default :return NOTIFY_DONE;/* If the PMU has the TOE IRQ enable bits, we need to do a * dummy write to the % pcr to clear the overflow bits and thus * the interrupt . * * Do this before we peek at the counters to determine * overflow so we don ' t lose any events . if (sparc_pmu->irq_bit &&1 )0 , cpuc->pcr[0 ]);for (i = 0 ; i < cpuc->n_events; i++) {struct perf_event *event = cpuc->event[i];int idx = cpuc->current_idx[i];struct hw_perf_event *hwc;if (sparc_pmu->irq_bit &&1 )if (val & (1 ULL << 31 ))continue ;0 , hwc->last_period);if (!sparc_perf_event_set_period(event, hwc, idx))continue ;return NOTIFY_STOP;static __read_mostly struct notifier_block perf_event_nmi_notifier = {static bool __init supported_pmu(void )if (!strcmp(sparc_pmu_type, "ultra3" ) ||"ultra3+" ) ||"ultra3i" ) ||"ultra4+" )) {return true ;if (!strcmp(sparc_pmu_type, "niagara" )) {return true ;if (!strcmp(sparc_pmu_type, "niagara2" ) ||"niagara3" )) {return true ;if (!strcmp(sparc_pmu_type, "niagara4" ) ||"niagara5" )) {return true ;if (!strcmp(sparc_pmu_type, "sparc-m7" )) {return true ;return false ;static int __init init_hw_perf_events(void )int err;"Performance events: " );if (err || !supported_pmu()) {"No support for PMU type '%s'\n" , sparc_pmu_type);return 0 ;"Supported PMU type is '%s'\n" , sparc_pmu_type);"cpu" , PERF_TYPE_RAW);return 0 ;void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry,struct pt_regs *regs)unsigned long ksp, fp;#ifdef CONFIG_FUNCTION_GRAPH_TRACERint graph = 0 ;#endif do {struct sparc_stackf *sf;struct pt_regs *regs;unsigned long pc;if (!kstack_valid(current_thread_info(), fp))break ;struct sparc_stackf *) fp;struct pt_regs *) (sf + 1 );if (kstack_is_trap_frame(current_thread_info(), regs)) {if (user_mode(regs))break ;else {unsigned long )sf->fp + STACK_BIAS;#ifdef CONFIG_FUNCTION_GRAPH_TRACERif ((pc + 8 UL) == (unsigned long ) &return_to_handler) {struct ftrace_ret_stack *ret_stack;if (ret_stack) {#endif while (entry->nr < entry->max_stack);static inline int const void __user *fp, unsigned long size)/* addresses should be at least 4-byte aligned */ if (((unsigned long ) fp) & 3 )return 0 ;return (__range_not_ok(fp, size, TASK_SIZE) == 0 );static void perf_callchain_user_64(struct perf_callchain_entry_ctx *entry,struct pt_regs *regs)unsigned long ufp;do {struct sparc_stackf __user *usf;struct sparc_stackf sf;unsigned long pc;struct sparc_stackf __user *)ufp;if (!valid_user_frame(usf, sizeof (sf)))break ;if (__copy_from_user_inatomic(&sf, usf, sizeof (sf)))break ;unsigned long )sf.fp + STACK_BIAS;while (entry->nr < entry->max_stack);static void perf_callchain_user_32(struct perf_callchain_entry_ctx *entry,struct pt_regs *regs)unsigned long ufp;0 xffffffffUL;do {unsigned long pc;if (thread32_stack_is_64bit(ufp)) {struct sparc_stackf __user *usf;struct sparc_stackf sf;struct sparc_stackf __user *)ufp;if (__copy_from_user_inatomic(&sf, usf, sizeof (sf)))break ;0 xffffffff;unsigned long ) sf.fp) & 0 xffffffff;else {struct sparc_stackf32 __user *usf;struct sparc_stackf32 sf;struct sparc_stackf32 __user *)ufp;if (__copy_from_user_inatomic(&sf, usf, sizeof (sf)))break ;unsigned long )sf.fp;while (entry->nr < entry->max_stack);void struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)if (!current->mm)return ;if (test_thread_flag(TIF_32BIT))else
Messung V0.5 in Prozent C=93 H=93 G=92
¤ Dauer der Verarbeitung: 0.27 Sekunden
(vorverarbeitet am 2026-09-29)
¤ *© Formatika GbR, Deutschland
