// SPDX-License-Identifier: GPL-2.0 /* * arch / sh / kernel / cpu / sh2a / opcode_helper . c * * Helper for the SH - 2 A 32 - bit opcodes . * * Copyright ( C ) 2007 Paul Mundt #include <linux/kernel.h>#include <asm /processor.h>/* * Instructions on SH are generally fixed at 16 - bits , however , SH - 2 A * introduces some 32 - bit instructions . Since there are no real * constraints on their use ( and they can be mixed and matched ) , we need * to check the instruction encoding to work out if it ' s a true 32 - bit * instruction or not . * * Presently , 32 - bit opcodes have only slight variations in what the * actual encoding looks like in the first - half of the instruction , which * makes it fairly straightforward to differentiate from the 16 - bit ones . * * First 16 - bits of encoding Used by * * 0011 nnnnmmmm0001 mov . b , mov . w , mov . l , fmov . d , * fmov . s , movu . b , movu . w * * 0011 nnnn0iii1001 bclr . b , bld . b , bset . b , bst . b , band . b , * bandnot . b , bldnot . b , bor . b , bornot . b , * bxor . b * * 0000 nnnniiii0000 movi20 * 0000 nnnniiii0001 movi20s unsigned int instruction_size(unsigned int insn)/* Look for the common cases */ switch ((insn & 0 xf00f)) {case 0 x0000: /* movi20 */ case 0 x0001: /* movi20s */ case 0 x3001: /* 32-bit mov/fmov/movu variants */ return 4 ;/* And the special cases.. */ switch ((insn & 0 xf08f)) {case 0 x3009: /* 32-bit b*.b bit operations */ return 4 ;return 2 ;
Messung V0.5 in Prozent C=84 H=86 G=84
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