Quelle sg2044-cpus.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
*/
/ {
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <50000000>;
cpu0: cpu@0 {
compatible = "thead,c920", "riscv";
reg = <0>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache0>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu1: cpu@1 {
compatible = "thead,c920", "riscv";
reg = <1>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache0>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu2: cpu@2 {
compatible = "thead,c920", "riscv";
reg = <2>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache0>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu3: cpu@3 {
compatible = "thead,c920", "riscv";
reg = <3>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache0>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu4: cpu@4 {
compatible = "thead,c920", "riscv";
reg = <4>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache1>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu4_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu5: cpu@5 {
compatible = "thead,c920", "riscv";
reg = <5>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache1>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu5_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu6: cpu@6 {
compatible = "thead,c920", "riscv";
reg = <6>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache1>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu6_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu7: cpu@7 {
compatible = "thead,c920", "riscv";
reg = <7>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache1>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu7_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu8: cpu@8 {
compatible = "thead,c920", "riscv";
reg = <8>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache2>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu8_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu9: cpu@9 {
compatible = "thead,c920", "riscv";
reg = <9>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache2>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu9_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu10: cpu@10 {
compatible = "thead,c920", "riscv";
reg = <10>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache2>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu10_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu11: cpu@11 {
compatible = "thead,c920", "riscv";
reg = <11>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache2>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu11_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu12: cpu@12 {
compatible = "thead,c920", "riscv";
reg = <12>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache3>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu12_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu13: cpu@13 {
compatible = "thead,c920", "riscv";
reg = <13>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache3>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu13_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu14: cpu@14 {
compatible = "thead,c920", "riscv";
reg = <14>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache3>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu14_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu15: cpu@15 {
compatible = "thead,c920", "riscv";
reg = <15>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache3>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu15_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu16: cpu@16 {
compatible = "thead,c920", "riscv";
reg = <16>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache4>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu16_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu17: cpu@17 {
compatible = "thead,c920", "riscv";
reg = <17>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache4>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu17_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu18: cpu@18 {
compatible = "thead,c920", "riscv";
reg = <18>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache4>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu18_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu19: cpu@19 {
compatible = "thead,c920", "riscv";
reg = <19>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache4>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu19_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu20: cpu@20 {
compatible = "thead,c920", "riscv";
reg = <20>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache5>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu20_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu21: cpu@21 {
compatible = "thead,c920", "riscv";
reg = <21>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache5>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu21_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu22: cpu@22 {
compatible = "thead,c920", "riscv";
reg = <22>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache5>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu22_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu23: cpu@23 {
compatible = "thead,c920", "riscv";
reg = <23>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache5>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu23_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu24: cpu@24 {
compatible = "thead,c920", "riscv";
reg = <24>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache6>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu24_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu25: cpu@25 {
compatible = "thead,c920", "riscv";
reg = <25>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache6>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu25_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu26: cpu@26 {
compatible = "thead,c920", "riscv";
reg = <26>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache6>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu26_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu27: cpu@27 {
compatible = "thead,c920", "riscv";
reg = <27>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache6>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu27_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu28: cpu@28 {
compatible = "thead,c920", "riscv";
reg = <28>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache7>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu28_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu29: cpu@29 {
compatible = "thead,c920", "riscv";
reg = <29>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache7>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu29_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu30: cpu@30 {
compatible = "thead,c920", "riscv";
reg = <30>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache7>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu30_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu31: cpu@31 {
compatible = "thead,c920", "riscv";
reg = <31>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache7>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu31_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu32: cpu@32 {
compatible = "thead,c920", "riscv";
reg = <32>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache8>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu32_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu33: cpu@33 {
compatible = "thead,c920", "riscv";
reg = <33>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache8>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu33_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu34: cpu@34 {
compatible = "thead,c920", "riscv";
reg = <34>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache8>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu34_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu35: cpu@35 {
compatible = "thead,c920", "riscv";
reg = <35>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache8>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu35_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu36: cpu@36 {
compatible = "thead,c920", "riscv";
reg = <36>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache9>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu36_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu37: cpu@37 {
compatible = "thead,c920", "riscv";
reg = <37>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache9>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu37_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu38: cpu@38 {
compatible = "thead,c920", "riscv";
reg = <38>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache9>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu38_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu39: cpu@39 {
compatible = "thead,c920", "riscv";
reg = <39>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache9>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu39_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu40: cpu@40 {
compatible = "thead,c920", "riscv";
reg = <40>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache10>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu40_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu41: cpu@41 {
compatible = "thead,c920", "riscv";
reg = <41>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache10>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu41_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu42: cpu@42 {
compatible = "thead,c920", "riscv";
reg = <42>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache10>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu42_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu43: cpu@43 {
compatible = "thead,c920", "riscv";
reg = <43>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache10>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu43_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu44: cpu@44 {
compatible = "thead,c920", "riscv";
reg = <44>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache11>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu44_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu45: cpu@45 {
compatible = "thead,c920", "riscv";
reg = <45>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache11>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu45_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu46: cpu@46 {
compatible = "thead,c920", "riscv";
reg = <46>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache11>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu46_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu47: cpu@47 {
compatible = "thead,c920", "riscv";
reg = <47>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache11>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu47_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu48: cpu@48 {
compatible = "thead,c920", "riscv";
reg = <48>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache12>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu48_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu49: cpu@49 {
compatible = "thead,c920", "riscv";
reg = <49>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache12>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu49_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu50: cpu@50 {
compatible = "thead,c920", "riscv";
reg = <50>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache12>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu50_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu51: cpu@51 {
compatible = "thead,c920", "riscv";
reg = <51>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache12>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu51_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu52: cpu@52 {
compatible = "thead,c920", "riscv";
reg = <52>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache13>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu52_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu53: cpu@53 {
compatible = "thead,c920", "riscv";
reg = <53>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache13>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu53_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu54: cpu@54 {
compatible = "thead,c920", "riscv";
reg = <54>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache13>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu54_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu55: cpu@55 {
compatible = "thead,c920", "riscv";
reg = <55>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache13>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu55_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu56: cpu@56 {
compatible = "thead,c920", "riscv";
reg = <56>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache14>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu56_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu57: cpu@57 {
compatible = "thead,c920", "riscv";
reg = <57>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache14>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
cpu57_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
cpu58: cpu@58 {
compatible = "thead,c920", "riscv";
reg = <58>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <65536>;
d-cache-sets = <512>;
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache14>;
riscv,isa = "rv64imafdcv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
"zfa", "zfbfmin", "zfh", "zfhmin",
"zicbom", "zicbop", "zicboz", "ziccrse",
"zicntr", "zicond","zicsr", "zifencei",
"zihintntl", "zihintpause", "zihpm",
"zvfbfmin", "zvfbfwma", "zvfh",
"zvfhmin";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
--> --------------------
--> maximum size reached
--> --------------------
[ Dauer der Verarbeitung: 0.19 Sekunden
(vorverarbeitet)
]
|
2026-04-07
|
