Quelle  sg2042.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
 */

/dts-v1/;
#include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
#include <dt-bindings/clock/sophgo,sg2042-pll.h>
#include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/pinctrl-sg2042.h>
#include <dt-bindings/reset/sophgo,sg2042-reset.h>

#include "sg2042-cpus.dtsi"

/ {
 compatible = "sophgo,sg2042";
 #address-cells = <2>;
 #size-cells = <2>;
 dma-noncoherent;

 aliases {
  serial0 = &uart0;
 };

 cgi_main: oscillator0 {
  compatible = "fixed-clock";
  clock-output-names = "cgi_main";
  #clock-cells = <0>;
 };

 cgi_dpll0: oscillator1 {
  compatible = "fixed-clock";
  clock-output-names = "cgi_dpll0";
  #clock-cells = <0>;
 };

 cgi_dpll1: oscillator2 {
  compatible = "fixed-clock";
  clock-output-names = "cgi_dpll1";
  #clock-cells = <0>;
 };

 soc: soc {
  compatible = "simple-bus";
  #address-cells = <2>;
  #size-cells = <2>;
  interrupt-parent = <&intc>;
  ranges;

  i2c0: i2c@7030005000 {
   compatible = "snps,designware-i2c";
   reg = <0x70 0x30005000 0x0 0x1000>;
   #address-cells = <1>;
   #size-cells = <0>;
   clocks = <&clkgen GATE_CLK_APB_I2C>;
   clock-names = "ref";
   clock-frequency = <100000>;
   interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
   resets = <&rstgen RST_I2C0>;
   status = "disabled";
  };

  i2c1: i2c@7030006000 {
   compatible = "snps,designware-i2c";
   reg = <0x70 0x30006000 0x0 0x1000>;
   #address-cells = <1>;
   #size-cells = <0>;
   clocks = <&clkgen GATE_CLK_APB_I2C>;
   clock-names = "ref";
   clock-frequency = <100000>;
   interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
   resets = <&rstgen RST_I2C1>;
   status = "disabled";
  };

  i2c2: i2c@7030007000 {
   compatible = "snps,designware-i2c";
   reg = <0x70 0x30007000 0x0 0x1000>;
   #address-cells = <1>;
   #size-cells = <0>;
   clocks = <&clkgen GATE_CLK_APB_I2C>;
   clock-names = "ref";
   clock-frequency = <100000>;
   interrupts = <103 IRQ_TYPE_LEVEL_HIGH>;
   resets = <&rstgen RST_I2C2>;
   status = "disabled";
  };

  i2c3: i2c@7030008000 {
   compatible = "snps,designware-i2c";
   reg = <0x70 0x30008000 0x0 0x1000>;
   #address-cells = <1>;
   #size-cells = <0>;
   clocks = <&clkgen GATE_CLK_APB_I2C>;
   clock-names = "ref";
   clock-frequency = <100000>;
   interrupts = <104 IRQ_TYPE_LEVEL_HIGH>;
   resets = <&rstgen RST_I2C3>;
   status = "disabled";
  };

  gpio0: gpio@7030009000 {
   compatible = "snps,dw-apb-gpio";
   reg = <0x70 0x30009000 0x0 0x400>;
   #address-cells = <1>;
   #size-cells = <0>;
   clocks = <&clkgen GATE_CLK_APB_GPIO>,
     <&clkgen GATE_CLK_GPIO_DB>;
   clock-names = "bus", "db";

   port0a: gpio-controller@0 {
    compatible = "snps,dw-apb-gpio-port";
    gpio-controller;
    #gpio-cells = <2>;
    ngpios = <32>;
    reg = <0>;
    interrupt-controller;
    #interrupt-cells = <2>;
    interrupt-parent = <&intc>;
    interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
   };
  };

  gpio1: gpio@703000a000 {
   compatible = "snps,dw-apb-gpio";
   reg = <0x70 0x3000a000 0x0 0x400>;
   #address-cells = <1>;
   #size-cells = <0>;
   clocks = <&clkgen GATE_CLK_APB_GPIO>,
     <&clkgen GATE_CLK_GPIO_DB>;
   clock-names = "bus", "db";

   port1a: gpio-controller@0 {
    compatible = "snps,dw-apb-gpio-port";
    gpio-controller;
    #gpio-cells = <2>;
    ngpios = <32>;
    reg = <0>;
    interrupt-controller;
    #interrupt-cells = <2>;
    interrupt-parent = <&intc>;
    interrupts = <97 IRQ_TYPE_LEVEL_HIGH>;
   };
  };

  gpio2: gpio@703000b000 {
   compatible = "snps,dw-apb-gpio";
   reg = <0x70 0x3000b000 0x0 0x400>;
   #address-cells = <1>;
   #size-cells = <0>;
   clocks = <&clkgen GATE_CLK_APB_GPIO>,
     <&clkgen GATE_CLK_GPIO_DB>;
   clock-names = "bus", "db";

   port2a: gpio-controller@0 {
    compatible = "snps,dw-apb-gpio-port";
    gpio-controller;
    #gpio-cells = <2>;
    ngpios = <32>;
    reg = <0>;
    interrupt-controller;
    #interrupt-cells = <2>;
    interrupt-parent = <&intc>;
    interrupts = <98 IRQ_TYPE_LEVEL_HIGH>;
   };
  };

  pwm: pwm@703000c000 {
   compatible = "sophgo,sg2042-pwm";
   reg = <0x70 0x3000c000 0x0 0x20>;
   #pwm-cells = <3>;
   clocks = <&clkgen GATE_CLK_APB_PWM>;
   clock-names = "apb";
   resets = <&rstgen RST_PWM>;
  };

  pllclk: clock-controller@70300100c0 {
   compatible = "sophgo,sg2042-pll";
   reg = <0x70 0x300100c0 0x0 0x40>;
   clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
   clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
   #clock-cells = <1>;
  };

  msi: msi-controller@7030010304 {
   compatible = "sophgo,sg2042-msi";
   reg = <0x70 0x30010304 0x0 0x4>,
         <0x70 0x30010300 0x0 0x4>;
   reg-names = "clr", "doorbell";
   msi-controller;
   #msi-cells = <0>;
   msi-ranges = <&intc 64 IRQ_TYPE_LEVEL_HIGH 32>;
  };

  rpgate: clock-controller@7030010368 {
   compatible = "sophgo,sg2042-rpgate";
   reg = <0x70 0x30010368 0x0 0x98>;
   clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>;
   clock-names = "rpgate";
   #clock-cells = <1>;
  };

  pinctrl: pinctrl@7030011000 {
   compatible = "sophgo,sg2042-pinctrl";
   reg = <0x70 0x30011000 0x0 0x1000>;
  };

  clkgen: clock-controller@7030012000 {
   compatible = "sophgo,sg2042-clkgen";
   reg = <0x70 0x30012000 0x0 0x1000>;
   clocks = <&pllclk MPLL_CLK>,
     <&pllclk FPLL_CLK>,
     <&pllclk DPLL0_CLK>,
     <&pllclk DPLL1_CLK>;
   clock-names = "mpll",
          "fpll",
          "dpll0",
          "dpll1";
   #clock-cells = <1>;
  };

  clint_mswi: interrupt-controller@7094000000 {
   compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
   reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
   interrupts-extended = <&cpu0_intc 3>,
           <&cpu1_intc 3>,
           <&cpu2_intc 3>,
           <&cpu3_intc 3>,
           <&cpu4_intc 3>,
           <&cpu5_intc 3>,
           <&cpu6_intc 3>,
           <&cpu7_intc 3>,
           <&cpu8_intc 3>,
           <&cpu9_intc 3>,
           <&cpu10_intc 3>,
           <&cpu11_intc 3>,
           <&cpu12_intc 3>,
           <&cpu13_intc 3>,
           <&cpu14_intc 3>,
           <&cpu15_intc 3>,
           <&cpu16_intc 3>,
           <&cpu17_intc 3>,
           <&cpu18_intc 3>,
           <&cpu19_intc 3>,
           <&cpu20_intc 3>,
           <&cpu21_intc 3>,
           <&cpu22_intc 3>,
           <&cpu23_intc 3>,
           <&cpu24_intc 3>,
           <&cpu25_intc 3>,
           <&cpu26_intc 3>,
           <&cpu27_intc 3>,
           <&cpu28_intc 3>,
           <&cpu29_intc 3>,
           <&cpu30_intc 3>,
           <&cpu31_intc 3>,
           <&cpu32_intc 3>,
           <&cpu33_intc 3>,
           <&cpu34_intc 3>,
           <&cpu35_intc 3>,
           <&cpu36_intc 3>,
           <&cpu37_intc 3>,
           <&cpu38_intc 3>,
           <&cpu39_intc 3>,
           <&cpu40_intc 3>,
           <&cpu41_intc 3>,
           <&cpu42_intc 3>,
           <&cpu43_intc 3>,
           <&cpu44_intc 3>,
           <&cpu45_intc 3>,
           <&cpu46_intc 3>,
           <&cpu47_intc 3>,
           <&cpu48_intc 3>,
           <&cpu49_intc 3>,
           <&cpu50_intc 3>,
           <&cpu51_intc 3>,
           <&cpu52_intc 3>,
           <&cpu53_intc 3>,
           <&cpu54_intc 3>,
           <&cpu55_intc 3>,
           <&cpu56_intc 3>,
           <&cpu57_intc 3>,
           <&cpu58_intc 3>,
           <&cpu59_intc 3>,
           <&cpu60_intc 3>,
           <&cpu61_intc 3>,
           <&cpu62_intc 3>,
           <&cpu63_intc 3>;
  };

  clint_mtimer0: timer@70ac004000 {
   compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
   reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
   reg-names = "mtimecmp";
   interrupts-extended = <&cpu0_intc 7>,
           <&cpu1_intc 7>,
           <&cpu2_intc 7>,
           <&cpu3_intc 7>;
  };

  clint_mtimer1: timer@70ac014000 {
   compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
   reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
   reg-names = "mtimecmp";
   interrupts-extended = <&cpu4_intc 7>,
           <&cpu5_intc 7>,
           <&cpu6_intc 7>,
           <&cpu7_intc 7>;
  };

  clint_mtimer2: timer@70ac024000 {
   compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
   reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
   reg-names = "mtimecmp";
   interrupts-extended = <&cpu8_intc 7>,
           <&cpu9_intc 7>,
           <&cpu10_intc 7>,
           <&cpu11_intc 7>;
  };

  clint_mtimer3: timer@70ac034000 {
   compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
   reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
   reg-names = "mtimecmp";
   interrupts-extended = <&cpu12_intc 7>,
           <&cpu13_intc 7>,
           <&cpu14_intc 7>,
           <&cpu15_intc 7>;
  };

  clint_mtimer4: timer@70ac044000 {
   compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
   reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
   reg-names = "mtimecmp";
   interrupts-extended = <&cpu16_intc 7>,
           <&cpu17_intc 7>,
           <&cpu18_intc 7>,
           <&cpu19_intc 7>;
  };

  clint_mtimer5: timer@70ac054000 {
   compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
   reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
   reg-names = "mtimecmp";
   interrupts-extended = <&cpu20_intc 7>,
           <&cpu21_intc 7>,
           <&cpu22_intc 7>,
           <&cpu23_intc 7>;
  };

  clint_mtimer6: timer@70ac064000 {
   compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
   reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
   reg-names = "mtimecmp";
   interrupts-extended = <&cpu24_intc 7>,
           <&cpu25_intc 7>,
           <&cpu26_intc 7>,
           <&cpu27_intc 7>;
  };

  clint_mtimer7: timer@70ac074000 {
   compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
   reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
   reg-names = "mtimecmp";
   interrupts-extended = <&cpu28_intc 7>,
           <&cpu29_intc 7>,
           <&cpu30_intc 7>,
           <&cpu31_intc 7>;
  };

  clint_mtimer8: timer@70ac084000 {
   compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
   reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
   reg-names = "mtimecmp";
   interrupts-extended = <&cpu32_intc 7>,
           <&cpu33_intc 7>,
           <&cpu34_intc 7>,
           <&cpu35_intc 7>;
  };

  clint_mtimer9: timer@70ac094000 {
   compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
   reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
   reg-names = "mtimecmp";
   interrupts-extended = <&cpu36_intc 7>,
           <&cpu37_intc 7>,
           <&cpu38_intc 7>,
           <&cpu39_intc 7>;
  };

  clint_mtimer10: timer@70ac0a4000 {
   compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
   reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
   reg-names = "mtimecmp";
   interrupts-extended = <&cpu40_intc 7>,
           <&cpu41_intc 7>,
           <&cpu42_intc 7>,
           <&cpu43_intc 7>;
  };

  clint_mtimer11: timer@70ac0b4000 {
   compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
   reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
   reg-names = "mtimecmp";
   interrupts-extended = <&cpu44_intc 7>,
           <&cpu45_intc 7>,
           <&cpu46_intc 7>,
           <&cpu47_intc 7>;
  };

  clint_mtimer12: timer@70ac0c4000 {
   compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
   reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
   reg-names = "mtimecmp";
   interrupts-extended = <&cpu48_intc 7>,
           <&cpu49_intc 7>,
           <&cpu50_intc 7>,
           <&cpu51_intc 7>;
  };

  clint_mtimer13: timer@70ac0d4000 {
   compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
   reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
   reg-names = "mtimecmp";
   interrupts-extended = <&cpu52_intc 7>,
           <&cpu53_intc 7>,
           <&cpu54_intc 7>,
           <&cpu55_intc 7>;
  };

  clint_mtimer14: timer@70ac0e4000 {
   compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
   reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
   reg-names = "mtimecmp";
   interrupts-extended = <&cpu56_intc 7>,
           <&cpu57_intc 7>,
           <&cpu58_intc 7>,
           <&cpu59_intc 7>;
  };

  clint_mtimer15: timer@70ac0f4000 {
   compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
   reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
   reg-names = "mtimecmp";
   interrupts-extended = <&cpu60_intc 7>,
           <&cpu61_intc 7>,
           <&cpu62_intc 7>,
           <&cpu63_intc 7>;
  };

  intc: interrupt-controller@7090000000 {
   compatible = "sophgo,sg2042-plic", "thead,c900-plic";
   #address-cells = <0>;
   #interrupt-cells = <2>;
   reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
   interrupt-controller;
   interrupts-extended =
    <&cpu0_intc 11>,  <&cpu0_intc 9>,
    <&cpu1_intc 11>,  <&cpu1_intc 9>,
    <&cpu2_intc 11>,  <&cpu2_intc 9>,
    <&cpu3_intc 11>,  <&cpu3_intc 9>,
    <&cpu4_intc 11>,  <&cpu4_intc 9>,
    <&cpu5_intc 11>,  <&cpu5_intc 9>,
    <&cpu6_intc 11>,  <&cpu6_intc 9>,
    <&cpu7_intc 11>,  <&cpu7_intc 9>,
    <&cpu8_intc 11>,  <&cpu8_intc 9>,
    <&cpu9_intc 11>,  <&cpu9_intc 9>,
    <&cpu10_intc 11>, <&cpu10_intc 9>,
    <&cpu11_intc 11>, <&cpu11_intc 9>,
    <&cpu12_intc 11>, <&cpu12_intc 9>,
    <&cpu13_intc 11>, <&cpu13_intc 9>,
    <&cpu14_intc 11>, <&cpu14_intc 9>,
    <&cpu15_intc 11>, <&cpu15_intc 9>,
    <&cpu16_intc 11>, <&cpu16_intc 9>,
    <&cpu17_intc 11>, <&cpu17_intc 9>,
    <&cpu18_intc 11>, <&cpu18_intc 9>,
    <&cpu19_intc 11>, <&cpu19_intc 9>,
    <&cpu20_intc 11>, <&cpu20_intc 9>,
    <&cpu21_intc 11>, <&cpu21_intc 9>,
    <&cpu22_intc 11>, <&cpu22_intc 9>,
    <&cpu23_intc 11>, <&cpu23_intc 9>,
    <&cpu24_intc 11>, <&cpu24_intc 9>,
    <&cpu25_intc 11>, <&cpu25_intc 9>,
    <&cpu26_intc 11>, <&cpu26_intc 9>,
    <&cpu27_intc 11>, <&cpu27_intc 9>,
    <&cpu28_intc 11>, <&cpu28_intc 9>,
    <&cpu29_intc 11>, <&cpu29_intc 9>,
    <&cpu30_intc 11>, <&cpu30_intc 9>,
    <&cpu31_intc 11>, <&cpu31_intc 9>,
    <&cpu32_intc 11>, <&cpu32_intc 9>,
    <&cpu33_intc 11>, <&cpu33_intc 9>,
    <&cpu34_intc 11>, <&cpu34_intc 9>,
    <&cpu35_intc 11>, <&cpu35_intc 9>,
    <&cpu36_intc 11>, <&cpu36_intc 9>,
    <&cpu37_intc 11>, <&cpu37_intc 9>,
    <&cpu38_intc 11>, <&cpu38_intc 9>,
    <&cpu39_intc 11>, <&cpu39_intc 9>,
    <&cpu40_intc 11>, <&cpu40_intc 9>,
    <&cpu41_intc 11>, <&cpu41_intc 9>,
    <&cpu42_intc 11>, <&cpu42_intc 9>,
    <&cpu43_intc 11>, <&cpu43_intc 9>,
    <&cpu44_intc 11>, <&cpu44_intc 9>,
    <&cpu45_intc 11>, <&cpu45_intc 9>,
    <&cpu46_intc 11>, <&cpu46_intc 9>,
    <&cpu47_intc 11>, <&cpu47_intc 9>,
    <&cpu48_intc 11>, <&cpu48_intc 9>,
    <&cpu49_intc 11>, <&cpu49_intc 9>,
    <&cpu50_intc 11>, <&cpu50_intc 9>,
    <&cpu51_intc 11>, <&cpu51_intc 9>,
    <&cpu52_intc 11>, <&cpu52_intc 9>,
    <&cpu53_intc 11>, <&cpu53_intc 9>,
    <&cpu54_intc 11>, <&cpu54_intc 9>,
    <&cpu55_intc 11>, <&cpu55_intc 9>,
    <&cpu56_intc 11>, <&cpu56_intc 9>,
    <&cpu57_intc 11>, <&cpu57_intc 9>,
    <&cpu58_intc 11>, <&cpu58_intc 9>,
    <&cpu59_intc 11>, <&cpu59_intc 9>,
    <&cpu60_intc 11>, <&cpu60_intc 9>,
    <&cpu61_intc 11>, <&cpu61_intc 9>,
    <&cpu62_intc 11>, <&cpu62_intc 9>,
    <&cpu63_intc 11>, <&cpu63_intc 9>;
   riscv,ndev = <224>;
  };

  rstgen: reset-controller@7030013000 {
   compatible = "sophgo,sg2042-reset";
   reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
   #reset-cells = <1>;
  };

  uart0: serial@7040000000 {
   compatible = "snps,dw-apb-uart";
   reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
   interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
   clock-frequency = <500000000>;
   clocks = <&clkgen GATE_CLK_UART_500M>,
     <&clkgen GATE_CLK_APB_UART>;
   clock-names = "baudclk", "apb_pclk";
   reg-shift = <2>;
   reg-io-width = <4>;
   resets = <&rstgen RST_UART0>;
   status = "disabled";
  };

  spi0: spi@7040004000 {
   compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
   reg = <0x70 0x40004000 0x00 0x1000>;
   clocks = <&clkgen GATE_CLK_APB_SPI>;
   interrupt-parent = <&intc>;
   interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
   #address-cells = <1>;
   #size-cells = <0>;
   num-cs = <2>;
   resets = <&rstgen RST_SPI0>;
   status = "disabled";
  };

  spi1: spi@7040005000 {
   compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
   reg = <0x70 0x40005000 0x00 0x1000>;
   clocks = <&clkgen GATE_CLK_APB_SPI>;
   interrupt-parent = <&intc>;
   interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
   #address-cells = <1>;
   #size-cells = <0>;
   num-cs = <2>;
   resets = <&rstgen RST_SPI1>;
   status = "disabled";
  };

  gmac0: ethernet@7040026000 {
   compatible = "sophgo,sg2042-dwmac", "snps,dwmac-5.00a";
   reg = <0x70 0x40026000 0x0 0x4000>;
   clocks = <&clkgen GATE_CLK_AXI_ETH0>,
     <&clkgen GATE_CLK_PTP_REF_I_ETH0>,
     <&clkgen GATE_CLK_TX_ETH0>;
   clock-names = "stmmaceth", "ptp_ref", "tx";
   dma-noncoherent;
   interrupt-parent = <&intc>;
   interrupts = <132 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "macirq";
   resets = <&rstgen RST_ETH0>;
   reset-names = "stmmaceth";
   snps,multicast-filter-bins = <0>;
   snps,perfect-filter-entries = <1>;
   snps,aal;
   snps,tso;
   snps,txpbl = <32>;
   snps,rxpbl = <32>;
   snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
   snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
   snps,axi-config = <&gmac0_stmmac_axi_setup>;
   status = "disabled";

   mdio {
    compatible = "snps,dwmac-mdio";
    #address-cells = <1>;
    #size-cells = <0>;
   };

   gmac0_mtl_rx_setup: rx-queues-config {
    snps,rx-queues-to-use = <8>;
    queue0 {};
    queue1 {};
    queue2 {};
    queue3 {};
    queue4 {};
    queue5 {};
    queue6 {};
    queue7 {};
   };

   gmac0_mtl_tx_setup: tx-queues-config {
    snps,tx-queues-to-use = <8>;
    queue0 {};
    queue1 {};
    queue2 {};
    queue3 {};
    queue4 {};
    queue5 {};
    queue6 {};
    queue7 {};
   };

   gmac0_stmmac_axi_setup: stmmac-axi-config {
    snps,blen = <16 8 4 0 0 0 0>;
    snps,wr_osr_lmt = <1>;
    snps,rd_osr_lmt = <2>;
   };
  };

  emmc: mmc@704002a000 {
   compatible = "sophgo,sg2042-dwcmshc";
   reg = <0x70 0x4002a000 0x0 0x1000>;
   interrupt-parent = <&intc>;
   interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&clkgen GATE_CLK_EMMC_100M>,
     <&clkgen GATE_CLK_AXI_EMMC>,
     <&clkgen GATE_CLK_100K_EMMC>;
   clock-names = "core",
          "bus",
          "timer";
   status = "disabled";
  };

  sd: mmc@704002b000 {
   compatible = "sophgo,sg2042-dwcmshc";
   reg = <0x70 0x4002b000 0x0 0x1000>;
   interrupt-parent = <&intc>;
   interrupts = <136 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&clkgen GATE_CLK_SD_100M>,
     <&clkgen GATE_CLK_AXI_SD>,
     <&clkgen GATE_CLK_100K_SD>;
   clock-names = "core",
          "bus",
          "timer";
   status = "disabled";
  };
 };
};