/* SPDX-License-Identifier: GPL-2.0-only */ /* * Enter and leave deep sleep state on MPC83xx * * Copyright (c) 2006-2008 Freescale Semiconductor, Inc. * Author: Scott Wood <scottwood@freescale.com>
*/
/* The first 2 words of memory are used to communicate with the * bootloader, to tell it how to resume. * * The first word is the magic number 0xf5153ae5, and the second * is the pointer to mpc83xx_deep_resume. * * The original content of these two words is saved in SS_MEMSAVE.
*/
lis r3, mpc83xx_sleep_save_area@h
ori r3, r3, mpc83xx_sleep_save_area@l
lis r4, KERNELBASE@h
lwz r5, 0(r4)
lwz r6, 4(r4)
stw r5, SS_MEMSAVE+0(r3)
stw r6, SS_MEMSAVE+4(r3)
mfspr r5, SPRN_HID0
mfspr r6, SPRN_HID1 /* FIXME: Should this use SPRN_HID2_G2_LE? */
mfspr r7, SPRN_HID2_750FX
ori r4, r4, 0x002a
mtspr SPRN_DBAT0L, r4
lis r8, TMP_VIRT_IMMR@h
ori r4, r8, 0x001e /* 1 MByte accessible from Kernel Space only */
mtspr SPRN_DBAT0U, r4
isync
/* Use DBAT1 to address the original IMMR space */
lis r4, DEFAULT_IMMR_VALUE@h
ori r4, r4, 0x002a
mtspr SPRN_DBAT1L, r4
lis r9, (TMP_VIRT_IMMR + 0x01000000)@h
ori r4, r9, 0x001e /* 1 MByte accessible from Kernel Space only */
mtspr SPRN_DBAT1U, r4
isync
/* Use DBAT2 to address the beginning of RAM. This isn't done * using the normal virtual mapping, because with page debugging * enabled it will be read-only.
*/
li r4, 0x0002
mtspr SPRN_DBAT2L, r4
lis r4, KERNELBASE@h
ori r4, r4, 0x001e /* 1 MByte accessible from Kernel Space only */
mtspr SPRN_DBAT2U, r4
isync
/* Flush the cache with our BAT, as there will be TLB misses * otherwise if page debugging is enabled, and these misses * will disturb the PLRU algorithm.
*/
bl __flush_disable_L1
/* Keep the i-cache enabled, so the hack below for low-boot * flash will work.
*/
mfspr r3, SPRN_HID0
ori r3, r3, HID0_ICE
mtspr SPRN_HID0, r3
isync
lis r6, 0xf515
ori r6, r6, 0x3ae5
lis r7, mpc83xx_deep_resume@h
ori r7, r7, mpc83xx_deep_resume@l
tophys(r7, r7)
/* Rev 1 of the 8313 has problems with wakeup events that are * pending during the transition to deep sleep state (such as if * the PCI host sets the state to D3 and then D0 in rapid * succession). This check shrinks the race window somewhat. * * See erratum PCI23, though the problem is not limited * to PCI.
*/
/* Enable the flash mapping at the appropriate address. This * mapping will override the RAM mapping if booting low, so there's * no need to disable the latter. This must be done inside the same * cache line as setting MSR_POW, so that no instruction fetches * from RAM happen after the flash mapping is turned on.
*/
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