/* SPDX-License-Identifier: GPL-2.0 */
/* * This file contains the 64 - bit " server " PowerPC variant * of the low level exception handling including exception * vectors , exception return , part of the slb and stab * handling and other fixed offset specific things . * * This file is meant to be # included from head_64 . S due to * position dependent assembly . * * Most of this originates from head_64 . S and thus has the same * copyright history . *
#include <linux/linkage.h>
#include <asm/hw_irq.h>
#include <asm/exception-
64 s.h>
#include <asm/ptrace.h>
#include <asm/cpuidle.h>
#include <asm/head-
64 .h>
#include <asm/feature-fixups.h>
#include <asm/kup.h>
/* * Following are fixed section helper macros . * * EXC_REAL_BEGIN / END - real , unrelocated exception vectors * EXC_VIRT_BEGIN / END - virt ( AIL ) , unrelocated exception vectors * TRAMP_REAL_BEGIN - real , unrelocated helpers ( virt may call these ) * TRAMP_VIRT_BEGIN - virt , unreloc helpers ( in practice , real can use ) * EXC_COMMON - After switching to virtual , relocated mode .
#define EXC_REAL_BEGIN(name, start,
size ) \
FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##name, start,
size )
#define EXC_REAL_END(name, start,
size ) \
FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##name, start,
size )
#define EXC_VIRT_BEGIN(name, start,
size ) \
FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##name, start,
size )
#define EXC_VIRT_END(name, start,
size ) \
FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##name, start,
size )
#define EXC_COMMON_BEGIN(name) \
USE_TEXT_SECTION(); \
.balign IFETCH_ALIGN_BYTES; \
.
global name; \
_ASM_NOKPROBE_SYMBOL(name); \
DEFINE_FIXED_SYMBOL(name, text); \
name:
#define TRAMP_REAL_BEGIN(name) \
FIXED_SECTION_ENTRY_BEGIN(real_trampolines, name)
#define TRAMP_VIRT_BEGIN(name) \
FIXED_SECTION_ENTRY_BEGIN(virt_trampolines, name)
#define EXC_REAL_NONE(start,
size ) \
FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##unused, star
t, size ); \size size ) \t, size ); \size /* * We ' re short on space and time in the exception prolog , so we can ' t * use the normal LOAD_REG_IMMEDIATE macro to load the address of label . * Instead we get the base of the kernel from paca - > kernelbase and or in the low * part of label . This requires that the label be within 64 KB of kernelbase , and * that kernelbase be 64 K aligned . ld reg,PACAKBASE(r13); /* get high part of &label */ \ section ) \ld reg,PACAKBASE(r13); \section ))@l/* * Branches from unrelocated code ( e . g . , interrupts ) to labels outside * head - y require > 64 K offsets . section ) \ld reg,PACAKBASE(r13); \section ))@l; \section ))@h/* * Interrupt code generation macros /* Interrupt vector address */ /* Sets SRR or HSRR registers */ /* HSRR if HV else SRR */ /* PACA save area */ /* Has virt mode entry point */ /* Uses SRR0/1 not DAR/DSISR */ /* Uses CFAR */ /* Uses CFAR if HV */ /* Uses DAR (or SRR0) */ /* Uses DSISR (or SRR1) */ /* ENTRY branch to common */ /* Common runs in realmode */ /* IRQ soft-mask bit */ /* Real entry tests KVM */ /* Virt entry tests KVM */ /* Set regular kernel stack */ /* Do KUAP lock */ /* Assumes MSR saved to r12 */ "IVEC not defined" 0 0 1 0 1 0 0 0 1 0 ! IBRANCH_TO_COMMON "IREALMODE_COMMON=1 but IBRANCH_TO_COMMON=0" 0 0 0 1 1 0 /* * All interrupts which set HSRR registers , as well as SRESET and MCE and * syscall when invoked with " sc 1 " switch to MSR [ HV ] = 1 ( HVMODE ) to be taken , * so they all generally need to test whether they were taken in guest context . * * Note : SRESET and MCE may also be sent to the guest by the hypervisor , and be * taken with MSR [ HV ] = 0 . * * Interrupts which set SRR registers ( with the above exceptions ) do not * elevate to MSR [ HV ] = 1 mode , though most can be taken when running with * MSR [ HV ] = 1 ( e . g . , bare metal kernel and userspace ) . So these interrupts do * not need to test whether a guest is running because they get delivered to * the guest directly , including nested HV KVM guests . * * The exception is PR KVM , where the guest runs with MSR [ PR ] = 1 and the host * runs with MSR [ HV ] = 0 , so the host takes all interrupts on behalf of the * guest . PR KVM runs with LPCR [ AIL ] = 0 which causes interrupts to always be * delivered to the real - mode entry point , therefore such interrupts only test * KVM in their real mode handlers , and only when PR KVM is possible . * * Interrupts that are taken in MSR [ HV ] = 0 and escalate to MSR [ HV ] = 1 are always * delivered in real - mode when the MMU is in hash mode because the MMU * registers are not set appropriately to translate host addresses . In nested * radix mode these can be delivered in virt - mode as the host translations are * used implicitly ( see : effective LPID , effective PID ) . /* * If an interrupt is taken while a guest is running , it is immediately routed * to KVM to handle . 0 /* HSRR variants have the 0x2 bit added to their trap number */ 0 x2)0 x2)/* * This is the BOOK3S interrupt entry code macro . * * This can result in one of several things happening : * - Branch to the _ common handler , relocated , in virtual mode . * These are normal interrupts ( synchronous and asynchronous ) handled by * the kernel . * - Branch to KVM , relocated but real mode interrupts remain in real mode . * These occur when HSTATE_IN_GUEST is set . The interrupt may be caused by * / intended for host or guest kernel , but KVM must always be involved * because the machine state is set for guest execution . * - Branch to the masked handler , unrelocated . * These occur when maskable asynchronous interrupts are taken with the * irq_soft_mask set . * - Branch to an " early " handler in real mode but relocated . * This is done if early = 1 . MCE and HMI use these to handle errors in real * mode . * - Fall through and continue executing in real , unrelocated mode . * This is done if early = 2 . 0 /* save r13 */ /* save r9 */ /* save r10 */ 69 )69 )69 )0 69 )!\virt /* save r11 - r12 */ /* * DAR / DSISR , SCRATCH0 must be read before setting MSR [ RI ] , * because a d - side MCE will clobber those registers so is * not recoverable if they are live . !IISIDE !IISIDE /* save HSRR0 */ /* and HSRR1 */ /* save SRR0 */ /* and SRR1 */ /* save HSRR0 */ /* and HSRR1 */ /* save SRR0 */ /* and SRR1 */ /* * _ _ GEN_COMMON_ENTRY is required to receive the branch from interrupt * entry , except in the case of the real - mode handlers which require * _ _ GEN_REALMODE_COMMON_ENTRY . * * This switches to virtual mode and sets MSR [ RI ] . ld r10,PACAKMSR(r13) /* get MSR value for kernel */ /* MSR[RI] is clear iff using SRR regs */ ! IHSRR 1 f /* skip the virt test coming from real */ 1 :/* IVIRT */ /* * Don ' t switch to virt mode . Used for early MCE and HMI handlers that * want to run in real mode . ! ISTACK "No support for masked interrupt to use custom stack" /* If coming from user, skip soft-mask tests. */ 3 f/* * Kernel code running below _ _ end_soft_masked may be * implicitly soft - masked if it is within the regions * in the soft mask table . 1 f/* SEARCH_SOFT_MASK_TABLE clobbers r9,r10,r12 */ 0 /* Restore r12 to SRR1 */ 1 f /* Not in soft-mask table */ 2 f /* In soft-mask table, always mask */ /* Test the soft mask state against our interrupt's bit */ 1 : lbz r10,PACAIRQSOFTMASK(r13)2 : andi. r10,r10,IMASK/* Associate vector numbers with bits in paca->irq_happened */ 0 x500 || IVEC == 0 xea00 x9000 xa00 || IVEC == 0 xe800 xe600 xf00"Bad maskable vector" /* See if coming from user */ 3 : mr r10,r1 /* Save r1 */ /* alloc frame on kernel stack */ 100 fld r1,PACAKSAVE(r13) /* kernel stack to use */ 100 : tdgei r1,-INT_FRAME_SIZE /* trap if r1 is in userspace */ 100 b,__FILE__,__LINE__,0 /* save CR in stackframe */ /* save SRR0 in stackframe */ /* save SRR1 in stackframe */ 0 (r1) /* make stack chain pointer */ /* save r0 in stackframe */ /* save r1 in stackframe */ 0 )/* Mark our [H]SRRs valid for return */ 1 101 f /* if from kernel mode */ ld r9,IAREA+EX_PPR(r13) /* Read PPR from paca */ 101 :/* Save original regs values from save area to stack frame. */ ld r9,IAREA+EX_R9(r13) /* move r9, r10 to stackframe */ ld r10,IAREA+EX_R10(r13)ld r9,IAREA+EX_R11(r13) /* move r11 - r13 to stackframe */ ld r10,IAREA+EX_R12(r13)ld r11,IAREA+EX_R13(r13)!IMSR_R12 9 , 12 )9 , 11 )ld r10,_NIP(r1)ld r10,IAREA+EX_DAR(r13)ld r10,_MSR(r1)ld r10,IAREA+EX_CFAR(r13)0 ld r10,IAREA+EX_CTR(r13)2 , 8 , r1) /* save r2 - r8 in stackframe */ 2 , 8 )/* Get LR, later save to stack */ /* get kernel TOC into r2 */ /* save XER in stackframe */ /* set trap number */ 0 /* clear regs->result */ /* mark the frame */ /* * On entry r13 points to the paca , r9 - r13 are saved in the paca , * r9 contains the saved CR , r11 and r12 contain the saved SRR0 and * SRR1 , and relocation is on . * * If stack = 0 , then the stack is already set in r1 , and r1 is saved in r10 . * PPR save and CPU accounting is not done for the !stack case (XXX why not?) 300 :302 fld r12,0 (r9)301 fld r12,8 (r9)301 fld r12,16 (r9)303 f301 :24 300 b302 :0 303 :300 :302 fld r12,0 (r9)301 fld r12,8 (r9)301 f1 303 f301 :16 300 b302 :0 303 :/* * Restore all registers including H / SRR0 / 1 saved in a stack frame of a * standard exception . 0 /* Move original SRR0 and SRR1 into the respective regs */ ld r9,_MSR(r1)0 ld r9,_NIP(r1)ld r9,_CTR(r1)ld r9,_XER(r1)ld r9,_LINK(r1)ld r9,_CCR(r1)2 , 13 , r1)0 , r1)/* restore original r1. */ ld r1,GPR1(r1)/* * EARLY_BOOT_FIXUP - Fix real - mode interrupt with wrong endian in early boot . * * There ' s a short window during boot where although the kernel is running * little endian , any exceptions will cause the CPU to switch back to big * endian . For example a WARN ( ) boils down to a trap instruction , which will * cause a program check , and we end up here but with the CPU in big endian * mode . The first instruction of the program check handler ( in GEN_INT_ENTRY * below ) is an mtsprg , which when executed in the wrong endian is an lhzu with * a ~ 3 GB displacement from r3 . The content of r3 is random , so that is a load * from some random location , and depending on the system can easily lead to a * checkstop , or an infinitely recursive page fault . * * So to handle that case we have a trampoline here that can detect we are in * the wrong endian and flip us back to the correct endian . We can ' t flip * MSR [ LE ] using mtmsr , so we have to use rfid . That requires backing up SRR0 / 1 * as well as a GPR . To do that we use SPRG0 / 2 / 3 , as SPRG1 is already used for * the paca . SPRG3 is user readable , but this trampoline is only active very * early in boot , and SPRG3 will be reinitialised in vdso_getcpu_init ( ) before * userspace starts . 0 ,0 ,0 x48 // Trap never, or in reverse endian: b . + 8 2 f // Skip trampoline if endian is correct0 xa643707d // mtsprg 0 , r11 Backup r110 xa6027a7d // mfsrr0 r110 xa643727d // mtsprg 2 , r11 Backup SRR0 in SPRG20 xa6027b7d // mfsrr1 r110 xa643737d // mtsprg 3 , r11 Backup SRR1 in SPRG30 xa600607d // mfmsr r110 x01006b69 // xori r11, r11, 1 Invert MSR[LE]0 xa6037b7d // mtsrr1 r11/* * This is ' li r11 , 1 f ' where 1 f is the absolute address of that * label , byteswapped into the SI field of the instruction . 0 x00006039 | \1 f, real_vectors) & 0 x00ff) << 24 ) | \1 f, real_vectors) & 0 xff00) << 8 )0 xa6037a7d // mtsrr0 r110 x2400004c // rfid1 :3 2 0 // Restore r112 :/* * program check could hit at any time , and pseries can not block * MSR [ ME ] in early boot . So check if there is anything useful in r13 * yet , and spin forever if not . 0 , r110 0 0 , 1 ) // nop out after boot/* * There are a few constraints to be concerned with . * - Real mode exceptions code / data must be located at their physical location . * - Virtual mode exceptions must be mapped at their 0 xc000 . . . location . * - Fixed location code must not call directly beyond the _ _ end_interrupts * area when built with CONFIG_RELOCATABLE . LOAD_HANDLER / bctr sequence * must be used . * - LOAD_HANDLER targets must be within first 64 K of physical 0 / * virtual 0 xc00 . . . * - Conditional branch targets must be within + / - 32 K of caller . * * " Virtual exceptions " run with relocation on ( MSR_IR = 1 , MSR_DR = 1 ) , and * therefore don ' t have to run in physically located code or rfid to * virtual mode kernel code . However on relocatable kernels they do have * to branch to KERNELBASE offset because the rest of the kernel ( outside * the exception vectors ) may be located elsewhere . * * Virtual exceptions correspond with physical , except their entry points * are offset by 0 xc000000000000000 and also tend to get an added 0 x4000 * offset applied . Virtual exceptions are enabled with the Alternate * Interrupt Location ( AIL ) bit set in the LPCR . However this does not * guarantee they will be delivered virtually . Some conditions ( see the ISA ) * cause exceptions to be delivered in real mode . * * The scv instructions are a special case . They get a 0 x3000 offset applied . * scv exceptions have unique reentrancy properties , see below . * * It ' s impossible to receive interrupts below 0 x300 via AIL . * * KVM : None of the virtual exceptions are from the guest . Anything that * escalated to HV = 1 from HV = 0 is delivered via real mode handlers . * * * We layout physical memory as follows : * 0 x0000 - 0 x00ff : Secondary processor spin code * 0 x0100 - 0 x18ff : Real mode pSeries interrupt vectors * 0 x1900 - 0 x2fff : Real mode trampolines * 0 x3000 - 0 x58ff : Relon ( IR = 1 , DR = 1 ) mode pSeries interrupt vectors * 0 x5900 - 0 x6fff : Relon mode trampolines * 0 x7000 - 0 x7fff : FWNMI data area * 0 x8000 - . . . . : Common interrupt handlers , remaining early * setup code , rest of kernel . * * We could reclaim 0 x4000 - 0 x42ff for real mode trampolines if the space * is necessary . Until then it ' s more consistent to explicitly put VIRT_NONE * vectors there . 0 x0100, 0 x1900)0 x1900, 0 x3000)0 x3000, 0 x5900)0 x5900, 0 x7000)/* * Data area reserved for FWNMI option . * This address ( 0 x7000 ) is fixed by the RPA . * pseries and powernv need to keep the whole page from * 0 x7000 to 0 x8000 free for use by the firmware 0 x7000, 0 x8000)0 x8000)0 x7000)/* * This is the start of the interrupt handlers for pSeries * This code runs with relocation off . * Code from here to _ _ end_interrupts gets copied down to real * address 0 x100 when we are running a relocatable kernel . * Therefore any relative branches in this section must only * branch to labels in this section . /** * Interrupt 0 x3000 - System Call Vectored Interrupt ( syscall ) . * This is a synchronous interrupt invoked with the " scv " instruction . The * system call does not alter the HV bit , so it is directed to the OS . * * Handling : * scv instructions enter the kernel without changing EE , RI , ME , or HV . * In particular , this means we can take a maskable interrupt at any point * in the scv handler , which is unlike any other interrupt . This is solved * by treating the instruction addresses in the handler as being soft - masked , * by adding a SOFT_MASK_TABLE entry for them . * * AIL - 0 mode scv exceptions go to 0 x17000 - 0 x17fff , but we set AIL - 3 and * ensure scv is never executed with relocation off , which means AIL - 0 * should never happen . * * Before leaving the following inside - _ _ end_soft_masked text , at least of the * following must be true : * - MSR [ PR ] = 1 ( i . e . , return to userspace ) * - MSR_EE | MSR_RI is clear ( no reentrant exceptions ) * - Standard kernel environment is set up ( stack , paca , etc ) * * KVM : * These interrupts do not elevate HV 0 - > 1 , so HV is not involved . PR KVM * ensures that FSCR [ SCV ] is disabled whenever it has to force AIL off . * * Call convention : * * syscall register convention is in Documentation / arch / powerpc / syscall64 - abi . rst 0 x3000, 0 x1000)/* SCV 0 */ /* SCV 1 - 127 */ 127 1 /* cause failure */ 0 x3000, 0 x1000)'t get relocated, 0 xc000000000003000, 0 xc000000000004000)/* No virt vectors corresponding with 0x0..0x100 */ 0 x4000, 0 x100)/** * Interrupt 0 x100 - System Reset Interrupt ( SRESET aka NMI ) . * This is a non - maskable , asynchronous interrupt always taken in real - mode . * It is caused by : * - Wake from power - saving state , on powernv . * - An NMI from another CPU , triggered by firmware or hypercall . * - As crash / debug signal injected from BMC , firmware or hypervisor . * * Handling : * Power - save wakeup is the only performance critical path , so this is * determined quickly as possible first . In this case volatile registers * can be discarded and SPRs like CFAR don ' t need to be read . * * If not a powersave wakeup , then it ' s run as a regular interrupt , however * it uses its own stack and PACA save area to preserve the regular kernel * environment for debugging . * * This interrupt is not maskable , so triggering it when MSR [ RI ] is clear , * or SCRATCH0 is in use , etc . may cause a crash . It ' s also not entirely * correct to switch to virtual mode to run the regular interrupt handler * because it might be interrupted when the MMU is in a bad state ( e . g . , SLB * is clear ) . * * FWNMI : * PAPR specifies a " fwnmi " facility which sends the sreset to a different * entry point with a different register set up . Some hypervisors will * send the sreset to 0 x100 in the guest if it is not fwnmi capable . * * KVM : * Unlike most SRR interrupts , this may be taken by the host while executing * in a guest , so a KVM test is required . KVM will pull the CPU out of guest * mode and then raise the sreset . 0 x1000 /* no virt entry point */ 0 1 0 x100, 0 x100)/* * If running native on arch 2 . 06 or later , check if we are waking up * from nap / sleep / winkle , and branch to idle handler . This tests SRR1 * bits 46 : 47 . A non - 0 value indicates that we are coming from a power * saving state . The idle wakeup handler initially runs in real mode , * but we branch to the 0 xc000 . . . address so we can turn on relocation * with mtmsrd later , after SPRs are restored . * * Careful to minimise cost for the fast path ( idle wakeup ) while * also avoiding clobbering CFAR for the debug path ( non - idle ) . * * For the idle wake case volatile registers can be clobbered , which * is why we use those initially . If it turns out to not be an idle * wake , carefully put everything back the way it was , so we can use * common exception macros to handle it . 0 *8 (r13)1 *8 (r13)2 *8 (r13)0 x8047 -31 ,30 ,31 /* Not powersave wakeup. Restore regs for regular interrupt handler. */ 0 x80,r4ld r3,PACA_EXNMI+0 *8 (r13)ld r4,PACA_EXNMI+1 *8 (r13)ld r5,PACA_EXNMI+2 *8 (r13)0 /* * In theory , we should not enable relocation here if it was disabled * in SRR1 , because the MMU may not be configured to support it ( e . g . , * SLB may have been cleared ) . In practice , there should only be a few * small windows where that ' s the case , and sreset is considered to * be dangerous anyway . 0 x100, 0 x100)0 x4100, 0 x100)/* We are waking up from idle, so may clobber any volatile register */ 2 /* no state loss, return to idle caller with r3=SRR1 */ /* * Vectors for the FWNMI option . Share common code . 0 /* CONFIG_PPC_PSERIES */ /* * Increment paca - > in_nmi . When the interrupt entry wrapper later * enable MSR_RI , then SLB or MCE will be able to recover , but a nested * NMI will notice in_nmi and not recover because of the use of the NMI * stack . in_nmi reentrancy is tested in system_reset_exception . 1 ld r1,PACA_NMI_EMERG_SP(r13)/* Clear MSR_RI before setting SRR0 and SRR1. */ 0 1 /* * MSR_RI is clear , now we can decrement paca - > in_nmi . 1 /** * Interrupt 0 x200 - Machine Check Interrupt ( MCE ) . * This is a non - maskable interrupt always taken in real - mode . It can be * synchronous or asynchronous , caused by hardware or software , and it may be * taken in a power - saving state . * * Handling : * Similarly to system reset , this uses its own stack and PACA save area , * the difference is re - entrancy is allowed on the machine check stack . * * machine_check_early is run in real mode , and carefully decodes the * machine check and tries to handle it ( e . g . , flush the SLB if there was an * error detected there ) , determines if it was recoverable and logs the * event . * * This early code does not " reconcile " irq soft - mask state like SRESET or * regular interrupts do , so irqs_disabled ( ) among other things may not work * properly ( irq disable / enable already doesn ' t work because irq tracing can * not work in real mode ) . * * Then , depending on the execution context when the interrupt is taken , there * are 3 main actions : * - Executing in kernel mode . The event is queued with irq_work , which means * it is handled when it is next safe to do so ( i . e . , the kernel has enabled * interrupts ) , which could be immediately when the interrupt returns . This * avoids nasty issues like switching to virtual mode when the MMU is in a * bad state , or when executing OPAL code . ( SRESET is exposed to such issues , * but it has different priorities ) . Check to see if the CPU was in power * save , and return via the wake up code if it was . * * - Executing in user mode . machine_check_exception is run like a normal * interrupt handler , which processes the data generated by the early handler . * * - Executing in guest mode . The interrupt is run with its KVM test , and * branches to KVM to deal with . KVM may queue the event for the host * to report later . * * This interrupt is not maskable , so if it triggers when MSR [ RI ] is clear , * or SCRATCH0 is in use , it may cause a crash . * * KVM : * See SRESET . 0 x2000 /* no virt entry point */ 1 0 1 1 0 /* We don't touch AMR here, we never go to virtual mode */ 0 x2000 /* no virt entry point */ 1 1 1 0 x200, 0 x100)0 0 x200, 0 x100)0 x4200, 0 x100)/* See comment at machine_check exception, don't turn on RI */ 0 /* Clear MSR_RI before setting SRR0 and SRR1. */\ 0 ; \1 ; /* Clear MSR_RI */ \ /* Decrement paca->in_mce now RI is clear. */ \ 1 ; \/* * Switch to mc_emergency stack and handle re - entrancy ( we limit * the nested MCE upto level 4 to avoid stack overflow ) . * Save MCE registers srr1 , srr0 , dar and dsisr and then set ME = 1 * * We use paca - > in_mce to check whether this is the first entry or * nested machine check . We increment paca - > in_mce to track nested * machine checks . * * If this is the first entry then set stack pointer to * paca - > mc_emergency_sp , otherwise r1 is already pointing to * stack frame on mc_emergency stack . * * NOTE : We are here with MSR_ME = 0 ( off ) , which means we risk a * checkstop if we get another machine check exception before we do * rfid with MSR_ME = 1 . * * This interrupt can wake directly from idle . If that is the case , * the machine check is handled then the idle wakeup code is called * to restore state . 0 /* Are we in nested machine check */ /* Are we at maximum nesting */ 1 /* increment paca->in_mce */ /* Save r1 */ 1 f/* First machine check entry */ ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ 1 : /* Limit nested MCE to level 4 to avoid stack overflow */ /* Check if we hit limit of 4 */ /* alloc stack frame */ 0 , 1 ) // nop out after boot/* Save result */ ld r12,_MSR(r1)/* * Check if thread was in power saving mode . We come here when any * of the following is true : * a . thread wasn ' t in power saving mode * b . thread was in power saving mode with no state loss , * supervisor state loss or hypervisor state loss . * * Go back to nap / sleep / winkle mode again if ( b ) is true . 47 -31 ,30 ,31 /* * Check if we are coming from guest . If yes , then run the normal * exception handler which will take the * machine_check_kvm - > kvm_interrupt branch to deliver the MC event * to guest . 0 /* Check if coming from guest */ /* continue if we are. */ /* * Check if we are coming from userspace . If yes , then run the normal * exception handler which will deliver the MC event to this kernel . /* See if coming from user. */ /* continue in V mode if we are. */ /* * At this point we are coming from kernel context . * Queue up the MCE event and return from the interrupt . * But before that , check if this is an un - recoverable exception . * If yes , then stay on emergency stack and panic . /* * Check if we have successfully handled / recovered from error , if not * then stay on emergency stack and panic . ld r3,RESULT(r1) /* Load result */ 0 /* see if we handled MCE successfully */ /* if !handled then panic */ /* * Return from MC interrupt . * Queue up the MCE event so that we can log it later , while * returning from kernel or opal call . /* * This is a host user or guest MCE . Restore all registers , then * run the " late " handler . For host user , this will run the * machine_check_exception handler in virtual mode like a normal * interrupt handler . For guest , this will trigger the KVM test * and branch to the KVM interrupt similarly to other interrupts . ld r10,ORIG_GPR3(r1)0 /* * Machine check is different because we use a different * save area : PACA_EXMC instead of PACA_EXGEN . /* * This is an idle wakeup . Low level machine check has already been * done . Queue the event then call the idle code to do the wake up . /* * GPR - loss wakeups are relatively straightforward , because the * idle sleep code has saved all non - volatile registers on its * own stack , and r1 in PACAR1 . * * For no - loss wakeups the r1 and lr registers used by the * early machine check handler have to be restored first . r2 is * the kernel TOC , so no need to restore it . * * Then decrement MCE nesting after finishing with the stack . ld r3,_MSR(r1)ld r4,_LINK(r1)ld r1,GPR1(r1)1 47 -31 ,30 ,31 2 /* no state loss, return to idle caller with r3=SRR1 */ /* * We are going down . But there are chances that we might get hit by * another MCE during panic path and we may run into unstable state * with no way out . Hence , turn ME bit off while going down , so that * when another MCE is hit during panic path , system will checkstop * and hypervisor will get restarted cleanly by SP . 0 /* clear MSR_RI */ 1 ld r10,PACAKMSR(r13)1 /* * Invoke machine_check_exception to print MCE event and panic . * This is the NMI version of the handler because we are called from * the early handler which is a true NMI . /* * We will not reach here . Even if we did , there is no way out . * Call unrecoverable_exception and die . /** * Interrupt 0 x300 - Data Storage Interrupt ( DSI ) . * This is a synchronous interrupt generated due to a data access exception , * e . g . , a load orstore which does not have a valid page table entry with * permissions . DAWR matches also fault here , as do RC updates , and minor misc * errors e . g . , copy / paste , AMO , certain invalid CI accesses , etc . * * Handling : * - Hash MMU * Go to do_hash_fault , which attempts to fill the HPT from an entry in the * Linux page table . Hash faults can hit in kernel mode in a fairly * arbitrary state ( e . g . , interrupts disabled , locks held ) when accessing * " non - bolted " regions , e . g . , vmalloc space . However these should always be * backed by Linux page table entries . * * If no entry is found the Linux page fault handler is invoked ( by * do_hash_fault ) . Linux page faults can happen in kernel mode due to user * copy operations of course . * * KVM : The KVM HDSI handler may perform a load with MSR [ DR ] = 1 in guest * MMU context , which may cause a DSI in the host , which must go to the * KVM handler . MSR [ IR ] is not enabled , so the real - mode handler will * always be used regardless of AIL setting . * * - Radix MMU * The hardware loads from the Linux page table directly , so a fault goes * immediately to Linux page fault . * * Conditions like DAWR match are handled on the way in to Linux page fault . 0 x3001 1 1 0 x300, 0 x80)0 0 x300, 0 x80)0 x4300, 0 x80)1 0 x4300, 0 x80)ld r4,_DSISR(r1)1 f1 : bl CFUNC(do_break)/* * do_break ( ) may have changed the NV GPRS while handling a breakpoint . * If so , we need to restore them with their updated values . /** * Interrupt 0 x380 - Data Segment Interrupt ( DSLB ) . * This is a synchronous interrupt in response to an MMU fault missing SLB * entry for HPT , or an address outside RPT translation range . * * Handling : * - HPT : * This refills the SLB , or reports an access fault similarly to a bad page * fault . When coming from user - mode , the SLB handler may access any kernel * data , though it may itself take a DSLB . When coming from kernel mode , * recursive faults must be avoided so access is restricted to the kernel * image text / data , kernel stack , and any data allocated below * ppc64_bolted_size ( first segment ) . The kernel handler must avoid stomping * on user - handler data structures . * * KVM : Same as 0 x300 , DSLB must test for KVM guest . 0 x3801 1 0 x380, 0 x80)0 0 x380, 0 x80)0 x4380, 0 x80)1 0 x4380, 0 x80)/* HPT case, do SLB fault */ 0 1 f1 : /* Error case */ /* Radix case, access is outside page table range */ /** * Interrupt 0 x400 - Instruction Storage Interrupt ( ISI ) . * This is a synchronous interrupt in response to an MMU fault due to an * instruction fetch . * * Handling : * Similar to DSI , though in response to fetch . The faulting address is found * in SRR0 ( rather than DAR ) , and status in SRR1 ( rather than DSISR ) . 0 x4001 1 1 1 0 x400, 0 x80)0 0 x400, 0 x80)0 x4400, 0 x80)1 0 x4400, 0 x80)/** * Interrupt 0 x480 - Instruction Segment Interrupt ( ISLB ) . * This is a synchronous interrupt in response to an MMU fault due to an * instruction fetch . * * Handling : * Similar to DSLB , though in response to fetch . The faulting address is found * in SRR0 ( rather than DAR ) . 0 x4801 1 1 0 x480, 0 x80)0 0 x480, 0 x80)0 x4480, 0 x80)1 0 x4480, 0 x80)/* HPT case, do SLB fault */ 0 1 f1 : /* Error case */ /* Radix case, access is outside page table range */ /** * Interrupt 0 x500 - External Interrupt . * This is an asynchronous maskable interrupt in response to an " external * exception " from the interrupt controller or hypervisor ( e . g . , device * interrupt ) . It is maskable in hardware by clearing MSR [ EE ] , and * soft - maskable with IRQS_DISABLED mask ( i . e . , local_irq_disable ( ) ) . * * When running in HV mode , Linux sets up the LPCR [ LPES ] bit such that * interrupts are delivered with HSRR registers , guests use SRRs , which * reqiures IHSRR_IF_HVMODE . * * On bare metal POWER9 and later , Linux sets the LPCR [ HVICE ] bit such that * external interrupts are delivered as Hypervisor Virtualization Interrupts * rather than External Interrupts . * * Handling : * This calls into Linux IRQ handler . NVGPRs are not saved to reduce overhead , * because registers at the time of the interrupt are not so important as it is * asynchronous . * * If soft masked , the masked handler will note the pending interrupt for * replay , and clear MSR [ EE ] in the interrupted context . * * CFAR is not required because this is an asynchronous interrupt that in * general won ' t have much bearing on the state of the CPU , with the possible * exception of crash / debug IPIs , but those are generally moving to use SRESET * IPIs . Unless this is an HV interrupt and KVM HV is possible , in which case * it may be exiting the guest and need CFAR to be saved . 0 x5001 1 1 0 1 0 x500, 0 x100)0 0 x500, 0 x100)0 x4500, 0 x100)1 0 x4500, 0 x100)/** * Interrupt 0 x600 - Alignment Interrupt * This is a synchronous interrupt in response to data alignment fault . 0 x6001 1 1 0 x600, 0 x100)0 0 x600, 0 x100)0 x4600, 0 x100)1 0 x4600, 0 x100)/* instruction emulation may change GPRs */ /** * Interrupt 0 x700 - Program Interrupt ( program check ) . * This is a synchronous interrupt in response to various instruction faults : * traps , privilege errors , TM errors , floating point exceptions . * * Handling : * This interrupt may use the " emergency stack " in some cases when being taken * from kernel context , which complicates handling . 0 x7001 0 x700, 0 x100)0 0 x700, 0 x100)0 x4700, 0 x100)1 0 x4700, 0 x100)/* * It ' s possible to receive a TM Bad Thing type program check with * userspace register values ( in particular r1 ) , but with SRR1 reporting * that we came from the kernel . Normally that would confuse the bad * stack logic , and we would report a bad kernel stack pointer . Instead * we switch to the emergency stack if we ' re taking a TM Bad Thing from * the kernel . /* If userspace, go normal path */ /* If TM, emergency */ /* check if r1 is in userspace */ /* normal path if not */ /* Use the emergency stack */ /* Set CR0 correctly for label */ /* 3 in EXCEPTION_PROLOG_COMMON */ /* Save r1 */ ld r1,PACAEMERGSP(r13) /* Use emergency stack */ /* alloc stack frame */ 0 1 /* instruction emulation may change GPRs */ /* * Interrupt 0 x800 - Floating - Point Unavailable Interrupt . * This is a synchronous interrupt in response to executing an fp instruction * with MSR [ FP ] = 0 . * * Handling : * This will load FP registers and enable the FP bit if coming from userspace , * otherwise report a bad kernel use of FP . 0 x8001 1 0 x800, 0 x100)0 0 x800, 0 x100)0 x4800, 0 x100)1 0 x4800, 0 x100)1 f /* if from user, just load it up */ 0 : trap0 b, __FILE__, __LINE__, 0 1 :/* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in * transaction ) , go do TM stuff 64 -MSR_TS_LG), (64 -2 )2 f2 : /* User process was in a transaction */ /** * Interrupt 0 x900 - Decrementer Interrupt . * This is an asynchronous interrupt in response to a decrementer exception * ( e . g . , DEC has wrapped below zero ) . It is maskable in hardware by clearing * MSR [ EE ] , and soft - maskable with IRQS_DISABLED mask ( i . e . , * local_irq_disable ( ) ) . * * Handling : * This calls into Linux timer handler . NVGPRs are not saved ( see 0 x500 ) . * * If soft masked , the masked handler will note the pending interrupt for * replay , and bump the decrementer to a high value , leaving MSR [ EE ] enabled * in the interrupted context . * If PPC_WATCHDOG is configured , the soft masked handler will actually set * things back up to run soft_nmi_interrupt as a regular interrupt handler * on the emergency stack . * * CFAR is not required because this is asynchronous ( see hardware_interrupt ) . * A watchdog interrupt may like to have CFAR , but usually the interesting * branch is long gone by that point ( e . g . , infinite loop ) . 0 x9001 0 0 x900, 0 x80)0 0 x900, 0 x80)0 x4900, 0 x80)1 0 x4900, 0 x80)/** * Interrupt 0 x980 - Hypervisor Decrementer Interrupt . * This is an asynchronous interrupt , similar to 0 x900 but for the HDEC * register . * * Handling : * Linux does not use this outside KVM where it ' s used to keep a host timer * while the guest is given control of DEC . It should normally be caught by * the KVM test and routed there . 0 x9801 0 1 1 0 x980, 0 x80)0 0 x980, 0 x80)0 x4980, 0 x80)1 0 x4980, 0 x80)/* * Hypervisor decrementer interrupts not caught by the KVM test * shouldn ' t occur but are sometimes left pending on exit from a KVM * guest . We don ' t need to do anything to clear them , as they are * edge - triggered . * * Be careful to avoid touching the kernel stack . 0 ld r10,PACA_EXGEN+EX_CTR(r13)0 x80,r9ld r9,PACA_EXGEN+EX_R9(r13)ld r10,PACA_EXGEN+EX_R10(r13)ld r11,PACA_EXGEN+EX_R11(r13)ld r12,PACA_EXGEN+EX_R12(r13)ld r13,PACA_EXGEN+EX_R13(r13)/** * Interrupt 0 xa00 - Directed Privileged Doorbell Interrupt . * This is an asynchronous interrupt in response to a msgsndp doorbell . * It is maskable in hardware by clearing MSR [ EE ] , and soft - maskable with * IRQS_DISABLED mask ( i . e . , local_irq_disable ( ) ) . * * Handling : * Guests may use this for IPIs between threads in a core if the * hypervisor supports it . NVGPRS are not saved ( see 0 x500 ) . * * If soft masked , the masked handler will note the pending interrupt for * replay , leaving MSR [ EE ] enabled in the interrupted context because the * doorbells are edge triggered . * * CFAR is not required , similarly to hardware_interrupt . 0 xa001 0 0 xa00, 0 x100)0 0 xa00, 0 x100)0 x4a00, 0 x100)1 0 x4a00, 0 x100)0 xb00, 0 x100)0 x4b00, 0 x100)/** * Interrupt 0 xc00 - System Call Interrupt ( syscall , hcall ) . * This is a synchronous interrupt invoked with the " sc " instruction . The * system call is invoked with " sc 0 " and does not alter the HV bit , so it * is directed to the currently running OS . The hypercall is invoked with * " sc 1 " and it sets HV = 1 , so it elevates to hypervisor . * * In HPT , sc 1 always goes to 0 xc00 real mode . In RADIX , sc 1 can go to * 0 x4c00 virtual mode . * * Handling : * If the KVM test fires then it was due to a hypercall and is accordingly * routed to KVM . Otherwise this executes a normal Linux system call . * * Call convention : * * syscall and hypercalls register conventions are documented in * Documentation / arch / powerpc / syscall64 - abi . rst and * Documentation / arch / powerpc / papr_hcalls . rst respectively . * * The intersection of volatile registers that don ' t contain possible * inputs is : cr0 , xer , ctr . We may use these as scratch regs upon entry * without saving , though xer is not a good idea to use , as hardware may * interpret some bits so it may be costly to change them . 0 xc001 1 0 /* * There is a little bit of juggling to get syscall and hcall * working well . Save r13 in ctr to avoid using SPRG scratch * register . * * Userspace syscalls have already saved the PPR , hcalls must save * it before setting HMT_MEDIUM . /* uses r10, branch to kvm_hcall */ /* We reach here with PACA in r13, r13 in r9. */ ! \virt 0 xc00, 0 x100)0 0 xc00, 0 x100)0 x4c00, 0 x100)1 0 x4c00, 0 x100)0 /* * Save the PPR ( on systems that support it ) before changing to * HMT_MEDIUM . That allows the KVM code to save that value into the * guest state ( it is the guest ' s PPR value ) . /* * Requires _ _ LOAD_FAR_HANDLER beause kvmppc_hcall lives * outside the head section . /** * Interrupt 0 xd00 - Trace Interrupt . * This is a synchronous interrupt in response to instruction step or * breakpoint faults . 0 xd001 0 xd00, 0 x100)0 0 xd00, 0 x100)0 x4d00, 0 x100)1 0 x4d00, 0 x100)/** * Interrupt 0 xe00 - Hypervisor Data Storage Interrupt ( HDSI ) . * This is a synchronous interrupt in response to an MMU fault caused by a * guest data access . * * Handling : * This should always get routed to KVM . In radix MMU mode , this is caused * by a guest nested radix access that can ' t be performed due to the * partition scope page table . In hash mode , this can be caused by guests * running with translation disabled ( virtual real mode ) or with VPM enabled . * KVM will update the page table structures or disallow the access . 0 xe001 1 1 1 1 0 xe00, 0 x20)0 , ool=1 0 xe00, 0 x20)0 x4e00, 0 x20)1 , ool=1 0 x4e00, 0 x20)/** * Interrupt 0 xe20 - Hypervisor Instruction Storage Interrupt ( HISI ) . * This is a synchronous interrupt in response to an MMU fault caused by a * guest instruction fetch , similar to HDSI . 0 xe201 1 1 0 xe20, 0 x20)0 , ool=1 0 xe20, 0 x20)0 x4e20, 0 x20)1 , ool=1 0 x4e20, 0 x20)/** * Interrupt 0 xe40 - Hypervisor Emulation Assistance Interrupt . 0 xe401 1 1 0 xe40, 0 x20)0 , ool=1 0 xe40, 0 x20)0 x4e40, 0 x20)1 , ool=1 0 x4e40, 0 x20)/* instruction emulation may change GPRs */ /** * Interrupt 0 xe60 - Hypervisor Maintenance Interrupt ( HMI ) . * This is an asynchronous interrupt caused by a Hypervisor Maintenance * Exception . It is always taken in real mode but uses HSRR registers * unlike SRESET and MCE . * * It is maskable in hardware by clearing MSR [ EE ] , and partially soft - maskable * with IRQS_DISABLED mask ( i . e . , local_irq_disable ( ) ) . * * Handling : * This is a special case , this is handled similarly to machine checks , with an * initial real mode handler that is not soft - masked , which attempts to fix the * problem . Then a regular handler which is soft - maskable and reports the * problem . * * The emergency stack is used for the early real mode handler . * * XXX : unclear why MCE and HMI schemes could not be made common , e . g . , * either use soft - masking for the MCE , or use irq_work for the HMI . * * KVM : * Unlike MCE , this calls into KVM without calling the real mode handler * first . 0 xe601 1 0 0 /* We don't touch AMR here, we never go to virtual mode */ 1 0 xe601 1 0 xe60, 0 x20)0 , ool=1 0 xe60, 0 x20)0 x4e60, 0 x20)/* Save r1 */ ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */ /* alloc stack frame */ 0 1 f1 1 :/* * Go to virtual mode and pull the HMI event information from * firmware . 1 0 /** * Interrupt 0 xe80 - Directed Hypervisor Doorbell Interrupt . * This is an asynchronous interrupt in response to a msgsnd doorbell . * Similar to the 0 xa00 doorbell but for host rather than guest . * * CFAR is not required ( similar to doorbell_interrupt ) , unless KVM HV * is enabled , in which case it may be a guest exit . Most PowerNV kernels * include KVM support so it would be nice if this could be dynamically * patched out if KVM was not currently running any guests . 0 xe801 1 1 0 0 xe80, 0 x20)0 , ool=1 0 xe80, 0 x20)0 x4e80, 0 x20)1 , ool=1 0 x4e80, 0 x20)/** * Interrupt 0 xea0 - Hypervisor Virtualization Interrupt . * This is an asynchronous interrupt in response to an " external exception " . * Similar to 0 x500 but for host only . * * Like h_doorbell , CFAR is only required for KVM HV because this can be * a guest exit . 0 xea01 1 1 0 0 xea0, 0 x20)0 , ool=1 0 xea0, 0 x20)0 x4ea0, 0 x20)1 , ool=1 0 x4ea0, 0 x20)0 xec0, 0 x20)0 x4ec0, 0 x20)0 xee0, 0 x20)0 x4ee0, 0 x20)/* * Interrupt 0 xf00 - Performance Monitor Interrupt ( PMI , PMU ) . * This is an asynchronous interrupt in response to a PMU exception . * It is maskable in hardware by clearing MSR [ EE ] , and soft - maskable with * IRQS_PMI_DISABLED mask ( NOTE : NOT local_irq_disable ( ) ) . * * Handling : * This calls into the perf subsystem . * * Like the watchdog soft - nmi , it appears an NMI interrupt to Linux , in that it * runs under local_irq_disable . However it may be soft - masked in * powerpc - specific code . * * If soft masked , the masked handler will note the pending interrupt for * replay , and clear MSR [ EE ] in the interrupted context . * * CFAR is not used by perf interrupts so not required . 0 xf001 0 0 xf00, 0 x20)0 , ool=1 0 xf00, 0 x20)0 x4f00, 0 x20)1 , ool=1 0 x4f00, 0 x20)1 f1 :/* Clear MSR_RI before setting SRR0 and SRR1. */ 0 1 0 /** * Interrupt 0 xf20 - Vector Unavailable Interrupt . * This is a synchronous interrupt in response to * executing a vector ( or altivec ) instruction with MSR [ VEC ] = 0 . * Similar to FP unavailable . 0 xf201 1 0 xf20, 0 x20)0 , ool=1 0 xf20, 0 x20)0 x4f20, 0 x20)1 , ool=1 0 x4f20, 0 x20)1 f69 )/* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in * transaction ) , go do TM stuff 64 -MSR_TS_LG), (64 -2 )2 f69 )2 : /* User process was in a transaction */ 1 :/** * Interrupt 0 xf40 - VSX Unavailable Interrupt . * This is a synchronous interrupt in response to * executing a VSX instruction with MSR [ VSX ] = 0 . * Similar to FP unavailable . 0 xf401 1 0 xf40, 0 x20)0 , ool=1 0 xf40, 0 x20)0 x4f40, 0 x20)1 , ool=1 0 x4f40, 0 x20)1 f69 )/* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in * transaction ) , go do TM stuff 64 -MSR_TS_LG), (64 -2 )2 f69 )2 : /* User process was in a transaction */ 1 :/** * Interrupt 0 xf60 - Facility Unavailable Interrupt . * This is a synchronous interrupt in response to * executing an instruction without access to the facility that can be * resolved by the OS ( e . g . , FSCR , MSR ) . * Similar to FP unavailable . 0 xf601 0 xf60, 0 x20)0 , ool=1 0 xf60, 0 x20)0 x4f60, 0 x20)1 , ool=1 0 x4f60, 0 x20)/* instruction emulation may change GPRs */ /** * Interrupt 0 xf60 - Hypervisor Facility Unavailable Interrupt . * This is a synchronous interrupt in response to * executing an instruction without access to the facility that can only * be resolved in HV mode ( e . g . , HFSCR ) . * Similar to FP unavailable . 0 xf801 1 1 0 xf80, 0 x20)0 , ool=1 0 xf80, 0 x20)0 x4f80, 0 x20)1 , ool=1 0 x4f80, 0 x20)/* XXX Shouldn't be necessary in practice */ 0 xfa0, 0 x20)0 x4fa0, 0 x20)0 xfc0, 0 x20)0 x4fc0, 0 x20)0 xfe0, 0 x20)0 x4fe0, 0 x20)0 x1000, 0 x100)0 x5000, 0 x100)0 x1100, 0 x100)0 x5100, 0 x100)0 x1200, 0 x100)0 x5200, 0 x100)/** * Interrupt 0 x1300 - Instruction Address Breakpoint Interrupt . * This has been removed from the ISA before 2 . 01 , which is the earliest * 64 - bit BookS ISA supported , however the G5 / 970 implements this * interrupt with a non - architected feature available through the support * processor interface . 0 x13001 0 x1300, 0 x100)0 0 x1300, 0 x100)0 x5300, 0 x100)1 0 x5300, 0 x100)0 x1400, 0 x100)0 x5400, 0 x100)/** * Interrupt 0 x1500 - Soft Patch Interrupt * * Handling : * This is an implementation specific interrupt which can be used for a * range of exceptions . * * This interrupt handler is unique in that it runs the denormal assist * code even for guests ( and even in guest context ) without going to KVM , * for speed . POWER9 does not raise denorm exceptions , so this special case * could be phased out in future to reduce special cases . 0 x15001 0 1 0 x1500, 0 x100)0 /* denorm? */ 0 0 x1500, 0 x100)0 x5500, 0 x100)1 /* denorm? */ 1 0 x5500, 0 x100)0 x5500, 0 x100)/* * To denormalise we need to move a copy of the register to itself . * For POWER6 do that here for all FP regs . 0 32 1 /* * To denormalise we need to move a copy of the register to itself . * For POWER7 do that here for the first 32 VSX registers only . 0 32 1 /* * To denormalise we need to move a copy of the register to itself . * For POWER8 we need to do that for all 64 VSX registers 32 32 1 4 0 x80,r9ld r9,PACA_EXGEN+EX_R9(r13)ld r10,PACA_EXGEN+EX_PPR(r13)ld r10,PACA_EXGEN+EX_CFAR(r13)0 ld r10,PACA_EXGEN+EX_R10(r13)ld r11,PACA_EXGEN+EX_R11(r13)ld r12,PACA_EXGEN+EX_R12(r13)ld r13,PACA_EXGEN+EX_R13(r13)0 x1600, 0 x100)0 x5600, 0 x100)0 x17001 0 x1700, 0 x100)0 0 x1700, 0 x100)0 x5700, 0 x100)1 0 x5700, 0 x100)/* instruction emulation may change GPRs */ 0 x1800, 0 x100)0 x5800, 0 x100)0 x9000 0 /* * Branch to soft_nmi_interrupt using the emergency stack . The emergency * stack is one that is usable by maskable interrupts so long as MSR_EE * remains off . It is used for recovery when something has corrupted the * normal kernel stack , for example . The " soft NMI " must not use the process * stack because we want irq disabled sections to avoid touching the stack * at all ( other than PMU interrupts ) , so use the emergency stack for this , * and run it entirely with interrupts hard disabled . ld r1,PACAEMERGSP(r13)/* Clear MSR_RI before setting SRR0 and SRR1. */ 0 1 0 /* CONFIG_PPC_WATCHDOG */ /* * An interrupt came in while soft - disabled . We set paca - > irq_happened , then : * - If it was a decrementer interrupt , we bump the dec to max and return . * - If it was a doorbell we return immediately since doorbells are edge * triggered and won ' t automatically refire . * - If it was a HMI we return immediately since we handled it in realmode * and it won ' t refire . * - Else it is one of PACA_IRQ_MUST_HARD_MASK , so hard disable and return . * This is called with r10 containing the value to OR to the paca field . 0 /* * Ensure there was no previous MUST_HARD_MASK interrupt or * HARD_DIS setting . If this does fire , the interrupt is still * masked and MSR [ EE ] will be cleared on return , so no need to * panic , but somebody probably enabled MSR [ EE ] under * PACA_IRQ_HARD_DIS , mtmsr ( mfmsr ( ) | MSR_x ) being a common * cause . 0 : tdnei r9,0 0 b,__FILE__,__LINE__,(BUGFLAG_WARNING | BUGFLAG_ONCE)! \hsrr 1 f0 x7fffffff)2 f1 : andi. r10,r10,PACA_IRQ_MUST_HARD_MASK2 f/* clear MSR_EE */ 2 : /* done */ 0 0 3 f3 :ld r9,PACA_EXGEN+EX_CTR(r13)0 x80,r9ld r9,PACA_EXGEN+EX_R9(r13)ld r10,PACA_EXGEN+EX_R10(r13)ld r11,PACA_EXGEN+EX_R11(r13)ld r12,PACA_EXGEN+EX_R12(r13)ld r13,PACA_EXGEN+EX_R13(r13)/* May return to masked low address where r13 is not set up */ ld r9,PACA_EXRFI+EX_R9(r13)ld r10,PACA_EXRFI+EX_R10(r13)31 ,31 ,0 14 1 f1 :/* Clobbers r10, r11, ctr */ ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)ld r11,PACA_L1D_FLUSH_SIZE(r13)7 + 3 ) /* 128 byte lines, unrolled 8x */ /* Stop prefetch streams */ /* order ld/st prior to dcbt stop all streams with flushing */ /* * The load addresses are at staggered offsets within cachelines , * which suits some pipelines better ( on others it should not * hurt ) . 1 :ld r11,(0 x80 + 8 )*0 (r10)ld r11,(0 x80 + 8 )*1 (r10)ld r11,(0 x80 + 8 )*2 (r10)ld r11,(0 x80 + 8 )*3 (r10)ld r11,(0 x80 + 8 )*4 (r10)ld r11,(0 x80 + 8 )*5 (r10)ld r11,(0 x80 + 8 )*6 (r10)ld r11,(0 x80 + 8 )*7 (r10)0 x80*8 1 bld r9,PACA_EXRFI+EX_R9(r13)ld r10,PACA_EXRFI+EX_R10(r13)ld r11,PACA_EXRFI+EX_R11(r13)/* * The SCV entry flush happens with interrupts enabled , so it must disable * to prevent EXRFI being clobbered by NMIs ( e . g . , soft_nmi_common ) . r10 * ( containing LR ) does not need to be preserved here because scv entry * puts 0 in the pt_regs , CTR can be clobbered for the same reason . 0 1 ld r11,PACA_EXRFI+EX_R11(r13)1 ld r1,PACAKSAVE(r13)ld r9,PACA_EXRFI+EX_R9(r13)ld r10,PACA_EXRFI+EX_R10(r13)ld r11,PACA_EXRFI+EX_R11(r13)ld r1,PACA_EXRFI+EX_R12(r13)ld r1,PACAKSAVE(r13)ld r9,PACA_EXRFI+EX_R9(r13)ld r10,PACA_EXRFI+EX_R10(r13)ld r11,PACA_EXRFI+EX_R11(r13)ld r1,PACA_EXRFI+EX_R12(r13)/* system call volatile */ ld r1,PACAKSAVE(r13)ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)ld r11,PACA_L1D_FLUSH_SIZE(r13)7 + 3 ) /* 128 byte lines, unrolled 8x */ /* Stop prefetch streams */ /* order ld/st prior to dcbt stop all streams with flushing */ /* * The load adresses are at staggered offsets within cachelines , * which suits some pipelines better ( on others it should not * hurt ) . 1 :ld r11,(0 x80 + 8 )*0 (r10)ld r11,(0 x80 + 8 )*1 (r10)ld r11,(0 x80 + 8 )*2 (r10)ld r11,(0 x80 + 8 )*3 (r10)ld r11,(0 x80 + 8 )*4 (r10)ld r11,(0 x80 + 8 )*5 (r10)ld r11,(0 x80 + 8 )*6 (r10)ld r11,(0 x80 + 8 )*7 (r10)0 x80*8 1 b0 0 0 /* * The conditional branch in KVMTEST can ' t reach all the way , * make a stub . GLOBAL (do_uaccess_flush)1 /* * All code below _ _ end_soft_masked is treated as soft - masked . If * any code runs here with MSR [ EE ] = 1 , it must then cope with pending * soft interrupt being raised ( i . e . , by ensuring it is replayed ) . * * The _ _ end_interrupts marker must be past the out - of - line ( OOL ) * handlers , so that they are copied to real address 0 x100 when running * a relocatable kernel . This ensures they can be reached from the short * trampoline handlers ( like 0 x4f00 , 0 x4f20 , etc . ) which branch * directly , without using LOAD_HANDLER ( ) . align 7 /* MSR[RI] should be clear because this uses SRR[01] */ GLOBAL (enable_machine_check)20 ,31 ,$+4 0 : mflr r31 f - 0 b)1 : mtlr r0/* MSR[RI] should be clear because this uses SRR[01] */ 20 ,31 ,$+4 0 : mflr r31 f - 0 b)1 : mtlr r0 Messung V0.5 in Prozent C=93 H=100 G=96
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