/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2003-2013 Altera Corporation * All rights reserved.
*/
#include <linux/linkage.h>
#include <asm/entry.h>
.set noat
.set nobreak
/* * Explicitly allow the use of r1 (the assembler temporary register) * within this code. This register is normally reserved for the use of * the compiler.
*/
/* INSTRUCTION EMULATION * --------------------- * * Nios II processors generate exceptions for unimplemented instructions. * The routines below emulate these instructions. Depending on the * processor core, the only instructions that might need to be emulated * are div, divu, mul, muli, mulxss, mulxsu, and mulxuu. * * The emulations match the instructions, except for the following * limitations: * * 1) The emulation routines do not emulate the use of the exception * temporary register (et) as a source operand because the exception * handler already has modified it. * * 2) The routines do not emulate the use of the stack pointer (sp) or * the exception return address register (ea) as a destination because * modifying these registers crashes the exception handler or the * interrupted routine. * * Detailed Design * --------------- * * The emulation routines expect the contents of integer registers r0-r31 * to be on the stack at addresses sp, 4(sp), 8(sp), ... 124(sp). The * routines retrieve source operands from the stack and modify the * destination register's value on the stack prior to the end of the * exception handler. Then all registers except the destination register * are restored to their previous values. * * The instruction that causes the exception is found at address -4(ea). * The instruction's OP and OPX fields identify the operation to be * performed. * * One instruction, muli, is an I-type instruction that is identified by * an OP field of 0x24. * * muli AAAAA,BBBBB,IIIIIIIIIIIIIIII,-0x24- * 27 22 6 0 <-- LSB of field * * The remaining emulated instructions are R-type and have an OP field * of 0x3a. Their OPX fields identify them. * * R-type AAAAA,BBBBB,CCCCC,XXXXXX,NNNNN,-0x3a- * 27 22 17 11 6 0 <-- LSB of field * * * Opcode Encoding. muli is identified by its OP value. Then OPX & 0x02 * is used to differentiate between the division opcodes and the * remaining multiplication opcodes. * * Instruction OP OPX OPX & 0x02 * ----------- ---- ---- ---------- * muli 0x24 * divu 0x3a 0x24 0 * div 0x3a 0x25 0 * mul 0x3a 0x27 != 0 * mulxuu 0x3a 0x07 != 0 * mulxsu 0x3a 0x17 != 0 * mulxss 0x3a 0x1f != 0
*/
/* * Save everything on the stack to make it easy for the emulation * routines to retrieve the source register operands.
*/
/* * Get the operands. * * It is necessary to check for muli because it uses an I-type * instruction format, while the other instructions are have an R-type * format. * * Prepare for either multiplication or division loop. * They both loop 32 times.
*/
movi r14, 32
add r3, r3, sp /* r3 = address of A-operand. */
ldw r3, 0(r3) /* r3 = A-operand. */
movi r7, 0x24 /* muli opcode (I-type instruction format) */
beq r2, r7, mul_immed /* muli doesn't use the B register as a source */
/* DIVISION * * Divide an unsigned dividend by an unsigned divisor using * a shift-and-subtract algorithm. The example below shows * 43 div 7 = 6 for 8-bit integers. This classic algorithm uses a * single register to store both the dividend and the quotient, * allowing both values to be shifted with a single instruction. * * remainder dividend:quotient * --------- ----------------- * initialize 00000000 00101011: * shift 00000000 0101011:_ * remainder >= divisor? no 00000000 0101011:0 * shift 00000000 101011:0_ * remainder >= divisor? no 00000000 101011:00 * shift 00000001 01011:00_ * remainder >= divisor? no 00000001 01011:000 * shift 00000010 1011:000_ * remainder >= divisor? no 00000010 1011:0000 * shift 00000101 011:0000_ * remainder >= divisor? no 00000101 011:00000 * shift 00001010 11:00000_ * remainder >= divisor? yes 00001010 11:000001 * remainder -= divisor - 00000111 * ---------- * 00000011 11:000001 * shift 00000111 1:000001_ * remainder >= divisor? yes 00000111 1:0000011 * remainder -= divisor - 00000111 * ---------- * 00000000 1:0000011 * shift 00000001 :0000011_ * remainder >= divisor? no 00000001 :00000110 * * The quotient is 00000110.
*/
divide: /* * Prepare for division by assuming the result * is unsigned, and storing its "sign" as 0.
*/
movi r17, 0
/* Which division opcode? */
xori r7, r4, 0x25 /* OPX of div */
bne r7, zero, unsigned_division
/* * OPX is div. Determine and store the sign of the quotient. * Then take the absolute value of both operands.
*/
xor r17, r3, r5 /* MSB contains sign of quotient */
bge r3,zero,dividend_is_nonnegative sub r3, zero, r3 /* -r3 */
dividend_is_nonnegative:
bge r5, zero, divisor_is_nonnegative sub r5, zero, r5 /* -r5 */
divisor_is_nonnegative:
/* Now * r3 = quotient * r4 = 0x25 for div, 0x24 for divu * r6 = 4*C * r17 = MSB contains sign of quotient
*/
/* * Conditionally negate signed quotient. If quotient is unsigned, * the sign already is initialized to 0.
*/
bge r17, zero, quotient_is_nonnegative sub r3, zero, r3 /* -r3 */
quotient_is_nonnegative:
/* * Final quotient is in r3.
*/
add r6, r6, sp
stw r3, 0(r6) /* write quotient to stack */
br restore_registers
/* MULTIPLICATION * * A "product" is the number that one gets by summing a "multiplicand" * several times. The "multiplier" specifies the number of copies of the * multiplicand that are summed. * * Actual multiplication algorithms don't use repeated addition, however. * Shift-and-add algorithms get the same answer as repeated addition, and * they are faster. To compute the lower half of a product (pppp below) * one shifts the product left before adding in each of the partial * products (a * mmmm) through (d * mmmm). * * To compute the upper half of a product (PPPP below), one adds in the * partial products (d * mmmm) through (a * mmmm), each time following * the add by a right shift of the product. * * mmmm * * abcd * ------ * #### = d * mmmm * #### = c * mmmm * #### = b * mmmm * #### = a * mmmm * -------- * PPPPpppp * * The example above shows 4 partial products. Computing actual Nios II * products requires 32 partials. * * It is possible to compute the result of mulxsu from the result of * mulxuu because the only difference between the results of these two * opcodes is the value of the partial product associated with the sign * bit of rA. * * mulxsu = mulxuu - (rA < 0) ? rB : 0; * * It is possible to compute the result of mulxss from the result of * mulxsu because the only difference between the results of these two * opcodes is the value of the partial product associated with the sign * bit of rB. * * mulxss = mulxsu - (rB < 0) ? rA : 0; *
*/
mul_immed: /* Opcode is muli. Change it into mul for remainder of algorithm. */
mov r6, r5 /* Field B is dest register, not field C. */
mov r5, r4 /* Field IMM16 is src2, not field B. */
movi r4, 0x27 /* OPX of mul is 0x27 */
multiply: /* Initialize the multiplication loop. */
movi r9, 0 /* mul_product = 0 */
movi r10, 0 /* mulxuu_product = 0 */
mov r11, r5 /* save original multiplier for mulxsu and mulxss */
mov r12, r5 /* mulxuu_multiplier (will be shifted) */
movi r16, 1 /* used to create "rori B,A,1" from "ror B,A,r16" */
/* Compute mulxss * * mulxss = mulxsu - (rB < 0) ? rA : 0;
*/
bge r11,zero,mulxss_skip sub r9, r9, r3
mulxss_skip: /* At this point, assume that OPX is mulxss, so store*/
store_product:
stw r9, 0(r6)
restore_registers: /* No need to restore r0. */
ldw r5, 100(sp)
wrctl estatus, r5
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