// SPDX-License-Identifier: GPL-2.0-or-later /***************************************************************************/ /* * m53xx . c - - platform support for ColdFire 53 xx based boards * * Copyright ( C ) 1999 - 2002 , Greg Ungerer ( gerg @ snapgear . com ) * Copyright ( C ) 2000 , Lineo ( www . lineo . com ) * Yaroslav Vinogradov yaroslav . vinogradov @ freescale . com * Copyright Freescale Semiconductor , Inc 2006 * Copyright ( c ) 2006 , emlix , Sebastian Hess < shess @ hessware . de > /***************************************************************************/ #include <linux/clkdev.h>#include <linux/kernel.h>#include <linux/param.h>#include <linux/init.h>#include <linux/io.h>#include <asm /machdep.h>#include <asm /coldfire.h>#include <asm /mcfsim.h>#include <asm /mcfuart.h>#include <asm /mcfdma.h>#include <asm /mcfwdebug.h>#include <asm /mcfclk.h>/***************************************************************************/ 0 , "flexbus" , 2 , MCF_CLK);0 , "mcfcan.0" , 8 , MCF_CLK);0 , "fec.0" , 12 , MCF_CLK);0 , "edma" , 17 , MCF_CLK);0 , "intc.0" , 18 , MCF_CLK);0 , "intc.1" , 19 , MCF_CLK);0 , "iack.0" , 21 , MCF_CLK);0 , "imx1-i2c.0" , 22 , MCF_CLK);0 , "mcfqspi.0" , 23 , MCF_CLK);0 , "mcfuart.0" , 24 , MCF_BUSCLK);0 , "mcfuart.1" , 25 , MCF_BUSCLK);0 , "mcfuart.2" , 26 , MCF_BUSCLK);0 , "mcftmr.0" , 28 , MCF_CLK);0 , "mcftmr.1" , 29 , MCF_CLK);0 , "mcftmr.2" , 30 , MCF_CLK);0 , "mcftmr.3" , 31 , MCF_CLK);0 , "mcfpit.0" , 32 , MCF_CLK);0 , "mcfpit.1" , 33 , MCF_CLK);0 , "mcfpit.2" , 34 , MCF_CLK);0 , "mcfpit.3" , 35 , MCF_CLK);0 , "mcfpwm.0" , 36 , MCF_CLK);0 , "mcfeport.0" , 37 , MCF_CLK);0 , "mcfwdt.0" , 38 , MCF_CLK);0 , "sys.0" , 40 , MCF_BUSCLK);0 , "gpio.0" , 41 , MCF_BUSCLK);0 , "mcfrtc.0" , 42 , MCF_CLK);0 , "mcflcd.0" , 43 , MCF_CLK);0 , "mcfusb-otg.0" , 44 , MCF_CLK);0 , "mcfusb-host.0" , 45 , MCF_CLK);0 , "sdram.0" , 46 , MCF_CLK);0 , "ssi.0" , 47 , MCF_CLK);0 , "pll.0" , 48 , MCF_CLK);1 , "mdha.0" , 32 , MCF_CLK);1 , "skha.0" , 33 , MCF_CLK);1 , "rng.0" , 34 , MCF_CLK);static struct clk_lookup m53xx_clk_lookup[] = {"flexbus" , NULL, &__clk_0_2),"mcfcan.0" , NULL, &__clk_0_8),"fec.0" , NULL, &__clk_0_12),"edma" , NULL, &__clk_0_17),"intc.0" , NULL, &__clk_0_18),"intc.1" , NULL, &__clk_0_19),"iack.0" , NULL, &__clk_0_21),"imx1-i2c.0" , NULL, &__clk_0_22),"mcfqspi.0" , NULL, &__clk_0_23),"mcfuart.0" , NULL, &__clk_0_24),"mcfuart.1" , NULL, &__clk_0_25),"mcfuart.2" , NULL, &__clk_0_26),"mcftmr.0" , NULL, &__clk_0_28),"mcftmr.1" , NULL, &__clk_0_29),"mcftmr.2" , NULL, &__clk_0_30),"mcftmr.3" , NULL, &__clk_0_31),"mcfpit.0" , NULL, &__clk_0_32),"mcfpit.1" , NULL, &__clk_0_33),"mcfpit.2" , NULL, &__clk_0_34),"mcfpit.3" , NULL, &__clk_0_35),"mcfpwm.0" , NULL, &__clk_0_36),"mcfeport.0" , NULL, &__clk_0_37),"mcfwdt.0" , NULL, &__clk_0_38),"sys.0" , &__clk_0_40),"gpio.0" , NULL, &__clk_0_41),"mcfrtc.0" , NULL, &__clk_0_42),"mcflcd.0" , NULL, &__clk_0_43),"mcfusb-otg.0" , NULL, &__clk_0_44),"mcfusb-host.0" , NULL, &__clk_0_45),"sdram.0" , NULL, &__clk_0_46),"ssi.0" , NULL, &__clk_0_47),"pll.0" , &__clk_0_48),"mdha.0" , NULL, &__clk_1_32),"skha.0" , NULL, &__clk_1_33),"rng.0" , NULL, &__clk_1_34),static struct clk * const enable_clks[] __initconst = {/* flexbus */ /* intc.0 */ /* intc.1 */ /* iack.0 */ /* mcfuart.0 */ /* mcfuart.1 */ /* mcfuart.2 */ /* mcftmr.0 */ /* mcftmr.1 */ /* mcfpit.0 */ /* mcfpit.1 */ /* mcfeport.0 */ /* sys.0 */ /* gpio.0 */ /* sdram.0 */ /* pll.0 */ static struct clk * const disable_clks[] __initconst = {/* mcfcan.0 */ /* fec.0 */ /* edma */ /* imx1-i2c.0 */ /* mcfqspi.0 */ /* mcftmr.2 */ /* mcftmr.3 */ /* mcfpit.2 */ /* mcfpit.3 */ /* mcfpwm.0 */ /* mcfwdt.0 */ /* mcfrtc.0 */ /* mcflcd.0 */ /* mcfusb-otg.0 */ /* mcfusb-host.0 */ /* ssi.0 */ /* mdha.0 */ /* skha.0 */ /* rng.0 */ static void __init m53xx_clk_init(void )unsigned i;/* make sure these clocks are enabled */ for (i = 0 ; i < ARRAY_SIZE(enable_clks); ++i)/* make sure these clocks are disabled */ for (i = 0 ; i < ARRAY_SIZE(disable_clks); ++i)/***************************************************************************/ static void __init m53xx_qspi_init(void )#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)/* setup QSPS pins for QSPI with gpio CS control */ 0 x01f0, MCFGPIO_PAR_QSPI);#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ /***************************************************************************/ static void __init m53xx_i2c_init(void )#if IS_ENABLED(CONFIG_I2C_IMX)/* setup Port AS Pin Assignment Register for I2C */ /* set PASPA0 to SCL and PASPA1 to SDA */ 0 x0f;#endif /* IS_ENABLED(CONFIG_I2C_IMX) */ /***************************************************************************/ static void __init m53xx_uarts_init(void )/* UART GPIO initialization */ 0 x0FFF, MCFGPIO_PAR_UART);/***************************************************************************/ static void __init m53xx_fec_init(void )/* Set multi-function pins to ethernet mode for fec0 */ /***************************************************************************/ void __init config_BSP(char *commandp, int size)#if !defined (CONFIG_BOOTPARAM)/* Copy command line from FLASH to local buffer... */ char *) 0 x4000, 4 );if (strncmp(commandp, "kcl " , 4 ) == 0 ){char *) 0 x4004, size);1 ] = 0 ;else {0 , size);#endif #ifdef CONFIG_BDM_DISABLE/* * Disable the BDM clocking . This also turns off most of the rest of * the BDM device . This is good for EMC reasons . This option is not * incompatible with the memory protection option . #endif /***************************************************************************/ /* Board initialization */ /***************************************************************************/ /* * PLL min / max specifications #define MAX_FVCO 500000 /* KHz */ #define MAX_FSYS 80000 /* KHz */ #define MIN_FSYS 58333 /* KHz */ #define FREF 16000 /* KHz */ #define MAX_MFD 135 /* Multiplier */ #define MIN_MFD 88 /* Multiplier */ #define BUSDIV 6 /* Divider */ /* * Low Power Divider specifications #define MIN_LPD (1 << 0 ) /* Divider (not encoded) */ #define MAX_LPD (1 << 15 ) /* Divider (not encoded) */ #define DEFAULT_LPD (1 << 1 ) /* Divider (not encoded) */ #define SYS_CLK_KHZ 80000 #define SYSTEM_PERIOD 12 .5 /* * SDRAM Timing Parameters #define SDRAM_BL 8 /* # of beats in a burst */ #define SDRAM_TWR 2 /* in clocks */ #define SDRAM_CASL 2 .5 /* CASL in clocks */ #define SDRAM_TRCD 2 /* in clocks */ #define SDRAM_TRP 2 /* in clocks */ #define SDRAM_TRFC 7 /* in clocks */ #define SDRAM_TREFI 7800 /* in ns */ #define EXT_SRAM_ADDRESS (0 xC0000000)#define FLASH_ADDRESS (0 x00000000)#define SDRAM_ADDRESS (0 x40000000)#define NAND_FLASH_ADDRESS (0 xD0000000)void wtm_init(void );void scm_init(void );void gpio_init(void );void fbcs_init(void );void sdramc_init(void );int clock_pll (int fsys, int flags);int clock_limp (int );int clock_exit_limp (void );int get_sys_clock (void );void __init sysinit(void )0 , 0 );void wtm_init(void )/* Disable watchdog timer */ 0 , MCF_WTM_WCR);#define MCF_SCM_BCR_GBW (0 x00000100)#define MCF_SCM_BCR_GBR (0 x00000200)void scm_init(void )/* All masters are trusted */ 0 x77777777, MCF_SCM_MPR);/* Allow supervisor/user, read/write, and trusted/untrusted 0 , MCF_SCM_PACRA);0 , MCF_SCM_PACRB);0 , MCF_SCM_PACRC);0 , MCF_SCM_PACRD);0 , MCF_SCM_PACRE);0 , MCF_SCM_PACRF);/* Enable bursts */ void fbcs_init(void )0 x3E, MCFGPIO_PAR_CS);/* Latch chip select */ 0 x10080000, MCF_FBCS1_CSAR);0 x002A3780, MCF_FBCS1_CSCR);/* Initialize latch to drive signals to inactive states */ 0 xffff, 0 x10080000);/* External SRAM */ 1 ),/* Boot Flash connected to FBCS0 */ 7 ),void sdramc_init(void )/* * Check to see if the SDRAM has already been initialized * by a run control tool if (!(readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) {/* SDRAM chip select initialization */ /* Initialize SDRAM chip select */ /* * Basic configuration and initialization int )((SDRAM_CASL + 2 ) + 0 .5 )) |1 ) |int )((SDRAM_CASL * 2 ) + 2 )) |int )(SDRAM_TRCD + 0 .5 )) |int )(SDRAM_TRP + 0 .5 )) |int )(SDRAM_TRFC + 0 .5 )) |3 ),2 + 1 ) |2 + SDRAM_TWR) |int )((SDRAM_CASL + SDRAM_BL / 2 - 1 .0 ) + 0 .5 )) |1 ),/* * Precharge and enable write to SDMR 1 ) |int )(((SDRAM_TREFI / (SYSTEM_PERIOD * 64 )) - 1 ) + 0 .5 )) |/* * Write extended mode register 0 x0) |/* * Write mode register and reset DLL 0 x163) |/* * Execute a PALL command /* * Perform two REF cycles /* * Write mode register and clear reset DLL 0 x063) |/* * Enable auto refresh and lock SDMR 0 xC),void gpio_init(void )/* Enable UART0 pins */ /* * Initialize TIN3 as a GPIO output to enable the write * half of the latch . 0 x00, MCFGPIO_PAR_TIMER);0 x08, MCFGPIO_PDDR_TIMER);0 x00, MCFGPIO_PCLRR_TIMER);int clock_pll(int fsys, int flags)int fref, temp, fout, mfd;if (fsys == 0 ) {/* Return current PLL output */ return (fref * mfd / (BUSDIV * 4 ));/* Check bounds of requested system clock */ if (fsys > MAX_FSYS)if (fsys < MIN_FSYS)/* Multiplying by 100 when calculating the temp value, and then dividing by 100 to calculate the mfd allows for exact values without needing to include floating 100 * fsys / fref;4 * BUSDIV * temp / 100 ;/* Determine the output frequency for selected values */ 4 ));/* * Check to see if the SDRAM has already been initialized . * If it has then the SDRAM needs to be put into self refresh * mode before reprogramming the PLL . if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)/* Put SDRAM into self refresh mode */ /* * Initialize the PLL to generate the new system clock frequency . * The device must be put into LIMP mode to reprogram the PLL . /* Enter LIMP mode */ /* Reprogram PLL for desired fsys */ 3 ) | MCF_PLL_PODR_BUSDIV(BUSDIV),/* Exit LIMP mode */ /* * Return the SDRAM to normal operation if it is in use . if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)/* Exit self refresh mode */ /* Errata - workaround for SDRAM operation after exiting LIMP mode */ /* wait for DQS logic to relock */ for (i = 0 ; i < 0 x200; i++)return fout;int clock_limp(int div)/* Check bounds of divider */ if (div < MIN_LPD)if (div > MAX_LPD)/* Save of the current value of the SSIDIV so we don't 0 xF);/* Apply the divider to the system clock */ return (FREF/(3 *(1 << div)));int clock_exit_limp(void )int fout;/* Exit LIMP mode */ /* Wait for PLL to lock */ while (!(readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_PLL_LOCK))return fout;int get_sys_clock(void )int divider;/* Test to see if device is in LIMP mode */ if (readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_LIMP) {0 xF);return (FREF/(2 << divider));else return (FREF * readb(MCF_PLL_PFDR)) / (BUSDIV * 4 );
Messung V0.5 in Prozent C=94 H=95 G=94
¤ Dauer der Verarbeitung: 0.12 Sekunden
(vorverarbeitet am 2026-09-28)
¤ *© Formatika GbR, Deutschland
