// SPDX-License-Identifier: GPL-2.0-only /* * Contains CPU feature definitions * * Copyright ( C ) 2015 ARM Ltd . * * A note for the weary kernel hacker : the code here is confusing and hard to * follow ! That ' s partly because it ' s solving a nasty problem , but also because * there ' s a little bit of over - abstraction that tends to obscure what ' s going * on behind a maze of helper functions and macros . * * The basic problem is that hardware folks have started gluing together CPUs * with distinct architectural features ; in some cases even creating SoCs where * user - visible instructions are available only on a subset of the available * cores . We try to address this by snapshotting the feature registers of the * boot CPU and comparing these with the feature registers of each secondary * CPU when bringing them up . If there is a mismatch , then we update the * snapshot state to indicate the lowest - common denominator of the feature , * known as the " safe " value . This snapshot state can be queried to view the * " sanitised " value of a feature register . * * The sanitised register values are used to decide which capabilities we * have in the system . These may be in the form of traditional " hwcaps " * advertised to userspace or internal " cpucaps " which are used to configure * things like alternative patching and static keys . While a feature mismatch * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint , a capability mismatch * may prevent a CPU from being onlined at all . * * Some implementation details worth remembering : * * - Mismatched features are * always * sanitised to a " safe " value , which * usually indicates that the feature is not supported . * * - A mismatched feature marked with FTR_STRICT will cause a " SANITY CHECK " * warning when onlining an offending CPU and the kernel will be tainted * with TAINT_CPU_OUT_OF_SPEC . * * - Features marked as FTR_VISIBLE have their sanitised value visible to * userspace . FTR_VISIBLE features in registers that are only visible * to EL0 by trapping * must * have a corresponding HWCAP so that late * onlining of CPUs cannot lead to features disappearing at runtime . * * - A " feature " is typically a 4 - bit register field . A " capability " is the * high - level description derived from the sanitised field value . * * - Read the Arm ARM ( DDI 0487 F . a ) section D13 . 1 . 3 ( " Principles of the ID * scheme for fields in ID registers " ) to understand when feature fields * may be signed or unsigned ( FTR_SIGNED and FTR_UNSIGNED accordingly ) . * * - KVM exposes its own view of the feature registers to guest operating * systems regardless of FTR_VISIBLE . This is typically driven from the * sanitised register values to allow virtual CPUs to be migrated between * arbitrary physical CPUs , but some features not present on the host are * also advertised and emulated . Look at sys_reg_descs [ ] for the gory * details . * * - If the arm64_ftr_bits [ ] for a register has a missing field , then this * field is treated as STRICT RES0 , including for read_sanitised_ftr_reg ( ) . * This is stronger than FTR_HIDDEN and can be used to hide features from * KVM guests . #define pr_fmt(fmt) "CPU features: " fmt#include <linux/bsearch.h>#include <linux/cpumask.h>#include <linux/crash_dump.h>#include <linux/kstrtox.h>#include <linux/sort.h>#include <linux/stop_machine.h>#include <linux/sysfs.h>#include <linux/types.h>#include <linux/minmax.h>#include <linux/mm.h>#include <linux/cpu.h>#include <linux/kasan.h>#include <linux/percpu.h>#include <linux/sched/isolation.h>#include <asm /cpu.h>#include <asm /cpufeature.h>#include <asm /cpu_ops.h>#include <asm /fpsimd.h>#include <asm /hwcap.h>#include <asm /insn.h>#include <asm /kvm_host.h>#include <asm /mmu.h>#include <asm /mmu_context.h>#include <asm /mte.h>#include <asm /hypervisor.h>#include <asm /processor.h>#include <asm /smp.h>#include <asm /sysreg.h>#include <asm /traps.h>#include <asm /vectors.h>#include <asm /virt.h>/* Kernel representation of AT_HWCAP and AT_HWCAP2 */ static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly;#ifdef CONFIG_COMPAT#define COMPAT_ELF_HWCAP_DEFAULT \unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;unsigned int compat_elf_hwcap2 __read_mostly;unsigned int compat_elf_hwcap3 __read_mostly;#endif static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS];/* * arm64_use_ng_mappings must be placed in the . data section , otherwise it * ends up in the . bss section where it is initialized in early_map_kernel ( ) * after the MMU ( with the idmap ) was enabled . create_init_idmap ( ) - which * runs before early_map_kernel ( ) and reads the variable via PTE_MAYBE_NG - * may end up generating an incorrect idmap page table attributes . bool arm64_use_ng_mappings __read_mostly = false ;const char *, this_cpu_vector) = vectors;/* * Permit PER_LINUX32 and execve ( ) of 32 - bit binaries even if not all CPUs * support it ? static bool __read_mostly allow_mismatched_32bit_el0;/* * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have * seen at least one CPU capable of 32 - bit EL0 . /* * Mask of CPUs supporting 32 - bit EL0 . * Only valid if arm64_mismatched_32bit_el0 is enabled . static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly;void dump_cpu_features(void )/* file-wide pr_fmt adds "CPU features: " prefix */ "0x%*pb\n" , ARM64_NCAPS, &system_cpucaps);#define __ARM64_MAX_POSITIVE(reg, field) \## _## field## _SIGNED ? \## _## field## _WIDTH - 1 ) : \## _## field## _WIDTH)) - 1 )#define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg## _## field## _WIDTH - 1 )#define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \## reg, \## _## field## _SHIFT, \## _## field## _WIDTH, \## _## field## _SIGNED , \/* * ARM64_CPUID_FIELDS ( ) encodes a field with a range from min_value to * an implicit maximum that depends on the sign - ess of the field . * * An unsigned field will be capped at all ones , while a signed field * will be limited to the positive half only . #define ARM64_CPUID_FIELDS(reg, field, min_value) \/* * ARM64_CPUID_FIELDS_NEG ( ) encodes a field with a range from an * implicit minimal value to max_value . This should be used when * matching a non - implemented property . #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \#define __ARM64_FTR_BITS(SIGNED , VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \SIGNED , \/* Define a feature with unsigned values */ #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \/* Define a feature with a signed value */ #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \#define ARM64_FTR_END \0 , \static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);static bool __system_matches_cap(unsigned int n);/* * NOTE : Any changes to the visibility of features should be kept in * sync with the documentation of the CPU feature register ABI . static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {, 4 , 0 ),4 , 0 ),4 , 0 ),4 0 ),4 , 0 ),4 0 ),4 0 ),, 4 , 0 ),4 0 ),FT, 4 , 0 ),T, 4 , 0 ),, 4 , 0 ),, 4 , 0 ),4 0 ),static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {4 , 0 , 4 , 0 ),4 0 ),, 4 , 0 ),FT, 4 , 0 ),4 , 0 ),IFT, 4 , 0 ),4 , 0 ),4 , 0 ),T, 4 , 0 ),, 4 , 0 ),T, 4 , 0 ),4 , 0 ),4 , 0 ),4 0 ),static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {FT, 4 , 0 ),IFT, 4 , 0 ),HIFT, 4 , 0 ),T, 4 , 0 ),4 , 0 ),, 4 , 0 ),4 , 0 ),4 , 0 ),HIFT, 4 , 0 ),IFT, 4 , 0 ),static const struct arm64_ftr_bits ftr_id_aa64isar3[] = {SHIFT, 4 , 0 ),X_SHIFT, 4 , 0 ),static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {T, 4 , 0 ),T, 4 , 0 ),4 , 0 ),, 4 , 0 ),4 , 0 ),T, 4 , 0 ),4 , 0 ),4 , 0 4 , 0 HIFT, 4 , ID_AA64PFR0_EL1_AdvSIMD_NI),4 , 4 , 0 ),, 4 , 0 ),, 4 , ID_AA64PFR0_EL1_EL1_IMP),, 4 , ID_AA64PFR0_EL1_EL0_IMP),static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {4 , 0 4 , 0 ),HIFT, 4 , 0 ),4 , 0 ),IFT, 4 , 0 ),FT, 4 , 0 ),4 , ID_AA64PFR1_EL1_MTE_NI),FT, 4 , ID_AA64PFR1_EL1_SSBS_NI),4 , 0 ),static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = {4 0 ),HIFT, 4 , ID_AA64PFR2_EL1_MTEFAR_NI),ONLY_SHIFT, 4 , ID_AA64PFR2_EL1_MTESTOREONLY_NI),static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = {1 , 0 ),1 , 0 ),4 , 0 ),4 , 0 ),1 , 0 ),4 , 0 ),1 , 0 ),1 , 0 ),1 , 0 ),1 , 0 ),4 , 0 ),1 , 0 ),1 , 0 ),1 , 0 ),1 , 0 ),1 , 0 ),1 , 0 ),1 , 0 ),1 , 0 ),1 , 0 ),1 , 0 ),1 , 0 ),1 , 0 ),static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = {1 , 0 ),1 , 0 ),1 , 0 ),1 , 0 ),1 , 0 ),1 , 0 ),1 , 0 1 , 0 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {4 0 ),4 , 0 ),4 , 0 ),/* * Page size not being supported at Stage - 2 is not fatal . You * just give up KVM if PAGE_SIZE isn ' t supported there . Go fix * your favourite nesting hypervisor . * * There is a small corner case where the hypervisor explicitly * advertises a given granule size at Stage - 2 ( value 2 ) on some * vCPUs , and uses the fallback to Stage - 1 ( value 0 ) for other * vCPUs . Although this is not forbidden by the architecture , it * indicates that the hypervisor is being silly ( or buggy ) . * * We make no effort to cope with this and pretend that if these * fields are inconsistent across vCPUs , then it isn ' t worth * trying to bring KVM up . T, 4 , 1 ),FT, 4 , 1 ),FT, 4 , 1 ),/* * We already refuse to boot CPUs that don ' t support our configured * page size , so we can only detect mismatches for a page size other * than the one we ' re currently using . Unfortunately , SoCs like this * exist in the wild so , even though we don ' t like it , we ' ll have to go * along with it and treat them as non - strict . _SHIFT, 4 , ID_AA64MMFR0_EL1_TGRAN4_NI),4_SHIFT, 4 , ID_AA64MMFR0_EL1_TGRAN64_NI),SHIFT, 4 , ID_AA64MMFR0_EL1_TGRAN16_NI),HIFT, 4 , 0 ),/* Linux shouldn't care about secure memory */ HIFT, 4 , 0 ),T, 4 , 0 ),IFT, 4 , 0 ),/* * Differing PARange is fine as long as all peripherals and memory are mapped * within the minimum PARange of all CPUs SHIFT, 4 , 0 ),static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {, 4 , 0 ),HIFT, 4 , 0 ),4 0 ),4 , 0 ),4 , 0 ),4 0 ),4 , 0 ),IFT, 4 , 0 ),4 , 0 ),4 , 0 4 0 ),4 , 0 IFT, 4 , 0 ),T, 4 , 0 ),static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {FT, 4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 4 , 0 , 4 , 0 ),FT, 4 , 0 ),FT, 4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = {4 , 0 ),IFT, 4 , 0 ),T, 4 , 0 ),FT, 4 , 0 ),static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = {T, 4 , 0 ),FT, 4 , 0 ),static const struct arm64_ftr_bits ftr_ctr[] = {31 , 1 , 1 ), /* RES1 */ 1 , 1 ),1 , 1 ),4 0 ),4 0 ),4 , 1 ),/* * Linux can handle differing I - cache policies . Userspace JITs will * make use of * minLine . * If we have differing I - cache policies , report it as the weakest - VIPT . 2 , CTR_EL0_L1Ip_VIPT), /* L1Ip */ 4 , 0 ),static struct arm64_ftr_override __ro_after_init no_override = { };struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {"SYS_CTR_EL0" ,static const struct arm64_ftr_bits ftr_id_mmfr0[] = {T, 4 , 0 xf),4 , 0 ),, 4 , 0 ),4 , 0 ),4 0 ),T, 4 , 0 xf),4 , 0 ),4 , 0 ),static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {_SHIFT, 4 , 0 ),IFT, 4 , 0 ),FT, 4 , 0 ),4 , 0 ),4 , 0 ),/* * We can instantiate multiple PMU instances with different levels * of support . , 4 , 0 ),4 , 0 static const struct arm64_ftr_bits ftr_mvfr0[] = {4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),static const struct arm64_ftr_bits ftr_mvfr1[] = {4 , 0 4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),static const struct arm64_ftr_bits ftr_mvfr2[] = {4 , 0 ),4 , 0 ),static const struct arm64_ftr_bits ftr_dczid[] = {1 , 1 ),4 , 0 ),static const struct arm64_ftr_bits ftr_gmid[] = {4 , 0 ),static const struct arm64_ftr_bits ftr_id_isar0[] = {4 , 0 4 , 0 ),4 , 0 , 4 , 0 ),4 0 ),4 0 ),4 , 0 ),static const struct arm64_ftr_bits ftr_id_isar5[] = {4 , 0 ),4 , 0 4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),static const struct arm64_ftr_bits ftr_id_mmfr4[] = {4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),/* * SpecSEI = 1 indicates that the PE might generate an SError on an * external abort on speculative read . It is safe to assume that an * SError might be generated than it will not be . Hence it has been * classified as FTR_HIGHER_SAFE . 4 0 ),static const struct arm64_ftr_bits ftr_id_isar4[] = {4 0 ),4 , 0 ),SHIFT, 4 , 0 ),4 , 0 ),4 , 0 ),, 4 , 0 ),T, 4 , 0 ),4 , 0 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {4 , 0 ),static const struct arm64_ftr_bits ftr_id_isar6[] = {4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),static const struct arm64_ftr_bits ftr_id_pfr0[] = {4 , 0 ),4 , 0 4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 ),static const struct arm64_ftr_bits ftr_id_pfr1[] = {4 , 0 ),4 0 ),4 , 0 ),4 , 0 ),HIFT, 4 , 0 ),4 , 0 ),4 , 0 ),4 , 0 static const struct arm64_ftr_bits ftr_id_pfr2[] = {4 , 0 ),4 , 0 static const struct arm64_ftr_bits ftr_id_dfr0[] = {/* [31:28] TraceFilt */ 4 , 0 4 , 0 ),4 , 0 4 , 0 ),4 , 0 4 , 0 4 , 0 ),static const struct arm64_ftr_bits ftr_id_dfr1[] = {4 , 0 static const struct arm64_ftr_bits ftr_mpamidr[] = {, MPAMIDR_EL1_PMG_MAX_WIDTH, 0 ),T, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0 ),1 , 0 IFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0 ),/* * Common ftr bits for a 32 bit register with all hidden , strict * attributes , with 4 bit feature fields and a default safe value of * 0 . Covers the following 32 bit registers : * id_isar [ 1 - 3 ] , id_mmfr [ 1 - 3 ] static const struct arm64_ftr_bits ftr_generic_32bits[] = {28 , 4 , 0 ),24 , 4 , 0 ),20 , 4 , 0 ),16 , 4 , 0 ),12 , 4 , 0 ),8 , 4 , 0 ),4 , 4 , 0 ),0 , 4 , 0 ),/* Table for a single 32bit feature value */ static const struct arm64_ftr_bits ftr_single32[] = {0 , 32 , 0 ),static const struct arm64_ftr_bits ftr_raz[] = {#define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \struct arm64_ftr_reg){ \0 ]), \#define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \#id , id, table, ovr)#define ARM64_FTR_REG(id, table) \#id , id, table, &no_override)struct arm64_ftr_override __read_mostly id_aa64mmfr0_override;struct arm64_ftr_override __read_mostly id_aa64mmfr1_override;struct arm64_ftr_override __read_mostly id_aa64mmfr2_override;struct arm64_ftr_override __read_mostly id_aa64pfr0_override;struct arm64_ftr_override __read_mostly id_aa64pfr1_override;struct arm64_ftr_override __read_mostly id_aa64zfr0_override;struct arm64_ftr_override __read_mostly id_aa64smfr0_override;struct arm64_ftr_override __read_mostly id_aa64isar1_override;struct arm64_ftr_override __read_mostly id_aa64isar2_override;struct arm64_ftr_override __read_mostly arm64_sw_feature_override;static const struct __ftr_reg_entry {struct arm64_ftr_reg *reg;/* Op1 = 0, CRn = 0, CRm = 1 */ /* Op1 = 0, CRn = 0, CRm = 2 */ /* Op1 = 0, CRn = 0, CRm = 3 */ /* Op1 = 0, CRn = 0, CRm = 4 */ /* Op1 = 0, CRn = 0, CRm = 5 */ /* Op1 = 0, CRn = 0, CRm = 6 */ /* Op1 = 0, CRn = 0, CRm = 7 */ /* Op1 = 0, CRn = 10, CRm = 4 */ /* Op1 = 1, CRn = 0, CRm = 0 */ /* Op1 = 3, CRn = 0, CRm = 0 */ /* Op1 = 3, CRn = 14, CRm = 0 */ static int search_cmp_ftr_reg(const void *id, const void *regp)return (int )(unsigned long )id - (int )((const struct __ftr_reg_entry *)regp)->sys_id;/* * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using * its sys_reg ( ) encoding . With the array arm64_ftr_regs sorted in the * ascending order of sys_id , we use binary search to find a matching * entry . * * returns - Upon success , matching ftr_reg entry for id . * - NULL on failure . It is upto the caller to decide * the impact of a failure . static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)const struct __ftr_reg_entry *ret;const void *)(unsigned long )sys_id,sizeof (arm64_ftr_regs[0 ]),if (ret)return ret->reg;return NULL;/* * get_arm64_ftr_reg - Looks up a feature register entry using * its sys_reg ( ) encoding . This calls get_arm64_ftr_reg_nowarn ( ) . * * returns - Upon success , matching ftr_reg entry for id . * - NULL on failure but with an WARN_ON ( ) . struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)struct arm64_ftr_reg *reg;/* * Requesting a non - existent register search is an error . Warn * and let the caller handle it . return reg;static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,return reg;const struct arm64_ftr_bits *ftrp, s64 new ,0 ;switch (ftrp->type) {case FTR_EXACT:break ;case FTR_LOWER_SAFE:new , cur);break ;case FTR_HIGHER_OR_ZERO_SAFE:if (!cur || !new )break ;case FTR_HIGHER_SAFE:new , cur);break ;default :return ret;static void __init sort_ftr_regs(void )unsigned int i;for (i = 0 ; i < ARRAY_SIZE(arm64_ftr_regs); i++) {const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;unsigned int j = 0 ;/* * Features here must be sorted in descending order with respect * to their shift values and should not overlap with each other . for (; ftr_bits->width != 0 ; ftr_bits++, j++) {unsigned int width = ftr_reg->ftr_bits[j].width;unsigned int shift = ftr_reg->ftr_bits[j].shift;unsigned int prev_shift;64 ,"%s has invalid feature at shift %d\n" ,/* * Skip the first feature . There is nothing to * compare against for now . if (j == 0 )continue ;1 ].shift;"%s has feature overlap at shift %d\n" ,/* * Skip the first register . There is nothing to * compare against for now . if (i == 0 )continue ;/* * Registers here must be sorted in ascending order with respect * to sys_id for subsequent binary search in get_arm64_ftr_reg ( ) * to work correctly . 1 ].sys_id);/* * Initialise the CPU feature register from Boot CPU values . * Also initiliases the strict_mask for the register . * Any bits that are not covered by an arm64_ftr_bits entry are considered * RES0 for the system - wide value , and must strictly match . static void init_cpu_ftr_reg(u32 sys_reg, u64 new )0 ;0 x0ULL;0 ;0 ;const struct arm64_ftr_bits *ftrp;struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);if (!reg)return ;for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {new );if ((ftr_mask & reg->override->mask) == ftr_mask) {char *str = NULL;if (ftr_ovr != tmp) {/* Unsafe, remove the override */ "ignoring override" ;else if (ftr_new != tmp) {/* Override was valid */ "forced" ;else {/* Override was the safe value */ "already set" ;"%s[%d:%d]: %s to %llx\n" ,1 ,1 ));else if ((ftr_mask & reg->override->val) == ftr_mask) {"%s[%d:%d]: impossible override, ignored\n" ,1 ,if (!ftrp->strict)if (ftrp->visible)else extern const struct arm64_cpu_capabilities arm64_errata[];static const struct arm64_cpu_capabilities arm64_features[];static void __initconst struct arm64_cpu_capabilities *caps)for (; caps->matches; caps++) {if (WARN(caps->capability >= ARM64_NCAPS,"Invalid capability %d\n" , caps->capability))continue ;if (WARN(cpucap_ptrs[caps->capability],"Duplicate entry for capability %d\n" ,continue ;static void __init init_cpucap_indirect_list(void )static void __init setup_boot_cpu_capabilities(void );static void init_32bit_cpu_features(struct cpuinfo_32bit *info)#ifdef CONFIG_ARM64_PSEUDO_NMIstatic bool enable_pseudo_nmi;static int __init early_enable_pseudo_nmi(char *p)return kstrtobool(p, &enable_pseudo_nmi);"irqchip.gicv3_pseudo_nmi" , early_enable_pseudo_nmi);static __init void detect_system_supports_pseudo_nmi(void )struct device_node *np;if (!enable_pseudo_nmi)return ;/* * Detect broken MediaTek firmware that doesn ' t properly save and * restore GIC priorities . "arm,gic-v3" );if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw" )) {"Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n" );false ;#else /* CONFIG_ARM64_PSEUDO_NMI */ static inline void detect_system_supports_pseudo_nmi(void ) { }#endif void __init init_cpu_features(struct cpuinfo_arm64 *info)/* Before we start using the tables, make sure it is sorted */ if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))if (IS_ENABLED(CONFIG_ARM64_SVE) &&unsigned long cpacr = cpacr_save_enable_kernel_sve();if (IS_ENABLED(CONFIG_ARM64_SME) &&unsigned long cpacr = cpacr_save_enable_kernel_sme();if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new )const struct arm64_ftr_bits *ftrp;for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {new );if (ftr_cur == ftr_new)continue ;/* Find a safe value */ static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);if (!regp)return 0 ;if ((boot & regp->strict_mask) == (val & regp->strict_mask))return 0 ;"SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n" ,return 1 ;static void relax_cpu_ftr_reg(u32 sys_id, int field)const struct arm64_ftr_bits *ftrp;struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);if (!regp)return ;for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {if (ftrp->shift == field) {break ;/* Bogus field? */ static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info,struct cpuinfo_arm64 *boot)static bool boot_cpu_32bit_regs_overridden = false ;if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden)return ;if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0))return ;true ;static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,struct cpuinfo_32bit *boot)int taint = 0 ;/* * If we don ' t have AArch32 at EL1 , then relax the strictness of * EL1 - dependent register fields to avoid spurious sanity check fails . if (!id_aa64pfr0_32bit_el1(pfr0)) {/* * Regardless of the value of the AuxReg field , the AIFSR , ADFSR , and * ACTLR formats could differ across CPUs and therefore would have to * be trapped for virtualization anyway . return taint;/* * Update system wide CPU feature registers with the values from a * non - boot CPU . Also performs SANITY checks to make sure that there * aren ' t any insane variations from that of the boot CPU . void update_cpu_features(int cpu,struct cpuinfo_arm64 *info,struct cpuinfo_arm64 *boot)int taint = 0 ;/* * The kernel can handle differing I - cache policies , but otherwise * caches should look identical . Userspace JITs will make use of * * minLine . /* * Userspace may perform DC ZVA instructions . Mismatched block sizes * could result in too much or too little memory being zeroed if a * process is preempted and migrated between CPUs . /* If different, timekeeping will be broken (especially with KVM) */ /* * The kernel uses self - hosted debug features and expects CPUs to * support identical debug features . We presently need CTX_CMPs , WRPs , * and BRPs to be identical . * ID_AA64DFR1 is currently RES0 . /* * Even in big . LITTLE , processors should be identical instruction - set * wise . /* * Differing PARange support is fine as long as all peripherals and * memory are mapped within the minimum PARange of all CPUs . * Linux should not care about secure memory . /* Probe vector lengths */ if (IS_ENABLED(CONFIG_ARM64_SVE) &&if (!system_capabilities_finalized()) {unsigned long cpacr = cpacr_save_enable_kernel_sve();if (IS_ENABLED(CONFIG_ARM64_SME) &&unsigned long cpacr = cpacr_save_enable_kernel_sme();/* Probe vector lengths */ if (!system_capabilities_finalized())if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {/* * The kernel uses the LDGM / STGM instructions and the number of tags * they read / write depends on the GMID_EL1 . BS field . Check that the * value is the same on all CPUs . if (IS_ENABLED(CONFIG_ARM64_MTE) &&/* * If we don ' t have AArch32 at all then skip the checks entirely * as the register values may be UNKNOWN and we ' re not going to be * using them for anything . * * This relies on a sanitised view of the AArch64 ID registers * ( e . g . SYS_ID_AA64PFR0_EL1 ) , so we call it last . if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {/* * Mismatched CPU features are a recipe for disaster . Don ' t even * pretend to support them . if (taint) {"Unsupported CPU feature variation detected.\n" );struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);if (!regp)return 0 ;return regp->sys_val;#define read_sysreg_case(r) \case r: val = read_sysreg_s(r); break ;/* * _ _ read_sysreg_by_encoding ( ) - Used by a STARTING cpu before cpuinfo is populated . * Read the system register on the current CPU struct arm64_ftr_reg *regp;switch (sys_id) {default :return 0 ;if (regp) {return val;#include <linux/irqchip/arm-gic-v3.h>static bool const struct arm64_cpu_capabilities *entry, int scope)return true ;static bool const struct arm64_cpu_capabilities *entry)int val, min, max;return val >= min && val <= max;static u64const struct arm64_cpu_capabilities *entry, int scope)if (scope == SCOPE_SYSTEM)return read_sanitised_ftr_reg(entry->sys_reg);else return __read_sysreg_by_encoding(entry->sys_reg);static bool const struct arm64_cpu_capabilities *entry, int scope)int mask;struct arm64_ftr_reg *regp;if (!regp)return false ;if (!mask)return false ;return feature_matches(val, entry);static bool const struct arm64_cpu_capabilities *entry, int scope)return feature_matches(val, entry);const struct cpumask *system_32bit_el0_cpumask(void )if (!system_supports_32bit_el0())return cpu_none_mask;if (static_branch_unlikely(&arm64_mismatched_32bit_el0))return cpu_32bit_el0_mask;return cpu_possible_mask;const struct cpumask *task_cpu_fallback_mask(struct task_struct *p)return __task_cpu_possible_mask(p, housekeeping_cpumask(HK_TYPE_TICK));static int __init parse_32bit_el0_param(char *str)true ;return 0 ;"allow_mismatched_32bit_el0" , parse_32bit_el0_param);static ssize_t aarch32_el0_show(struct device *dev,struct device_attribute *attr, char *buf)const struct cpumask *mask = system_32bit_el0_cpumask();return sysfs_emit(buf, "%*pbl\n" , cpumask_pr_args(mask));static const DEVICE_ATTR_RO(aarch32_el0);static int __init aarch32_el0_sysfs_init(void )struct device *dev_root;int ret = 0 ;if (!allow_mismatched_32bit_el0)return 0 ;if (dev_root) {return ret;static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope)if (!has_cpuid_feature(entry, scope))return allow_mismatched_32bit_el0;if (scope == SCOPE_SYSTEM)"detected: 32-bit EL0 Support\n" );return true ;static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)bool has_sre;if (!has_cpuid_feature(entry, scope))return false ;if (!has_sre)"%s present but disabled by higher exception level\n" ,return has_sre;static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,int scope)if (scope == SCOPE_SYSTEM)else return ctr & BIT(CTR_EL0_IDC_SHIFT);static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)/* * If the CPU exposes raw CTR_EL0 . IDC = 0 , while effectively * CTR_EL0 . IDC = 1 ( from CLIDR values ) , we need to trap accesses * to the CTR_EL0 on this CPU and emulate it with the real / safe * value . if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT)))0 );static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,int scope)if (scope == SCOPE_SYSTEM)else return ctr & BIT(CTR_EL0_DIC_SHIFT);static bool __maybe_unusedconst struct arm64_cpu_capabilities *entry, int scope)/* * Kdump isn ' t guaranteed to power - off all secondary CPUs , CNP * may share TLB entries with a CPU stuck in the crashed * kernel . if (is_kdump_kernel())return false ;if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))return false ;return has_cpuid_feature(entry, scope);static bool __meltdown_safe = true ;static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,int scope)/* List of CPUs that are not vulnerable and don't need KPTI */ static const struct midr_range kpti_safe_list[] = {/* sentinel */ } char const *str = "kpti command line option" ;bool meltdown_safe;/* Defer to CPU feature registers */ if (has_cpuid_feature(entry, scope))true ;if (!meltdown_safe)false ;/* * For reasons that aren ' t entirely clear , enabling KPTI on Cavium * ThunderX leads to apparent I - cache corruption of kernel text , which * ends as well as you might imagine . Don ' t even try . We cannot rely * on the cpus_have_ * cap ( ) helpers here to detect the CPU erratum * because cpucap detection order may change . However , since we know * affected CPUs are always in a homogeneous configuration , it is * safe to rely on this_cpu_has_cap ( ) here . if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) {"ARM64_WORKAROUND_CAVIUM_27456" ;1 ;/* Useful for KASLR robustness */ if (kaslr_enabled() && kaslr_requires_kpti()) {if (!__kpti_forced) {"KASLR" ;1 ;if (cpu_mitigations_off() && !__kpti_forced) {"mitigations=off" ;1 ;if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {"kernel page table isolation disabled by kernel configuration\n" );return false ;/* Forced? */ if (__kpti_forced) {"kernel page table isolation forced %s by %s\n" ,0 ? "ON" : "OFF" , str);return __kpti_forced > 0 ;return !meltdown_safe;static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope)/* * Although the Apple M2 family appears to support NV1 , the * PTW barfs on the nVHE EL2 S1 page table format . Pretend * that it doesn ' t support NV1 at all . static const struct midr_range nv1_ni_list[] = {return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) &&#if defined (ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined (ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2)static bool has_lpa2_at_stage1(u64 mmfr0)unsigned int tgran;return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2;static bool has_lpa2_at_stage2(u64 mmfr0)unsigned int tgran;return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2;static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope)return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0);#else static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope)return false ;#endif #ifdef CONFIG_HW_PERF_EVENTSstatic bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope)unsigned int pmuver;/* * PMUVer follows the standard ID scheme for an unsigned field with the * exception of 0 xF ( IMP_DEF ) which is treated specially and implies * FEAT_PMUv3 is not implemented . * * See DDI0487L . a D24 . 1 . 3 . 2 for more details . if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF)return false ;return pmuver >= ID_AA64DFR0_EL1_PMUVer_IMP;#endif #ifdef CONFIG_UNMAP_KERNEL_AT_EL0#define KPTI_NG_TEMP_VA (-(1 UL << PMD_SHIFT))extern void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt,enum pgtable_type), int flags);static phys_addr_t __initdata kpti_ng_temp_alloc;static phys_addr_t __init kpti_ng_pgd_alloc(enum pgtable_type type)return kpti_ng_temp_alloc;static int __init __kpti_install_ng_mappings(void *__unused)typedef void (kpti_remap_fn)(int , int , phys_addr_t, unsigned long );extern kpti_remap_fn idmap_kpti_install_ng_mappings;int cpu = smp_processor_id();int levels = CONFIG_PGTABLE_LEVELS;int order = order_base_2(levels);0 ;0 ;if (levels == 5 && !pgtable_l5_enabled())4 ;else if (levels == 4 && !pgtable_l4_enabled())3 ;void *)__pa_symbol(idmap_kpti_install_ng_mappings);if (!cpu) {1 ) * PAGE_SIZE);// // Create a minimal page table hierarchy that permits us to map // the swapper page tables temporarily as we traverse them. // // The physical pages are laid out as follows: // // +--------+-/-------+-/------ +-/------ +-\\\--------+ // : PTE[] : | PMD[] : | PUD[] : | P4D[] : ||| PGD[] : // +--------+-\-------+-\------ +-\------ +-///--------+ // ^ // The first page is mapped into this hierarchy at a PMD_SHIFT // aligned virtual address, so that we can manipulate the PTE // level entries while the mapping is active. The first entry // covers the PTE[] page itself, the remaining entries are free // to be used as a ad-hoc fixmap. // 0 );if (!cpu) {true ;return 0 ;static void __init kpti_install_ng_mappings(void )/* Check whether KPTI is going to be used */ if (!arm64_kernel_unmapped_at_el0())return ;/* * We don ' t need to rewrite the page - tables if either we ' ve done * it already or we have KASLR enabled and therefore have not * created any global mappings at all . if (arm64_use_ng_mappings)return ;#else static inline void kpti_install_ng_mappings(void )#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap)if (__this_cpu_read(this_cpu_vector) == vectors) {const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);static int __init parse_kpti(char *str)bool enabled;int ret = kstrtobool(str, &enabled);if (ret)return ret;1 : -1 ;return 0 ;"kpti" , parse_kpti);#ifdef CONFIG_ARM64_HW_AFDBMstatic struct cpumask dbm_cpus __read_mostly;static inline void __cpu_enable_hw_dbm(void )static bool cpu_has_broken_dbm(void )/* List of CPUs which have broken DBM support. */ static const struct midr_range cpus[] = {#ifdef CONFIG_ARM64_ERRATUM_1024718/* Kryo4xx Silver (rdpe => r1p0) */ 0 xd, 0 xe),#endif #ifdef CONFIG_ARM64_ERRATUM_20516780 , 0 , 2 ),#endif return is_midr_in_range_list(cpus);static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)if (cpu_can_use_dbm(cap)) {static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,int __unused)/* * DBM is a non - conflicting feature . i . e , the kernel can safely * run a mix of CPUs with and without the feature . So , we * unconditionally enable the capability to allow any late CPU * to use the feature . We only enable the control bits on the * CPU , if it is supported . return true ;#endif #ifdef CONFIG_ARM64_AMU_EXTN/* * The " amu_cpus " cpumask only signals that the CPU implementation for the * flagged CPUs supports the Activity Monitors Unit ( AMU ) but does not provide * information regarding all the events that it supports . When a CPU bit is * set in the cpumask , the user of this feature can only rely on the presence * of the 4 fixed counters for that CPU . But this does not guarantee that the * counters are enabled or access to these counters is enabled by code * executed at higher exception levels ( firmware ) . static struct cpumask amu_cpus __read_mostly;bool cpu_has_amu_feat(int cpu)return cpumask_test_cpu(cpu, &amu_cpus);int get_cpu_with_amu_feat(void )return cpumask_any(&amu_cpus);static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {/* 0 reference values signal broken/disabled counters */ if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168))static bool has_amu(const struct arm64_cpu_capabilities *cap,int __unused)/* * The AMU extension is a non - conflicting feature : the kernel can * safely run a mix of CPUs with and without support for the * activity monitors extension . Therefore , unconditionally enable * the capability to allow any late CPU to use the feature . * * With this feature unconditionally enabled , the cpu_enable * function will be called for all CPUs that match the criteria , * including secondary and hotplugged , marking this feature as * present on that respective CPU . The enable function will also * print a detection message . return true ;#else int get_cpu_with_amu_feat(void )return nr_cpu_ids;#endif static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)return is_kernel_in_hyp_mode();static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)/* * Copy register values that aren ' t redirected by hardware . * * Before code patching , we only set tpidr_el1 , all CPUs need to copy * this value to tpidr_el2 before we patch the code . Once we ' ve done * that , freshly - onlined CPUs will set tpidr_el2 , so we don ' t need to * do anything here . if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap,int scope)if (kvm_get_mode() != KVM_MODE_NV)return false ;if (!cpucap_multi_entry_cap_matches(cap, scope)) {"unavailable: %s\n" , cap->desc);return false ;return true ;static bool hvhe_possible(const struct arm64_cpu_capabilities *entry,int __unused)return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE);static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, int scope)/* * We want to allow usage of BBML2 in as wide a range of kernel contexts * as possible . This list is therefore an allow - list of known - good * implementations that both support BBML2 and additionally , fulfill the * extra constraint of never generating TLB conflict aborts when using * the relaxed BBML2 semantics ( such aborts make use of BBML2 in certain * kernel contexts difficult to prove safe against recursive aborts ) . * * Note that implementations can only be considered " known - good " if their * implementors attest to the fact that the implementation never raises * TLB conflict aborts for BBML2 mapping granularity changes . static const struct midr_range supports_bbml2_noabort_list[] = {0 , 3 , 0 xf),0 , 2 , 0 xf),/* Does our cpu guarantee to never raise TLB conflict aborts? */ if (!is_midr_in_range_list(supports_bbml2_noabort_list))return false ;/* * We currently ignore the ID_AA64MMFR2_EL1 register , and only care * about whether the MIDR check passes . return true ;#ifdef CONFIG_ARM64_PANstatic void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)/* * We modify PSTATE . This won ' t work from irq context as the PSTATE * is discarded once we return from the exception . 0 );1 );#endif /* CONFIG_ARM64_PAN */ #ifdef CONFIG_ARM64_RAS_EXTNstatic void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)/* Firmware may have left a deferred SError in this register. */ 0 , SYS_DISR_EL1);static bool has_rasv1p1(const struct arm64_cpu_capabilities *__unused, int scope)const struct arm64_cpu_capabilities rasv1p1_caps[] = {return (has_cpuid_feature(&rasv1p1_caps[0 ], scope) ||1 ], scope) &&2 ], scope)));#endif /* CONFIG_ARM64_RAS_EXTN */ #ifdef CONFIG_ARM64_PTR_AUTHstatic bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)int boot_val, sec_val;/* We don't expect to be called with SCOPE_SYSTEM */ /* * The ptr - auth feature levels are not intercompatible with lower * levels . Hence we must match ptr - auth feature level of the secondary * CPUs with that of the boot CPU . The level of boot cpu is fetched * from the sanitised register whereas direct register read is done for * the secondary CPUs . * The sanitised feature state is guaranteed to match that of the * boot CPU as a mismatched secondary CPU is parked before it gets * a chance to update the state , with the capability . if (scope & SCOPE_BOOT_CPU)return boot_val >= entry->min_field_value;/* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ return (sec_val >= entry->min_field_value) && (sec_val == boot_val);static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,int scope)bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope);bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope);return apa || apa3 || api;static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,int __unused)bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5);bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3);return gpa || gpa3 || gpi;#endif /* CONFIG_ARM64_PTR_AUTH */ #ifdef CONFIG_ARM64_E0PDstatic void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)if (this_cpu_has_cap(ARM64_HAS_E0PD))0 , TCR_E0PD1);#endif /* CONFIG_ARM64_E0PD */ #ifdef CONFIG_ARM64_PSEUDO_NMIstatic bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,int scope)/* * ARM64_HAS_GICV3_CPUIF has a lower index , and is a boot CPU * feature , so will be detected earlier . if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF))return false ;return enable_pseudo_nmi;static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry,int scope)/* * If we ' re not using priority masking then we won ' t be poking PMR_EL1 , * and there ' s no need to relax synchronization of writes to it , and * ICC_CTLR_EL1 might not be accessible and we must avoid reads from * that . * * ARM64_HAS_GIC_PRIO_MASKING has a lower index , and is a boot CPU * feature , so will be detected earlier . if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING))return false ;/* * When Priority Mask Hint Enable ( PMHE ) = = 0 b0 , PMR is not used as a * hint for interrupt distribution , a DSB is not necessary when * unmasking IRQs via PMR , and we can relax the barrier to a NOP . * * Linux itself doesn ' t use 1 : N distribution , so has no need to * set PMHE . The only reason to have it set is if EL3 requires it * ( and we can ' t change it ) . return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0 ;#endif #ifdef CONFIG_ARM64_BTIstatic void bti_enable(const struct arm64_cpu_capabilities *__unused)/* * Use of X16 / X17 for tail - calls and trampolines that jump to * function entry points using BR is a requirement for * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI . * So , be strict and forbid other BRs using other registers to * jump onto a PACIxSP instruction : 0 , SCTLR_EL1_BT0 | SCTLR_EL1_BT1);#endif /* CONFIG_ARM64_BTI */ #ifdef CONFIG_ARM64_MTEstatic void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)static bool cleared_zero_page = false ;0 , SCTLR_ELx_ATA | SCTLR_EL1_ATA0);/* * Clear the tags in the zero page . This needs to be done via the * linear map which has the Tagged attribute . Since this page is * always mapped as pte_special ( ) , set_pte_at ( ) will not attempt to * clear the tags or set PG_mte_tagged . if (!cleared_zero_page) {true ;#endif /* CONFIG_ARM64_MTE */ static void user_feature_fixup(void )if (cpus_have_cap(ARM64_WORKAROUND_2658417)) {struct arm64_ftr_reg *regp;if (regp)if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) {struct arm64_ftr_reg *regp;if (regp)static void elf_hwcap_fixup(void )#ifdef CONFIG_COMPATif (cpus_have_cap(ARM64_WORKAROUND_1742098))#endif /* CONFIG_COMPAT */ #ifdef CONFIG_KVMstatic bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)return kvm_get_mode() == KVM_MODE_PROTECTED;#endif /* CONFIG_KVM */ static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused)0 , SCTLR_EL1_TIDCP);static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused)1 );static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused)0 , SCTLR_EL1_MSCEn);#ifdef CONFIG_ARM64_POEstatic void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused)0 , TCR2_EL1_E0POE);0 , CPACR_EL1_E0POE);#endif #ifdef CONFIG_ARM64_GCSstatic void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused)/* GCSPR_EL0 is always readable */ #endif /* Internal helper functions to match cpu capability type */ static bool const struct arm64_cpu_capabilities *cap)return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);static bool const struct arm64_cpu_capabilities *cap)return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);static bool const struct arm64_cpu_capabilities *cap)return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);static bool const struct arm64_cpu_capabilities *entry, int scope)if (!has_cpuid_feature(entry, scope))return false ;/* Check firmware actually enabled MPAM on this cpu. */ return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN);static void const struct arm64_cpu_capabilities *entry)/* * Access by the kernel ( at EL1 ) should use the reserved PARTID * which is configured unrestricted . This avoids priority - inversion * where latency sensitive tasks have to wait for a task that has * been throttled to release the lock . 0 , SYS_MPAM1_EL1);static bool const struct arm64_cpu_capabilities *entry, int scope)return idr & MPAMIDR_EL1_HAS_HCR;static const struct arm64_cpu_capabilities arm64_features[] = {"GICv3 CPU interface" ,"Enhanced Counter Virtualization" ,"Enhanced Counter Virtualization (CNTPOFF)" ,#ifdef CONFIG_ARM64_PAN"Privileged Access Never" ,#endif /* CONFIG_ARM64_PAN */ #ifdef CONFIG_ARM64_EPAN"Enhanced Privileged Access Never" ,#endif /* CONFIG_ARM64_EPAN */ #ifdef CONFIG_ARM64_LSE_ATOMICS"LSE atomic instructions" ,#endif /* CONFIG_ARM64_LSE_ATOMICS */ "Virtualization Host Extensions" ,"Nested Virtualization Support" ,const struct arm64_cpu_capabilities []){/* Sentinel */ } #ifdef CONFIG_KVM"32-bit EL1 Support" ,"Protected KVM" ,"HCRX_EL2 register" ,#endif "Kernel page table isolation (KPTI)" ,/* * The ID feature fields below are used to indicate that * the CPU doesn ' t need KPTI . See unmap_kernel_at_el0 for * more details . #ifdef CONFIG_ARM64_PMEM"Data cache clean to Point of Persistence" ,"Data cache clean to Point of Deep Persistence" ,#endif #ifdef CONFIG_ARM64_SVE"Scalable Vector Extension" ,#endif /* CONFIG_ARM64_SVE */ #ifdef CONFIG_ARM64_RAS_EXTN"RAS Extension Support" ,"RASv1p1 Extension Support" ,#endif /* CONFIG_ARM64_RAS_EXTN */ #ifdef CONFIG_ARM64_AMU_EXTN"Activity Monitors Unit (AMU)" ,#endif /* CONFIG_ARM64_AMU_EXTN */ "Data cache clean to the PoU not required for I/D coherence" ,"Instruction cache invalidation not required for I/D coherence" ,"Stage-2 Force Write-Back" ,"ARMv8.4 Translation Table Level" ,"TLB range maintenance instructions" ,#ifdef CONFIG_ARM64_HW_AFDBM"Hardware dirty bit management" ,#endif #ifdef CONFIG_ARM64_HAFT"Hardware managed Access Flag for Table Descriptors" ,/* * Contrary to the page / block access flag , the table access flag * cannot be emulated in software ( no access fault will occur ) . * Therefore this should be used only if it ' s supported system * wide . #endif "CRC32 instructions" ,"Speculative Store Bypassing Safe (SSBS)" ,#ifdef CONFIG_ARM64_CNP"Common not Private translations" ,#endif "Speculation barrier (SB)" ,#ifdef CONFIG_ARM64_PTR_AUTH"Address authentication (architected QARMA5 algorithm)" ,"Address authentication (architected QARMA3 algorithm)" ,"Address authentication (IMP DEF algorithm)" ,"Generic authentication (architected QARMA5 algorithm)" ,"Generic authentication (architected QARMA3 algorithm)" ,"Generic authentication (IMP DEF algorithm)" ,#endif /* CONFIG_ARM64_PTR_AUTH */ #ifdef CONFIG_ARM64_PSEUDO_NMI/* * Depends on having GICv3 "IRQ priority masking" ,/* * Depends on ARM64_HAS_GIC_PRIO_MASKING #endif #ifdef CONFIG_ARM64_E0PD"E0PD" ,#endif "Random Number Generator" ,#ifdef CONFIG_ARM64_BTI"Branch Target Identification" ,#ifdef CONFIG_ARM64_BTI_KERNEL#else #endif #endif #ifdef CONFIG_ARM64_MTE"Memory Tagging Extension" ,"Asymmetric MTE Tag Check Fault" ,"FAR on MTE Tag Check Fault" ,"Store Only MTE Tag Check" ,#endif /* CONFIG_ARM64_MTE */ "RCpc load-acquire (LDAPR)" ,"Fine Grained Traps" ,"Fine Grained Traps 2" ,#ifdef CONFIG_ARM64_SME"Scalable Matrix Extension" ,/* FA64 should be sorted after the base SME capability */ "FA64" ,"SME2" ,#endif /* CONFIG_ARM64_SME */ "WFx with timeout" ,"Trap EL0 IMPLEMENTATION DEFINED functionality" ,"Data independent timing control (DIT)" ,"Memory Copy and Memory Set instructions" ,"Stage-1 Permission Indirection Extension (S1PIE)" ,"VHE for hypervisor only" ,"Enhanced Virtualization Traps" ,"BBM Level 2 without TLB conflict abort" ,"52-bit Virtual Addressing for KVM (LPA2)" ,"FPMR" ,#ifdef CONFIG_ARM64_VA_BITS_52#ifdef CONFIG_ARM64_64K_PAGES"52-bit Virtual Addressing (LVA)" ,52 )#else "52-bit Virtual Addressing (LPA2)" ,#ifdef CONFIG_ARM64_4K_PAGES52 _BIT)#else 52 _BIT)#endif #endif #endif "Memory Partitioning And Monitoring" ,1 )"Memory Partitioning And Monitoring Virtualisation" ,"NV1" ,#ifdef CONFIG_ARM64_POE"Stage-1 Permission Overlay Extension (S1POE)" ,#endif #ifdef CONFIG_ARM64_GCS"Guarded Control Stack (GCS)" ,#endif #ifdef CONFIG_HW_PERF_EVENTS"PMUv3" ,#endif "SCTLR2" ,"GICv5 CPU interface" ,#define HWCAP_CPUID_MATCH(reg, field, min_value) \#define __HWCAP_CAP(name, cap_type, cap) \#define HWCAP_CAP(reg, field, min_value, cap_type, cap) \#cap , cap_type, cap) \#define HWCAP_MULTI_CAP(list, cap_type, cap) \#cap , cap_type, cap) \#define HWCAP_CAP_MATCH(match, cap_type, cap) \#cap , cap_type, cap) \#define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \#cap , cap_type, cap) \#ifdef CONFIG_ARM64_PTR_AUTHstatic const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {#endif #ifdef CONFIG_ARM64_SVEstatic bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope)return system_supports_sve() && has_user_cpuid_feature(cap, scope);#endif #ifdef CONFIG_ARM64_SMEstatic bool has_sme_feature(const struct arm64_cpu_capabilities *cap, int scope)return system_supports_sme() && has_user_cpuid_feature(cap, scope);#endif static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {#ifdef CONFIG_ARM64_SVEL_HWCAP_SVE2P2),L_HWCAP_SVE2P1),HWCAP_SVE2),P_SVEAES),_HWCAP_SVEPMULL),AP_SVE_AES2),HWCAP_SVEBITPERM),WCAP_SVE_B16B16),EL_HWCAP_SVE_BFSCALE),AP_SVEBF16),WCAP_SVE_EBF16),AP_SVESHA3),P_SVESM4),AP_SVEI8MM),CAP_SVEF32MM),CAP_SVEF64MM),CAP_SVE_F16MM),HWCAP_SVE_ELTPERM),#endif #ifdef CONFIG_ARM64_GCS#endif #ifdef CONFIG_ARM64_BTI#endif #ifdef CONFIG_ARM64_PTR_AUTH#endif #ifdef CONFIG_ARM64_MTE),#endif /* CONFIG_ARM64_MTE */ #ifdef CONFIG_ARM64_SMECAP_SME_FA64),WCAP_SME_LUTV2),EL_HWCAP_SME2P2),EL_HWCAP_SME2P1),_HWCAP_SME2),HWCAP_SME_I16I64),HWCAP_SME_F64F64),HWCAP_SME_I16I32),HWCAP_SME_B16B16),HWCAP_SME_F16F16),WCAP_SME_F8F16),WCAP_SME_F8F32),WCAP_SME_I8I32),HWCAP_SME_F16F32),HWCAP_SME_B16F32),_HWCAP_SME_BI32I32),HWCAP_SME_F32F32),HWCAP_SME_SF8FMA),HWCAP_SME_SF8DP4),HWCAP_SME_SF8DP2),L_HWCAP_SME_SBITPERM),AP_SME_AES),HWCAP_SME_SFEXPA),WCAP_SME_STMOP),WCAP_SME_SMOP4),#endif /* CONFIG_ARM64_SME */ #ifdef CONFIG_ARM64_POE#endif #ifdef CONFIG_COMPATstatic bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)/* * Check that all of MVFR1_EL1 . { SIMDSP , SIMDInt , SIMDLS } are available , * in line with that of arm32 as in vfp_init ( ) . We make sure that the * check is future proof , by making sure value is non - zero . if (scope == SCOPE_SYSTEM)else return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) &&#endif static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {#ifdef CONFIG_COMPAT/* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ #endif static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)switch (cap->hwcap_type) {case CAP_HWCAP:break ;#ifdef CONFIG_COMPATcase CAP_COMPAT_HWCAP:break ;case CAP_COMPAT_HWCAP2:break ;#endif default :1 );break ;/* Check if we have a particular HWCAP enabled */ static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)bool rc;switch (cap->hwcap_type) {case CAP_HWCAP:break ;#ifdef CONFIG_COMPATcase CAP_COMPAT_HWCAP:0 ;break ;case CAP_COMPAT_HWCAP2:0 ;break ;#endif default :1 );false ;return rc;static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)/* We support emulation of accesses to CPU ID feature registers */ for (; hwcaps->matches; hwcaps++)if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))static void update_cpu_capabilities(u16 scope_mask)int i;const struct arm64_cpu_capabilities *caps;for (i = 0 ; i < ARM64_NCAPS; i++) {bool match_all = false ;bool caps_set = false ;bool boot_cpu = false ;if (!caps || !(caps->type & scope_mask))continue ;/* * Unless it ' s a match - all CPUs feature , avoid probing if * already detected . if (!match_all && caps_set)continue ;/* * A match - all CPUs capability is only set when probing the * boot CPU . It may be cleared subsequently if not detected on * secondary ones . if (match_all && !caps_set && !boot_cpu)continue ;if (!caps->matches(caps, cpucap_default_scope(caps))) {if (match_all)continue ;/* * Match - all CPUs capabilities are logged later when the * system capabilities are finalised . if (!match_all && caps->desc && !caps->cpus)"detected: %s\n" , caps->desc);if (boot_cpu && (caps->type & SCOPE_BOOT_CPU))/* * Enable all the available capabilities on this CPU . The capabilities * with BOOT_CPU scope are handled separately and hence skipped here . static int cpu_enable_non_boot_scope_capabilities(void *__unused)int i;const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i];if (WARN_ON(!cap))continue ;if (!(cap->type & non_boot_scope))continue ;if (cap->cpu_enable)return 0 ;/* * Run through the enabled capabilities and enable ( ) it on all active * CPUs static void __init enable_cpu_capabilities(u16 scope_mask)int i;const struct arm64_cpu_capabilities *caps;bool boot_scope;for (i = 0 ; i < ARM64_NCAPS; i++) {if (!caps || !(caps->type & scope_mask) ||continue ;if (boot_scope && caps->cpu_enable)/* * Capabilities with SCOPE_BOOT_CPU scope are finalised * before any secondary CPU boots . Thus , each secondary * will enable the capability as appropriate via * check_local_cpu_capabilities ( ) . The only exception is * the boot CPU , for which the capability must be * enabled here . This approach avoids costly * stop_machine ( ) calls for this case . /* * For all non - boot scope capabilities , use stop_machine ( ) * as it schedules the work allowing us to modify PSTATE , * instead of on_each_cpu ( ) which uses an IPI , giving us a * PSTATE that disappears when we return . if (!boot_scope)/* * Run through the list of capabilities to check for conflicts . * If the system has already detected a capability , take necessary * action on this CPU . static void verify_local_cpu_caps(u16 scope_mask)int i;bool cpu_has_cap, system_has_cap;const struct arm64_cpu_capabilities *caps;for (i = 0 ; i < ARM64_NCAPS; i++) {if (!caps || !(caps->type & scope_mask))continue ;if (system_has_cap) {/* * Check if the new CPU misses an advertised feature , * which is not safe to miss . if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))break ;/* * We have to issue cpu_enable ( ) irrespective of * whether the CPU has it or not , as it is enabeld * system wide . It is upto the call back to take * appropriate action on this CPU . if (caps->cpu_enable)else {/* * Check if the CPU has this capability if it isn ' t * safe to have when the system doesn ' t . if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))break ;if (i < ARM64_NCAPS) {"CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n" ,if (cpucap_panic_on_conflict(caps))else /* * Check for CPU features that are used in early boot * based on the Boot CPU value . static void check_early_cpu_features(void )static void const struct arm64_cpu_capabilities *caps)for (; caps->matches; caps++)if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {"CPU%d: missing HWCAP: %s\n" ,static void verify_local_elf_hwcaps(void )if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1)))static void verify_sve_features(void )unsigned long cpacr = cpacr_save_enable_kernel_sve();if (vec_verify_vq_map(ARM64_VEC_SVE)) {"CPU%d: SVE: vector length support mismatch\n" ,static void verify_sme_features(void )unsigned long cpacr = cpacr_save_enable_kernel_sme();if (vec_verify_vq_map(ARM64_VEC_SME)) {"CPU%d: SME: vector length support mismatch\n" ,static void verify_hyp_capabilities(void )int parange, ipa_max;unsigned int safe_vmid_bits, vmid_bits;if (!IS_ENABLED(CONFIG_KVM))return ;/* Verify VMID bits */ if (vmid_bits < safe_vmid_bits) {"CPU%d: VMID width mismatch\n" , smp_processor_id());/* Verify IPA range */ if (ipa_max < get_kvm_ipa_limit()) {"CPU%d: IPA range mismatch\n" , smp_processor_id());static void verify_mpam_capabilities(void )if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) !="CPU%d: MPAM version mismatch\n" , smp_processor_id());if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) !="CPU%d: Missing MPAM HCR\n" , smp_processor_id());if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) {"CPU%d: MPAM PARTID/PMG max values are mismatched\n" , smp_processor_id());/* * Run through the enabled system capabilities and enable ( ) it on this CPU . * The capabilities were decided based on the available CPUs at the boot time . * Any new CPU should match the system wide status of the capability . If the * new CPU doesn ' t have a capability which the system now has enabled , we * cannot do anything to fix it up and could cause unexpected failures . So * we park the CPU . static void verify_local_cpu_capabilities(void )/* * The capabilities with SCOPE_BOOT_CPU are checked from * check_early_cpu_features ( ) , as they need to be verified * on all secondary CPUs . if (system_supports_sve())if (system_supports_sme())if (is_hyp_mode_available())if (system_supports_mpam())void check_local_cpu_capabilities(void )/* * All secondary CPUs should conform to the early CPU features * in use by the kernel based on boot CPU . /* * If we haven ' t finalised the system capabilities , this CPU gets * a chance to update the errata work arounds and local features . * Otherwise , this CPU should verify that it has all the system * advertised capabilities . if (!system_capabilities_finalized())else bool this_cpu_has_cap(unsigned int n)if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n];if (cap)return cap->matches(cap, SCOPE_LOCAL_CPU);return false ;/* * This helper function is used in a narrow window when , * - The system wide safe registers are set with all the SMP CPUs and , * - The SYSTEM_FEATURE system_cpucaps may not have been set . static bool __maybe_unused __system_matches_cap(unsigned int n)if (n < ARM64_NCAPS) {const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n];if (cap)return cap->matches(cap, SCOPE_SYSTEM);return false ;void cpu_set_feature(unsigned int num)bool cpu_have_feature(unsigned int num)return test_bit(num, elf_hwcap);unsigned long cpu_get_elf_hwcap(void )/* * We currently only populate the first 32 bits of AT_HWCAP . Please * note that for userspace compatibility we guarantee that bits 62 * and 63 will always be returned as 0 . return elf_hwcap[0 ];unsigned long cpu_get_elf_hwcap2(void )return elf_hwcap[1 ];unsigned long cpu_get_elf_hwcap3(void )return elf_hwcap[2 ];static void __init setup_boot_cpu_capabilities(void )/* * The boot CPU ' s feature register values have been recorded . Detect * boot cpucaps and local cpucaps for the boot CPU , then enable and * patch alternatives for the available boot cpucaps . void __init setup_boot_cpu_features(void )/* * Initialize the indirect array of CPU capabilities pointers before we * handle the boot CPU . /* * Detect broken pseudo - NMI . Must be called _ before_ the call to * setup_boot_cpu_capabilities ( ) since it interacts with * can_use_gic_priorities ( ) . static void __init setup_system_capabilities(void )/* * The system - wide safe feature register values have been finalized . * Detect , enable , and patch alternatives for the available system * cpucaps . for (int i = 0 ; i < ARM64_NCAPS; i++) {const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i];if (!caps || !caps->desc)continue ;/* * Log any cpucaps with a cpumask as these aren ' t logged by * update_cpu_capabilities ( ) . if (caps->cpus && cpumask_any(caps->cpus) < nr_cpu_ids)"detected: %s on CPU%*pbl\n" ,/* Log match-all CPUs capabilities */ if (cpucap_match_all_early_cpus(caps) &&"detected: %s\n" , caps->desc);/* * TTBR0 PAN doesn ' t have its own cpucap , so log it manually . if (system_uses_ttbr0_pan())"emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n" );void __init setup_system_features(void )/* * Check for sane CTR_EL0 . CWG value . if (!cache_type_cwg())"No Cache Writeback Granule information, assuming %d\n" ,void __init setup_user_features(void )if (system_supports_32bit_el0()) {static int enable_mismatched_32bit_el0(unsigned int cpu)/* * The first 32 - bit - capable CPU we detected and so can no longer * be offlined by userspace . - 1 indicates we haven ' t yet onlined * a 32 - bit - capable CPU . static int lucky_winner = -1 ;struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);bool cpu_32bit = false ;if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {if (!housekeeping_cpu(cpu, HK_TYPE_TICK))"Treating adaptive-ticks CPU %u as 64-bit only\n" , cpu);else true ;if (cpu_32bit) {if (cpumask_test_cpu(0 , cpu_32bit_el0_mask) == cpu_32bit)return 0 ;if (lucky_winner >= 0 )return 0 ;/* * We ' ve detected a mismatch . We need to keep one of our CPUs with * 32 - bit EL0 online so that is_cpu_allowed ( ) doesn ' t end up rejecting * every CPU in the system for a 32 - bit task . true ;"Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n" ,return 0 ;static int __init init_32bit_el0_mask(void )if (!allow_mismatched_32bit_el0)return 0 ;if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL))return -ENOMEM;return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,"arm64/mismatched_32bit_el0:online" ,static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)/* * We emulate only the following system register space . * Op0 = 0 x3 , CRn = 0 x0 , Op1 = 0 x0 , CRm = [ 0 , 2 - 7 ] * See Table C5 - 6 System instruction encodings for System register accesses , * ARMv8 ARM ( ARM DDI 0487 A . f ) for more details . static inline bool __attribute_const__ is_emulated(u32 id)return (sys_reg_Op0(id) == 0 x3 &&0 x0 &&0 x0 &&0 ||2 ) && (sys_reg_CRm(id) <= 7 ))));/* * With CRm = = 0 , reg should be one of : * MIDR_EL1 , MPIDR_EL1 or REVIDR_EL1 . static inline int emulate_id_reg(u32 id, u64 *valp)switch (id) {case SYS_MIDR_EL1:break ;case SYS_MPIDR_EL1:break ;case SYS_REVIDR_EL1:/* IMPLEMENTATION DEFINED values are emulated with 0 */ 0 ;break ;default :return -EINVAL;return 0 ;static int emulate_sys_reg(u32 id, u64 *valp)struct arm64_ftr_reg *regp;if (!is_emulated(id))return -EINVAL;if (sys_reg_CRm(id) == 0 )return emulate_id_reg(id, valp);if (regp)else /* * The untracked registers are either IMPLEMENTATION DEFINED * ( e . g , ID_AFR0_EL1 ) or reserved RAZ . 0 ;return 0 ;int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)int rc;if (!rc) {return rc;bool try_emulate_mrs(struct pt_regs *regs, u32 insn)if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn))return false ;/* * sys_reg values are defined as used in mrs / msr instruction . * shift the imm value to get the encoding . 5 ;return do_emulate_mrs(regs, sys_reg, rt) == 0 ;enum mitigation_state arm64_get_meltdown_state(void )if (__meltdown_safe)return SPECTRE_UNAFFECTED;if (arm64_kernel_unmapped_at_el0())return SPECTRE_MITIGATED;return SPECTRE_VULNERABLE;struct device *dev, struct device_attribute *attr,char *buf)switch (arm64_get_meltdown_state()) {case SPECTRE_UNAFFECTED:return sprintf(buf, "Not affected\n" );case SPECTRE_MITIGATED:return sprintf(buf, "Mitigation: PTI\n" );default :return sprintf(buf, "Vulnerable\n" );
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