// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Copyright (C) 2021-2024 PHYTEC America, LLC -
https://www.phytec.com
* Author: Matt McKee <mmckee@phytec.com>
*
* Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* Product homepage:
*
https://www.phytec.com/product/phycore-am64x
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "PHYTEC phyCORE-AM64x";
compatible = "phytec,am64-phycore-som", "ti,am642";
aliases {
ethernet0 = &cpsw_port1;
mmc0 = &sdhci0;
rtc0 = &i2c_som_rtc;
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
bootph-all;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
mcu_m4fss_dma_memory_region: memory@a4000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4000000 0x00 0x100000>;
no-map;
};
mcu_m4fss_memory_region: memory@a4100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: memory@a5000000 {
reg = <0x00 0xa5000000 0x00 0x00800000>;
alignment = <0x1000>;
no-map;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_pins_default>;
led-0 {
color = <LED_COLOR_ID_GREEN>;
gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
function = LED_FUNCTION_HEARTBEAT;
};
};
vcc_5v0_som: regulator-vcc-5v0-som {
/* VIN / VCC_5V0_SOM */
compatible = "regulator-fixed";
regulator-name = "VCC_5V0_SOM";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
};
&main_pmx0 {
cpsw_mdio_pins_default: cpsw-mdio-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x0100, PIN_OUTPUT, 7) /* (V7) PRG1_PRU0_GPO18.GPIO0_63 */
>;
bootph-all;
};
cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* (V12) PRG1_PRU1_GPO19.GPIO0_84 */
>;
bootph-all;
};
eeprom_wp_pins_default: eeprom-wp-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0208, PIN_OUTPUT, 7) /* (D12) SPI0_CS0.GPIO1_42 */
>;
};
leds_pins_default: leds-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* (L18) OSPI0_CSn1.GPIO0_12 */
>;
};
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */
>;
bootph-all;
};
ospi0_pins_default: ospi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
>;
bootph-all;
};
rtc_pins_default: rtc-defaults-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* (C19) EXTINTn.GPIO1_70 */
>;
};
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&cpsw_rgmii1_pins_default>;
status = "okay";
};
&cpsw3g_mdio {
pinctrl-names = "default";
pinctrl-0 = <&cpsw_mdio_pins_default>;
bootph-all;
status = "okay";
cpsw3g_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&main_gpio0>;
interrupts = <84 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
bootph-all;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
bootph-all;
status = "okay";
};
&mailbox0_cluster2 {
status = "okay";
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster4 {
status = "okay";
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster6 {
status = "okay";
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
bootph-all;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
pinctrl-names = "default";
pinctrl-0 = <&eeprom_wp_pins_default>;
pagesize = <32>;
reg = <0x50>;
};
i2c_som_rtc: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
pinctrl-names = "default";
pinctrl-0 = <&rtc_pins_default>;
interrupt-parent = <&main_gpio1>;
interrupts = <70 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
};
pmic@61 {
compatible = "ti,lp8733";
reg = <0x61>;
buck0-in-supply = <&vcc_5v0_som>;
buck1-in-supply = <&vcc_5v0_som>;
ldo0-in-supply = <&vdd_3v3>;
ldo1-in-supply = <&vdd_3v3>;
regulators {
vdd_core: buck0 {
regulator-name = "VDD_CORE";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-always-on;
regulator-boot-on;
};
vdd_3v3: buck1 {
regulator-name = "VDD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vdd_1v8_ldo0: ldo0 {
regulator-name = "VDD_1V8_LDO0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
vdda_1v8: ldo1 {
regulator-name = "VDDA_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
};
};
};
&main_pktdma {
bootph-all;
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&mcu_m4fss {
mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
memory-region = <&mcu_m4fss_dma_memory_region>,
<&mcu_m4fss_memory_region>;
status = "okay";
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
status = "okay";
serial_flash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <0>;
bootph-all;
};
};
&sdhci0 {
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
keep-power-in-suspend;
bootph-all;
status = "okay";
};
&tscadc0 {
status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
