Spracherkennung für: .dtsi vermutete Sprache: Unknown {[0] [0] [0]} [Methode: Schwerpunktbildung, einfache Gewichte, sechs Dimensionen]
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the R9A08G045S33 SMARC Carrier-II's SoM board.
*
* Copyright (C) 2023 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
#include "rzg3s-smarc-switches.h"
/ {
compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
aliases {
i2c1 = &i2c1;
mmc0 = &sdhi0;
#if SW_CONFIG3 == SW_OFF
mmc2 = &sdhi2;
#else
ethernet0 = ð0;
ethernet1 = ð1;
#endif
};
memory@48000000 {
device_type = "memory";
/* First 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
vcc_sdhi0: regulator0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&pinctrl RZG2L_GPIO(2, 1) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator1 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&pinctrl RZG2L_GPIO(2, 2) GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1>, <1800000 0>;
};
reg_1p8v: regulator2 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator3 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_sdhi2: regulator4 {
compatible = "regulator-fixed";
regulator-name = "SDHI2 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
x3_clk: x3-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
&adc {
status = "okay";
};
#if SW_CONFIG3 == SW_ON
ð0 {
pinctrl-0 = <ð0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
phy0: ethernet-phy@7 {
reg = <7>;
interrupts-extended = <&pinctrl RZG2L_GPIO(12, 0) IRQ_TYPE_EDGE_FALLING>;
rxc-skew-psec = <0>;
txc-skew-psec = <0>;
rxdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
txd0-skew-psec = <0>;
txd1-skew-psec = <0>;
txd2-skew-psec = <0>;
txd3-skew-psec = <0>;
};
};
ð1 {
pinctrl-0 = <ð1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
phy1: ethernet-phy@7 {
reg = <7>;
interrupts-extended = <&pinctrl RZG2L_GPIO(12, 1) IRQ_TYPE_EDGE_FALLING>;
rxc-skew-psec = <0>;
txc-skew-psec = <0>;
rxdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
txd0-skew-psec = <0>;
txd1-skew-psec = <0>;
txd2-skew-psec = <0>;
txd3-skew-psec = <0>;
};
};
#endif
&extal_clk {
clock-frequency = <24000000>;
};
&i2c1 {
status = "okay";
versa3: clock-generator@68 {
compatible = "renesas,5l35023";
reg = <0x68>;
clocks = <&x3_clk>;
#clock-cells = <1>;
assigned-clocks = <&versa3 0>,
<&versa3 1>,
<&versa3 2>,
<&versa3 3>,
<&versa3 4>,
<&versa3 5>;
assigned-clock-rates = <24000000>,
<12288000>,
<11289600>,
<25000000>,
<100000000>,
<100000000>;
renesas,settings = [
80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27
00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86
a0 80 30 30 9c
];
};
};
#if SW_CONFIG2 == SW_ON
/* SD0 slot */
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_uhs_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
max-frequency = <125000000>;
status = "okay";
};
#else
/* eMMC */
&sdhi0 {
pinctrl-0 = <&sdhi0_emmc_pins>;
pinctrl-1 = <&sdhi0_emmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <®_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
fixed-emmc-driver-type = <1>;
max-frequency = <125000000>;
status = "okay";
};
#endif
#if SW_CONFIG3 == SW_OFF
&sdhi2 {
pinctrl-0 = <&sdhi2_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_sdhi2>;
bus-width = <4>;
max-frequency = <50000000>;
status = "okay";
};
#endif
&pinctrl {
#if SW_CONFIG3 == SW_ON
eth0-phy-irq-hog {
gpio-hog;
gpios = <RZG2L_GPIO(12, 0) GPIO_ACTIVE_LOW>;
input;
line-name = "eth0-phy-irq";
};
#endif
eth0_pins: eth0 {
txc {
pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>; /* ET0_TXC */
power-source = <1800>;
output-enable;
input-enable;
drive-strength-microamp = <5200>;
};
tx_ctl {
pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>; /* ET0_TX_CTL */
power-source = <1800>;
output-enable;
drive-strength-microamp = <5200>;
};
mux {
pinmux = <RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
<RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
<RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
<RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
<RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
<RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
<RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */
<RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
<RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
<RZG2L_PORT_PINMUX(4, 5, 1)>; /* ET0_LINKSTA */
power-source = <1800>;
};
};
#if SW_CONFIG3 == SW_ON
eth1-phy-irq-hog {
gpio-hog;
gpios = <RZG2L_GPIO(12, 1) GPIO_ACTIVE_LOW>;
input;
line-name = "eth1-phy-irq";
};
#endif
eth1_pins: eth1 {
txc {
pinmux = <RZG2L_PORT_PINMUX(7, 0, 1)>; /* ET1_TXC */
power-source = <1800>;
output-enable;
input-enable;
drive-strength-microamp = <5200>;
};
tx_ctl {
pinmux = <RZG2L_PORT_PINMUX(7, 1, 1)>; /* ET1_TX_CTL */
power-source = <1800>;
output-enable;
drive-strength-microamp = <5200>;
};
mux {
pinmux = <RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
<RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
<RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
<RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
<RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
<RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
<RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
<RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
<RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
<RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */
<RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
<RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
<RZG2L_PORT_PINMUX(10, 4, 1)>; /* ET1_LINKSTA */
power-source = <1800>;
};
};
sdhi0_pins: sd0 {
data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
power-source = <3300>;
};
ctrl {
pins = "SD0_CLK", "SD0_CMD";
power-source = <3300>;
};
cd {
pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
};
};
sdhi0_uhs_pins: sd0-uhs {
data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
power-source = <1800>;
};
ctrl {
pins = "SD0_CLK", "SD0_CMD";
power-source = <1800>;
};
cd {
pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
};
};
sdhi0_emmc_pins: sd0-emmc {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7",
"SD0_CLK", "SD0_CMD", "SD0_RST#";
power-source = <1800>;
};
sdhi2_pins: sd2 {
data {
pins = "P11_2", "P11_3", "P12_0", "P12_1";
input-enable;
};
ctrl {
pins = "P11_1";
input-enable;
};
mux {
pinmux = <RZG2L_PORT_PINMUX(11, 0, 8)>, /* SD2_CLK */
<RZG2L_PORT_PINMUX(11, 1, 8)>, /* SD2_CMD */
<RZG2L_PORT_PINMUX(11, 2, 8)>, /* SD2_DATA0 */
<RZG2L_PORT_PINMUX(11, 3, 8)>, /* SD2_DATA1 */
<RZG2L_PORT_PINMUX(12, 0, 8)>, /* SD2_DATA2 */
<RZG2L_PORT_PINMUX(12, 1, 8)>, /* SD2_DATA3 */
<RZG2L_PORT_PINMUX(14, 1, 7)>; /* SD2_CD# */
};
};
};
&rtc {
status = "okay";
};
&vbattb {
assigned-clocks = <&vbattb VBATTB_MUX>;
assigned-clock-parents = <&vbattb VBATTB_XC>;
quartz-load-femtofarads = <12500>;
status = "okay";
};
&vbattb_xtal {
clock-frequency = <32768>;
};
&wdt0 {
timeout-sec = <60>;
status = "okay";
};
