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Quelle tegra186.dtsi
Sprache: unbekannt
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// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/gpio/tegra186-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/memory/tegra186-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
#include <dt-bindings/power/tegra186-powergate.h>
#include <dt-bindings/reset/tegra186-reset.h>
#include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
/ {
compatible = "nvidia,tegra186";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
misc@100000 {
compatible = "nvidia,tegra186-misc";
reg = <0x0 0x00100000 0x0 0xf000>,
<0x0 0x0010f000 0x0 0x1000>;
};
gpio: gpio@2200000 {
compatible = "nvidia,tegra186-gpio";
reg-names = "security", "gpio";
reg = <0x0 0x2200000 0x0 0x10000>,
<0x0 0x2210000 0x0 0x10000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
};
ethernet@2490000 {
compatible = "nvidia,tegra186-eqos",
"snps,dwc-qos-ethernet-4.10";
reg = <0x0 0x02490000 0x0 0x10000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
<&bpmp TEGRA186_CLK_EQOS_AXI>,
<&bpmp TEGRA186_CLK_EQOS_RX>,
<&bpmp TEGRA186_CLK_EQOS_TX>,
<&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
resets = <&bpmp TEGRA186_RESET_EQOS>;
reset-names = "eqos";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_EQOS>;
status = "disabled";
snps,write-requests = <1>;
snps,read-requests = <3>;
snps,burst-map = <0x7>;
snps,txpbl = <32>;
snps,rxpbl = <8>;
};
gpcdma: dma-controller@2600000 {
compatible = "nvidia,tegra186-gpcdma";
reg = <0x0 0x2600000 0x0 0x210000>;
resets = <&bpmp TEGRA186_RESET_GPCDMA>;
reset-names = "gpcdma";
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dma-channel-mask = <0xfffffffe>;
status = "okay";
};
aconnect@2900000 {
compatible = "nvidia,tegra186-aconnect",
"nvidia,tegra210-aconnect";
clocks = <&bpmp TEGRA186_CLK_APE>,
<&bpmp TEGRA186_CLK_APB2APE>;
clock-names = "ape", "apb2ape";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>;
status = "disabled";
tegra_ahub: ahub@2900800 {
compatible = "nvidia,tegra186-ahub";
reg = <0x0 0x02900800 0x0 0x800>;
clocks = <&bpmp TEGRA186_CLK_AHUB>;
clock-names = "ahub";
assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
assigned-clock-rates = <81600000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
status = "disabled";
tegra_i2s1: i2s@2901000 {
compatible = "nvidia,tegra186-i2s",
"nvidia,tegra210-i2s";
reg = <0x0 0x2901000 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_I2S1>,
<&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S1";
status = "disabled";
};
tegra_i2s2: i2s@2901100 {
compatible = "nvidia,tegra186-i2s",
"nvidia,tegra210-i2s";
reg = <0x0 0x2901100 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_I2S2>,
<&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S2";
status = "disabled";
};
tegra_i2s3: i2s@2901200 {
compatible = "nvidia,tegra186-i2s",
"nvidia,tegra210-i2s";
reg = <0x0 0x2901200 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_I2S3>,
<&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S3";
status = "disabled";
};
tegra_i2s4: i2s@2901300 {
compatible = "nvidia,tegra186-i2s",
"nvidia,tegra210-i2s";
reg = <0x0 0x2901300 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_I2S4>,
<&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S4";
status = "disabled";
};
tegra_i2s5: i2s@2901400 {
compatible = "nvidia,tegra186-i2s",
"nvidia,tegra210-i2s";
reg = <0x0 0x2901400 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_I2S5>,
<&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S5";
status = "disabled";
};
tegra_i2s6: i2s@2901500 {
compatible = "nvidia,tegra186-i2s",
"nvidia,tegra210-i2s";
reg = <0x0 0x2901500 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_I2S6>,
<&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S6";
status = "disabled";
};
tegra_sfc1: sfc@2902000 {
compatible = "nvidia,tegra186-sfc",
"nvidia,tegra210-sfc";
reg = <0x0 0x2902000 0x0 0x200>;
sound-name-prefix = "SFC1";
status = "disabled";
};
tegra_sfc2: sfc@2902200 {
compatible = "nvidia,tegra186-sfc",
"nvidia,tegra210-sfc";
reg = <0x0 0x2902200 0x0 0x200>;
sound-name-prefix = "SFC2";
status = "disabled";
};
tegra_sfc3: sfc@2902400 {
compatible = "nvidia,tegra186-sfc",
"nvidia,tegra210-sfc";
reg = <0x0 0x2902400 0x0 0x200>;
sound-name-prefix = "SFC3";
status = "disabled";
};
tegra_sfc4: sfc@2902600 {
compatible = "nvidia,tegra186-sfc",
"nvidia,tegra210-sfc";
reg = <0x0 0x2902600 0x0 0x200>;
sound-name-prefix = "SFC4";
status = "disabled";
};
tegra_amx1: amx@2903000 {
compatible = "nvidia,tegra186-amx",
"nvidia,tegra210-amx";
reg = <0x0 0x2903000 0x0 0x100>;
sound-name-prefix = "AMX1";
status = "disabled";
};
tegra_amx2: amx@2903100 {
compatible = "nvidia,tegra186-amx",
"nvidia,tegra210-amx";
reg = <0x0 0x2903100 0x0 0x100>;
sound-name-prefix = "AMX2";
status = "disabled";
};
tegra_amx3: amx@2903200 {
compatible = "nvidia,tegra186-amx",
"nvidia,tegra210-amx";
reg = <0x0 0x2903200 0x0 0x100>;
sound-name-prefix = "AMX3";
status = "disabled";
};
tegra_amx4: amx@2903300 {
compatible = "nvidia,tegra186-amx",
"nvidia,tegra210-amx";
reg = <0x0 0x2903300 0x0 0x100>;
sound-name-prefix = "AMX4";
status = "disabled";
};
tegra_adx1: adx@2903800 {
compatible = "nvidia,tegra186-adx",
"nvidia,tegra210-adx";
reg = <0x0 0x2903800 0x0 0x100>;
sound-name-prefix = "ADX1";
status = "disabled";
};
tegra_adx2: adx@2903900 {
compatible = "nvidia,tegra186-adx",
"nvidia,tegra210-adx";
reg = <0x0 0x2903900 0x0 0x100>;
sound-name-prefix = "ADX2";
status = "disabled";
};
tegra_adx3: adx@2903a00 {
compatible = "nvidia,tegra186-adx",
"nvidia,tegra210-adx";
reg = <0x0 0x2903a00 0x0 0x100>;
sound-name-prefix = "ADX3";
status = "disabled";
};
tegra_adx4: adx@2903b00 {
compatible = "nvidia,tegra186-adx",
"nvidia,tegra210-adx";
reg = <0x0 0x2903b00 0x0 0x100>;
sound-name-prefix = "ADX4";
status = "disabled";
};
tegra_dmic1: dmic@2904000 {
compatible = "nvidia,tegra210-dmic";
reg = <0x0 0x2904000 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_DMIC1>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
assigned-clock-rates = <3072000>;
sound-name-prefix = "DMIC1";
status = "disabled";
};
tegra_dmic2: dmic@2904100 {
compatible = "nvidia,tegra210-dmic";
reg = <0x0 0x2904100 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_DMIC2>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
assigned-clock-rates = <3072000>;
sound-name-prefix = "DMIC2";
status = "disabled";
};
tegra_dmic3: dmic@2904200 {
compatible = "nvidia,tegra210-dmic";
reg = <0x0 0x2904200 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_DMIC3>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
assigned-clock-rates = <3072000>;
sound-name-prefix = "DMIC3";
status = "disabled";
};
tegra_dmic4: dmic@2904300 {
compatible = "nvidia,tegra210-dmic";
reg = <0x0 0x2904300 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_DMIC4>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
assigned-clock-rates = <3072000>;
sound-name-prefix = "DMIC4";
status = "disabled";
};
tegra_dspk1: dspk@2905000 {
compatible = "nvidia,tegra186-dspk";
reg = <0x0 0x2905000 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_DSPK1>;
clock-names = "dspk";
assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
assigned-clock-rates = <12288000>;
sound-name-prefix = "DSPK1";
status = "disabled";
};
tegra_dspk2: dspk@2905100 {
compatible = "nvidia,tegra186-dspk";
reg = <0x0 0x2905100 0x0 0x100>;
clocks = <&bpmp TEGRA186_CLK_DSPK2>;
clock-names = "dspk";
assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
assigned-clock-rates = <12288000>;
sound-name-prefix = "DSPK2";
status = "disabled";
};
tegra_ope1: processing-engine@2908000 {
compatible = "nvidia,tegra186-ope",
"nvidia,tegra210-ope";
reg = <0x0 0x2908000 0x0 0x100>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
sound-name-prefix = "OPE1";
status = "disabled";
equalizer@2908100 {
compatible = "nvidia,tegra186-peq",
"nvidia,tegra210-peq";
reg = <0x0 0x2908100 0x0 0x100>;
};
dynamic-range-compressor@2908200 {
compatible = "nvidia,tegra186-mbdrc",
"nvidia,tegra210-mbdrc";
reg = <0x0 0x2908200 0x0 0x200>;
};
};
tegra_mvc1: mvc@290a000 {
compatible = "nvidia,tegra186-mvc",
"nvidia,tegra210-mvc";
reg = <0x0 0x290a000 0x0 0x200>;
sound-name-prefix = "MVC1";
status = "disabled";
};
tegra_mvc2: mvc@290a200 {
compatible = "nvidia,tegra186-mvc",
"nvidia,tegra210-mvc";
reg = <0x0 0x290a200 0x0 0x200>;
sound-name-prefix = "MVC2";
status = "disabled";
};
tegra_amixer: amixer@290bb00 {
compatible = "nvidia,tegra186-amixer",
"nvidia,tegra210-amixer";
reg = <0x0 0x290bb00 0x0 0x800>;
sound-name-prefix = "MIXER1";
status = "disabled";
};
tegra_admaif: admaif@290f000 {
compatible = "nvidia,tegra186-admaif";
reg = <0x0 0x0290f000 0x0 0x1000>;
dmas = <&adma 1>, <&adma 1>,
<&adma 2>, <&adma 2>,
<&adma 3>, <&adma 3>,
<&adma 4>, <&adma 4>,
<&adma 5>, <&adma 5>,
<&adma 6>, <&adma 6>,
<&adma 7>, <&adma 7>,
<&adma 8>, <&adma 8>,
<&adma 9>, <&adma 9>,
<&adma 10>, <&adma 10>,
<&adma 11>, <&adma 11>,
<&adma 12>, <&adma 12>,
<&adma 13>, <&adma 13>,
<&adma 14>, <&adma 14>,
<&adma 15>, <&adma 15>,
<&adma 16>, <&adma 16>,
<&adma 17>, <&adma 17>,
<&adma 18>, <&adma 18>,
<&adma 19>, <&adma 19>,
<&adma 20>, <&adma 20>;
dma-names = "rx1", "tx1",
"rx2", "tx2",
"rx3", "tx3",
"rx4", "tx4",
"rx5", "tx5",
"rx6", "tx6",
"rx7", "tx7",
"rx8", "tx8",
"rx9", "tx9",
"rx10", "tx10",
"rx11", "tx11",
"rx12", "tx12",
"rx13", "tx13",
"rx14", "tx14",
"rx15", "tx15",
"rx16", "tx16",
"rx17", "tx17",
"rx18", "tx18",
"rx19", "tx19",
"rx20", "tx20";
status = "disabled";
};
tegra_asrc: asrc@2910000 {
compatible = "nvidia,tegra186-asrc";
reg = <0x0 0x2910000 0x0 0x2000>;
sound-name-prefix = "ASRC1";
status = "disabled";
};
};
adma: dma-controller@2930000 {
compatible = "nvidia,tegra186-adma";
reg = <0x0 0x02930000 0x0 0x20000>;
interrupt-parent = <&agic>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&bpmp TEGRA186_CLK_AHUB>;
clock-names = "d_audio";
status = "disabled";
};
agic: interrupt-controller@2a40000 {
compatible = "nvidia,tegra186-agic",
"nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x02a41000 0x0 0x1000>,
<0x0 0x02a42000 0x0 0x2000>;
interrupts = <GIC_SPI 145
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&bpmp TEGRA186_CLK_APE>;
clock-names = "clk";
status = "disabled";
};
};
mc: memory-controller@2c00000 {
compatible = "nvidia,tegra186-mc";
reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
<0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
<0x0 0x02c20000 0x0 0x10000>, /* MC0 */
<0x0 0x02c30000 0x0 0x10000>, /* MC1 */
<0x0 0x02c40000 0x0 0x10000>, /* MC2 */
<0x0 0x02c50000 0x0 0x10000>; /* MC3 */
reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#interconnect-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
/*
* Memory clients have access to all 40 bits that the memory
* controller can address.
*/
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
emc: external-memory-controller@2c60000 {
compatible = "nvidia,tegra186-emc";
reg = <0x0 0x02c60000 0x0 0x50000>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_EMC>;
clock-names = "emc";
#interconnect-cells = <0>;
nvidia,bpmp = <&bpmp>;
};
};
timer@3010000 {
compatible = "nvidia,tegra186-timer";
reg = <0x0 0x03010000 0x0 0x000e0000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
uarta: serial@3100000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03100000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTA>;
resets = <&bpmp TEGRA186_RESET_UARTA>;
dmas = <&gpcdma 8>, <&gpcdma 8>;
dma-names = "rx", "tx";
status = "disabled";
};
uartb: serial@3110000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03110000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTB>;
resets = <&bpmp TEGRA186_RESET_UARTB>;
dmas = <&gpcdma 9>, <&gpcdma 9>;
dma-names = "rx", "tx";
status = "disabled";
};
uartd: serial@3130000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03130000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTD>;
resets = <&bpmp TEGRA186_RESET_UARTD>;
dmas = <&gpcdma 19>, <&gpcdma 19>;
dma-names = "rx", "tx";
status = "disabled";
};
uarte: serial@3140000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03140000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTE>;
resets = <&bpmp TEGRA186_RESET_UARTE>;
dmas = <&gpcdma 20>, <&gpcdma 20>;
dma-names = "rx", "tx";
status = "disabled";
};
uartf: serial@3150000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03150000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTF>;
resets = <&bpmp TEGRA186_RESET_UARTF>;
dmas = <&gpcdma 12>, <&gpcdma 12>;
dma-names = "rx", "tx";
status = "disabled";
};
gen1_i2c: i2c@3160000 {
compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x03160000 0x0 0x10000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C1>;
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C1>;
reset-names = "i2c";
dmas = <&gpcdma 21>, <&gpcdma 21>;
dma-names = "rx", "tx";
status = "disabled";
};
cam_i2c: i2c@3180000 {
compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x03180000 0x0 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C3>;
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C3>;
reset-names = "i2c";
dmas = <&gpcdma 23>, <&gpcdma 23>;
dma-names = "rx", "tx";
status = "disabled";
};
/* shares pads with dpaux1 */
dp_aux_ch1_i2c: i2c@3190000 {
compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x03190000 0x0 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C4>;
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C4>;
reset-names = "i2c";
pinctrl-names = "default", "idle";
pinctrl-0 = <&state_dpaux1_i2c>;
pinctrl-1 = <&state_dpaux1_off>;
dmas = <&gpcdma 26>, <&gpcdma 26>;
dma-names = "rx", "tx";
status = "disabled";
};
/* controlled by BPMP, should not be enabled */
pwr_i2c: i2c@31a0000 {
compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x031a0000 0x0 0x10000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C5>;
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C5>;
reset-names = "i2c";
status = "disabled";
};
/* shares pads with dpaux0 */
dp_aux_ch0_i2c: i2c@31b0000 {
compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x031b0000 0x0 0x10000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C6>;
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C6>;
reset-names = "i2c";
pinctrl-names = "default", "idle";
pinctrl-0 = <&state_dpaux_i2c>;
pinctrl-1 = <&state_dpaux_off>;
dmas = <&gpcdma 30>, <&gpcdma 30>;
dma-names = "rx", "tx";
status = "disabled";
};
gen7_i2c: i2c@31c0000 {
compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x031c0000 0x0 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C7>;
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C7>;
reset-names = "i2c";
dmas = <&gpcdma 27>, <&gpcdma 27>;
dma-names = "rx", "tx";
status = "disabled";
};
gen9_i2c: i2c@31e0000 {
compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x031e0000 0x0 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C9>;
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C9>;
reset-names = "i2c";
dmas = <&gpcdma 31>, <&gpcdma 31>;
dma-names = "rx", "tx";
status = "disabled";
};
pwm1: pwm@3280000 {
compatible = "nvidia,tegra186-pwm";
reg = <0x0 0x3280000 0x0 0x10000>;
clocks = <&bpmp TEGRA186_CLK_PWM1>;
resets = <&bpmp TEGRA186_RESET_PWM1>;
reset-names = "pwm";
status = "disabled";
#pwm-cells = <2>;
};
pwm2: pwm@3290000 {
compatible = "nvidia,tegra186-pwm";
reg = <0x0 0x3290000 0x0 0x10000>;
clocks = <&bpmp TEGRA186_CLK_PWM2>;
resets = <&bpmp TEGRA186_RESET_PWM2>;
reset-names = "pwm";
status = "disabled";
#pwm-cells = <2>;
};
pwm3: pwm@32a0000 {
compatible = "nvidia,tegra186-pwm";
reg = <0x0 0x32a0000 0x0 0x10000>;
clocks = <&bpmp TEGRA186_CLK_PWM3>;
resets = <&bpmp TEGRA186_RESET_PWM3>;
reset-names = "pwm";
status = "disabled";
#pwm-cells = <2>;
};
pwm5: pwm@32c0000 {
compatible = "nvidia,tegra186-pwm";
reg = <0x0 0x32c0000 0x0 0x10000>;
clocks = <&bpmp TEGRA186_CLK_PWM5>;
resets = <&bpmp TEGRA186_RESET_PWM5>;
reset-names = "pwm";
status = "disabled";
#pwm-cells = <2>;
};
pwm6: pwm@32d0000 {
compatible = "nvidia,tegra186-pwm";
reg = <0x0 0x32d0000 0x0 0x10000>;
clocks = <&bpmp TEGRA186_CLK_PWM6>;
resets = <&bpmp TEGRA186_RESET_PWM6>;
reset-names = "pwm";
status = "disabled";
#pwm-cells = <2>;
};
pwm7: pwm@32e0000 {
compatible = "nvidia,tegra186-pwm";
reg = <0x0 0x32e0000 0x0 0x10000>;
clocks = <&bpmp TEGRA186_CLK_PWM7>;
resets = <&bpmp TEGRA186_RESET_PWM7>;
reset-names = "pwm";
status = "disabled";
#pwm-cells = <2>;
};
pwm8: pwm@32f0000 {
compatible = "nvidia,tegra186-pwm";
reg = <0x0 0x32f0000 0x0 0x10000>;
clocks = <&bpmp TEGRA186_CLK_PWM8>;
resets = <&bpmp TEGRA186_RESET_PWM8>;
reset-names = "pwm";
status = "disabled";
#pwm-cells = <2>;
};
sdmmc1: mmc@3400000 {
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03400000 0x0 0x10000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
<&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
clock-names = "sdhci", "tmclk";
resets = <&bpmp TEGRA186_RESET_SDMMC1>;
reset-names = "sdhci";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
<&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_SDMMC1>;
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc1_3v3>;
pinctrl-1 = <&sdmmc1_1v8>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
nvidia,default-tap = <0x5>;
nvidia,default-trim = <0xb>;
assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
<&bpmp TEGRA186_CLK_PLLP_OUT0>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
status = "disabled";
};
sdmmc2: mmc@3420000 {
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03420000 0x0 0x10000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
<&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
clock-names = "sdhci", "tmclk";
resets = <&bpmp TEGRA186_RESET_SDMMC2>;
reset-names = "sdhci";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
<&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_SDMMC2>;
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc2_3v3>;
pinctrl-1 = <&sdmmc2_1v8>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
nvidia,default-tap = <0x5>;
nvidia,default-trim = <0xb>;
status = "disabled";
};
sdmmc3: mmc@3440000 {
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03440000 0x0 0x10000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
<&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
clock-names = "sdhci", "tmclk";
resets = <&bpmp TEGRA186_RESET_SDMMC3>;
reset-names = "sdhci";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_SDMMC3>;
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc3_3v3>;
pinctrl-1 = <&sdmmc3_1v8>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
nvidia,default-tap = <0x5>;
nvidia,default-trim = <0xb>;
status = "disabled";
};
sdmmc4: mmc@3460000 {
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03460000 0x0 0x10000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
<&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
clock-names = "sdhci", "tmclk";
assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
<&bpmp TEGRA186_CLK_PLLC4_VCO>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
resets = <&bpmp TEGRA186_RESET_SDMMC4>;
reset-names = "sdhci";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>,
<&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_SDMMC4>;
nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
nvidia,default-tap = <0x9>;
nvidia,default-trim = <0x5>;
nvidia,dqs-trim = <63>;
mmc-hs400-1_8v;
supports-cqe;
status = "disabled";
};
sata@3507000 {
compatible = "nvidia,tegra186-ahci";
reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */
<0x0 0x03500000 0x0 0x00007000>, /* SATA */
<0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_SATA>;
clocks = <&bpmp TEGRA186_CLK_SATA>,
<&bpmp TEGRA186_CLK_SATA_OOB>;
clock-names = "sata", "sata-oob";
assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,
<&bpmp TEGRA186_CLK_SATA_OOB>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,
<&bpmp TEGRA186_CLK_PLLP>;
assigned-clock-rates = <102000000>,
<204000000>;
resets = <&bpmp TEGRA186_RESET_SATA>,
<&bpmp TEGRA186_RESET_SATACOLD>;
reset-names = "sata", "sata-cold";
status = "disabled";
};
hda@3510000 {
compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
reg = <0x0 0x03510000 0x0 0x10000>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_HDA>,
<&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
<&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
clock-names = "hda", "hda2hdmi", "hda2codec_2x";
resets = <&bpmp TEGRA186_RESET_HDA>,
<&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
<&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
reset-names = "hda", "hda2hdmi", "hda2codec_2x";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_HDA>;
status = "disabled";
};
padctl: padctl@3520000 {
compatible = "nvidia,tegra186-xusb-padctl";
reg = <0x0 0x03520000 0x0 0x1000>,
<0x0 0x03540000 0x0 0x1000>;
reg-names = "padctl", "ao";
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
reset-names = "padctl";
status = "disabled";
pads {
usb2 {
clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
clock-names = "trk";
status = "disabled";
lanes {
usb2-0 {
status = "disabled";
#phy-cells = <0>;
};
usb2-1 {
status = "disabled";
#phy-cells = <0>;
};
usb2-2 {
status = "disabled";
#phy-cells = <0>;
};
};
};
hsic {
clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
clock-names = "trk";
status = "disabled";
lanes {
hsic-0 {
status = "disabled";
#phy-cells = <0>;
};
};
};
usb3 {
status = "disabled";
lanes {
usb3-0 {
status = "disabled";
#phy-cells = <0>;
};
usb3-1 {
status = "disabled";
#phy-cells = <0>;
};
usb3-2 {
status = "disabled";
#phy-cells = <0>;
};
};
};
};
ports {
usb2-0 {
status = "disabled";
};
usb2-1 {
status = "disabled";
};
usb2-2 {
status = "disabled";
};
hsic-0 {
status = "disabled";
};
usb3-0 {
status = "disabled";
};
usb3-1 {
status = "disabled";
};
usb3-2 {
status = "disabled";
};
};
};
usb@3530000 {
compatible = "nvidia,tegra186-xusb";
reg = <0x0 0x03530000 0x0 0x8000>,
<0x0 0x03538000 0x0 0x1000>;
reg-names = "hcd", "fpci";
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
<&bpmp TEGRA186_CLK_XUSB_FALCON>,
<&bpmp TEGRA186_CLK_XUSB_SS>,
<&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
<&bpmp TEGRA186_CLK_CLK_M>,
<&bpmp TEGRA186_CLK_XUSB_FS>,
<&bpmp TEGRA186_CLK_PLLU>,
<&bpmp TEGRA186_CLK_CLK_M>,
<&bpmp TEGRA186_CLK_PLLE>;
clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
"xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
"pll_u_480m", "clk_m", "pll_e";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
power-domain-names = "xusb_host", "xusb_ss";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
nvidia,xusb-padctl = <&padctl>;
};
usb@3550000 {
compatible = "nvidia,tegra186-xudc";
reg = <0x0 0x03550000 0x0 0x8000>,
<0x0 0x03558000 0x0 0x1000>;
reg-names = "base", "fpci";
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
<&bpmp TEGRA186_CLK_XUSB_SS>,
<&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
<&bpmp TEGRA186_CLK_XUSB_FS>;
clock-names = "dev", "ss", "ss_src", "fs_src";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_XUSB_DEV>;
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
power-domain-names = "dev", "ss";
nvidia,xusb-padctl = <&padctl>;
status = "disabled";
};
fuse@3820000 {
compatible = "nvidia,tegra186-efuse";
reg = <0x0 0x03820000 0x0 0x10000>;
clocks = <&bpmp TEGRA186_CLK_FUSE>;
clock-names = "fuse";
};
gic: interrupt-controller@3881000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x03881000 0x0 0x1000>,
<0x0 0x03882000 0x0 0x2000>,
<0x0 0x03884000 0x0 0x2000>,
<0x0 0x03886000 0x0 0x2000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-parent = <&gic>;
};
cec@3960000 {
compatible = "nvidia,tegra186-cec", "nvidia,tegra210-cec";
reg = <0x0 0x03960000 0x0 0x10000>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_CEC>;
clock-names = "cec";
status = "disabled";
};
hsp_top0: hsp@3c00000 {
compatible = "nvidia,tegra186-hsp";
reg = <0x0 0x03c00000 0x0 0xa0000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "doorbell";
#mbox-cells = <2>;
status = "disabled";
};
gen2_i2c: i2c@c240000 {
compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x0c240000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C2>;
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C2>;
reset-names = "i2c";
dmas = <&gpcdma 22>, <&gpcdma 22>;
dma-names = "rx", "tx";
status = "disabled";
};
gen8_i2c: i2c@c250000 {
compatible = "nvidia,tegra186-i2c";
reg = <0x0 0x0c250000 0x0 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C8>;
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C8>;
reset-names = "i2c";
dmas = <&gpcdma 0>, <&gpcdma 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uartc: serial@c280000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x0c280000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTC>;
resets = <&bpmp TEGRA186_RESET_UARTC>;
dmas = <&gpcdma 3>, <&gpcdma 3>;
dma-names = "rx", "tx";
status = "disabled";
};
uartg: serial@c290000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x0c290000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_UARTG>;
resets = <&bpmp TEGRA186_RESET_UARTG>;
dmas = <&gpcdma 2>, <&gpcdma 2>;
dma-names = "rx", "tx";
status = "disabled";
};
rtc: rtc@c2a0000 {
compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
reg = <0 0x0c2a0000 0 0x10000>;
interrupt-parent = <&pmc>;
interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
clock-names = "rtc";
status = "disabled";
};
gpio_aon: gpio@c2f0000 {
compatible = "nvidia,tegra186-gpio-aon";
reg-names = "security", "gpio";
reg = <0x0 0xc2f0000 0x0 0x1000>,
<0x0 0xc2f1000 0x0 0x1000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pwm4: pwm@c340000 {
compatible = "nvidia,tegra186-pwm";
reg = <0x0 0xc340000 0x0 0x10000>;
clocks = <&bpmp TEGRA186_CLK_PWM4>;
resets = <&bpmp TEGRA186_RESET_PWM4>;
reset-names = "pwm";
status = "disabled";
#pwm-cells = <2>;
};
pmc: pmc@c360000 {
compatible = "nvidia,tegra186-pmc";
reg = <0 0x0c360000 0 0x10000>,
<0 0x0c370000 0 0x10000>,
<0 0x0c380000 0 0x10000>,
<0 0x0c390000 0 0x10000>;
reg-names = "pmc", "wake", "aotag", "scratch";
#interrupt-cells = <2>;
interrupt-controller;
sdmmc1_1v8: sdmmc1-1v8 {
pins = "sdmmc1-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
};
sdmmc1_3v3: sdmmc1-3v3 {
pins = "sdmmc1-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
};
sdmmc2_1v8: sdmmc2-1v8 {
pins = "sdmmc2-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
};
sdmmc2_3v3: sdmmc2-3v3 {
pins = "sdmmc2-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
};
sdmmc3_1v8: sdmmc3-1v8 {
pins = "sdmmc3-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
};
sdmmc3_3v3: sdmmc3-3v3 {
pins = "sdmmc3-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
};
};
ccplex@e000000 {
compatible = "nvidia,tegra186-ccplex-cluster";
reg = <0x0 0x0e000000 0x0 0x400000>;
nvidia,bpmp = <&bpmp>;
};
pcie@10003000 {
compatible = "nvidia,tegra186-pcie";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
device_type = "pci";
reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */
<0x0 0x10003800 0x0 0x00000800>, /* AFI registers */
<0x0 0x40000000 0x0 0x10000000>; /* configuration space */
reg-names = "pads", "afi", "cs";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */
<0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
<0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */
<0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
<0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
<0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
clocks = <&bpmp TEGRA186_CLK_PCIE>,
<&bpmp TEGRA186_CLK_AFI>,
<&bpmp TEGRA186_CLK_PLLE>;
clock-names = "pex", "afi", "pll_e";
resets = <&bpmp TEGRA186_RESET_PCIE>,
<&bpmp TEGRA186_RESET_AFI>,
<&bpmp TEGRA186_RESET_PCIEXCLK>;
reset-names = "pex", "afi", "pcie_x";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_AFI>;
iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
iommu-map-mask = <0x0>;
status = "disabled";
pci@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
reg = <0x000800 0 0 0 0>;
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
ranges;
nvidia,num-lanes = <2>;
};
pci@2,0 {
device_type = "pci";
assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
reg = <0x001000 0 0 0 0>;
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
ranges;
nvidia,num-lanes = <1>;
};
pci@3,0 {
device_type = "pci";
assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
reg = <0x001800 0 0 0 0>;
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
ranges;
nvidia,num-lanes = <1>;
};
};
smmu: iommu@12000000 {
compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";
reg = <0 0x12000000 0 0x800000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
stream-match-mask = <0x7f80>;
#global-interrupts = <1>;
#iommu-cells = <1>;
nvidia,memory-controller = <&mc>;
};
host1x@13e00000 {
compatible = "nvidia,tegra186-host1x";
reg = <0x0 0x13e00000 0x0 0x10000>,
<0x0 0x13e10000 0x0 0x10000>;
reg-names = "hypervisor", "vm";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "syncpt", "host1x";
clocks = <&bpmp TEGRA186_CLK_HOST1X>;
clock-names = "host1x";
resets = <&bpmp TEGRA186_RESET_HOST1X>;
reset-names = "host1x";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x15000000 0x0 0x15000000 0x0 0x01000000>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>;
interconnect-names = "dma-mem";
iommus = <&smmu TEGRA186_SID_HOST1X>;
/* Context isolation domains */
iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>,
<1 &smmu TEGRA186_SID_HOST1X_CTX1 1>,
<2 &smmu TEGRA186_SID_HOST1X_CTX2 1>,
<3 &smmu TEGRA186_SID_HOST1X_CTX3 1>,
<4 &smmu TEGRA186_SID_HOST1X_CTX4 1>,
<5 &smmu TEGRA186_SID_HOST1X_CTX5 1>,
<6 &smmu TEGRA186_SID_HOST1X_CTX6 1>,
<7 &smmu TEGRA186_SID_HOST1X_CTX7 1>;
dpaux1: dpaux@15040000 {
compatible = "nvidia,tegra186-dpaux";
reg = <0x0 0x15040000 0x0 0x10000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
<&bpmp TEGRA186_CLK_PLLDP>;
clock-names = "dpaux", "parent";
resets = <&bpmp TEGRA186_RESET_DPAUX1>;
reset-names = "dpaux";
status = "disabled";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
state_dpaux1_aux: pinmux-aux {
groups = "dpaux-io";
function = "aux";
};
state_dpaux1_i2c: pinmux-i2c {
groups = "dpaux-io";
function = "i2c";
};
state_dpaux1_off: pinmux-off {
groups = "dpaux-io";
function = "off";
};
i2c-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
display-hub@15200000 {
compatible = "nvidia,tegra186-display";
reg = <0x0 0x15200000 0x0 0x00040000>;
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
"wgrp3", "wgrp4", "wgrp5";
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
<&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
<&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
clock-names = "disp", "dsc", "hub";
status = "disabled";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>;
display@15200000 {
compatible = "nvidia,tegra186-dc";
reg = <0x0 0x15200000 0x0 0x10000>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
clock-names = "dc";
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
reset-names = "dc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
nvidia,head = <0>;
};
display@15210000 {
compatible = "nvidia,tegra186-dc";
reg = <0x0 0x15210000 0x0 0x10000>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
clock-names = "dc";
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
reset-names = "dc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
nvidia,head = <1>;
};
display@15220000 {
compatible = "nvidia,tegra186-dc";
reg = <0x0 0x15220000 0x0 0x10000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
clock-names = "dc";
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
reset-names = "dc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
nvidia,outputs = <&sor0 &sor1>;
nvidia,head = <2>;
};
};
dsia: dsi@15300000 {
compatible = "nvidia,tegra186-dsi";
reg = <0x0 0x15300000 0x0 0x10000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_DSI>,
<&bpmp TEGRA186_CLK_DSIA_LP>,
<&bpmp TEGRA186_CLK_PLLD>;
clock-names = "dsi", "lp", "parent";
resets = <&bpmp TEGRA186_RESET_DSI>;
reset-names = "dsi";
status = "disabled";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
};
vic@15340000 {
compatible = "nvidia,tegra186-vic";
reg = <0x0 0x15340000 0x0 0x40000>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_VIC>;
clock-names = "vic";
resets = <&bpmp TEGRA186_RESET_VIC>;
reset-names = "vic";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>,
<&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_VIC>;
};
nvjpg@15380000 {
compatible = "nvidia,tegra186-nvjpg";
reg = <0x0 0x15380000 0x0 0x40000>;
clocks = <&bpmp TEGRA186_CLK_NVJPG>;
clock-names = "nvjpg";
resets = <&bpmp TEGRA186_RESET_NVJPG>;
reset-names = "nvjpg";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_NVJPG>;
};
dsib: dsi@15400000 {
compatible = "nvidia,tegra186-dsi";
reg = <0x0 0x15400000 0x0 0x10000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_DSIB>,
<&bpmp TEGRA186_CLK_DSIB_LP>,
<&bpmp TEGRA186_CLK_PLLD>;
clock-names = "dsi", "lp", "parent";
resets = <&bpmp TEGRA186_RESET_DSIB>;
reset-names = "dsi";
status = "disabled";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
};
nvdec@15480000 {
compatible = "nvidia,tegra186-nvdec";
reg = <0x0 0x15480000 0x0 0x40000>;
clocks = <&bpmp TEGRA186_CLK_NVDEC>;
clock-names = "nvdec";
resets = <&bpmp TEGRA186_RESET_NVDEC>;
reset-names = "nvdec";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
interconnect-names = "dma-mem", "read-1", "write";
iommus = <&smmu TEGRA186_SID_NVDEC>;
};
nvenc@154c0000 {
compatible = "nvidia,tegra186-nvenc";
reg = <0x0 0x154c0000 0x0 0x40000>;
clocks = <&bpmp TEGRA186_CLK_NVENC>;
clock-names = "nvenc";
resets = <&bpmp TEGRA186_RESET_NVENC>;
reset-names = "nvenc";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
<&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_NVENC>;
};
sor0: sor@15540000 {
compatible = "nvidia,tegra186-sor";
reg = <0x0 0x15540000 0x0 0x10000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_SOR0>,
<&bpmp TEGRA186_CLK_SOR0_OUT>,
<&bpmp TEGRA186_CLK_PLLD2>,
<&bpmp TEGRA186_CLK_PLLDP>,
<&bpmp TEGRA186_CLK_SOR_SAFE>,
<&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
clock-names = "sor", "out", "parent", "dp", "safe",
"pad";
resets = <&bpmp TEGRA186_RESET_SOR0>;
reset-names = "sor";
pinctrl-0 = <&state_dpaux_aux>;
pinctrl-1 = <&state_dpaux_i2c>;
pinctrl-2 = <&state_dpaux_off>;
pinctrl-names = "aux", "i2c", "off";
status = "disabled";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
nvidia,interface = <0>;
};
sor1: sor@15580000 {
compatible = "nvidia,tegra186-sor";
reg = <0x0 0x15580000 0x0 0x10000>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_SOR1>,
<&bpmp TEGRA186_CLK_SOR1_OUT>,
<&bpmp TEGRA186_CLK_PLLD3>,
<&bpmp TEGRA186_CLK_PLLDP>,
<&bpmp TEGRA186_CLK_SOR_SAFE>,
<&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
clock-names = "sor", "out", "parent", "dp", "safe",
"pad";
resets = <&bpmp TEGRA186_RESET_SOR1>;
reset-names = "sor";
pinctrl-0 = <&state_dpaux1_aux>;
pinctrl-1 = <&state_dpaux1_i2c>;
pinctrl-2 = <&state_dpaux1_off>;
pinctrl-names = "aux", "i2c", "off";
status = "disabled";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
nvidia,interface = <1>;
};
dpaux: dpaux@155c0000 {
compatible = "nvidia,tegra186-dpaux";
reg = <0x0 0x155c0000 0x0 0x10000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_DPAUX>,
<&bpmp TEGRA186_CLK_PLLDP>;
clock-names = "dpaux", "parent";
resets = <&bpmp TEGRA186_RESET_DPAUX>;
reset-names = "dpaux";
status = "disabled";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
state_dpaux_aux: pinmux-aux {
groups = "dpaux-io";
function = "aux";
};
state_dpaux_i2c: pinmux-i2c {
groups = "dpaux-io";
function = "i2c";
};
state_dpaux_off: pinmux-off {
groups = "dpaux-io";
function = "off";
};
i2c-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
padctl@15880000 {
compatible = "nvidia,tegra186-dsi-padctl";
reg = <0x0 0x15880000 0x0 0x10000>;
resets = <&bpmp TEGRA186_RESET_DSI>;
reset-names = "dsi";
status = "disabled";
};
dsic: dsi@15900000 {
compatible = "nvidia,tegra186-dsi";
reg = <0x0 0x15900000 0x0 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_DSIC>,
<&bpmp TEGRA186_CLK_DSIC_LP>,
<&bpmp TEGRA186_CLK_PLLD>;
clock-names = "dsi", "lp", "parent";
resets = <&bpmp TEGRA186_RESET_DSIC>;
reset-names = "dsi";
status = "disabled";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
};
dsid: dsi@15940000 {
compatible = "nvidia,tegra186-dsi";
reg = <0x0 0x15940000 0x0 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_DSID>,
<&bpmp TEGRA186_CLK_DSID_LP>,
<&bpmp TEGRA186_CLK_PLLD>;
clock-names = "dsi", "lp", "parent";
resets = <&bpmp TEGRA186_RESET_DSID>;
reset-names = "dsi";
status = "disabled";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
};
};
gpu@17000000 {
compatible = "nvidia,gp10b";
reg = <0x0 0x17000000 0x0 0x1000000>,
<0x0 0x18000000 0x0 0x1000000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall", "nonstall";
clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
<&bpmp TEGRA186_CLK_GPU>;
clock-names = "gpu", "pwr";
resets = <&bpmp TEGRA186_RESET_GPU>;
reset-names = "gpu";
status = "disabled";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>,
<&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>,
<&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>;
interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
};
sram@30000000 {
compatible = "nvidia,tegra186-sysram", "mmio-sram";
reg = <0x0 0x30000000 0x0 0x50000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x30000000 0x50000>;
no-memory-wc;
cpu_bpmp_tx: sram@4e000 {
reg = <0x4e000 0x1000>;
label = "cpu-bpmp-tx";
pool;
};
cpu_bpmp_rx: sram@4f000 {
reg = <0x4f000 0x1000>;
label = "cpu-bpmp-rx";
pool;
};
};
bpmp: bpmp {
compatible = "nvidia,tegra186-bpmp";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
interconnect-names = "read", "write", "dma-mem", "dma-write";
iommus = <&smmu TEGRA186_SID_BPMP>;
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
TEGRA_HSP_DB_MASTER_BPMP>;
shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
bpmp_i2c: i2c {
compatible = "nvidia,tegra186-bpmp-i2c";
nvidia,bpmp-bus-id = <5>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
bpmp_thermal: thermal {
compatible = "nvidia,tegra186-bpmp-thermal";
#thermal-sensor-cells = <1>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
denver_0: cpu@0 {
compatible = "nvidia,tegra186-denver";
device_type = "cpu";
i-cache-size = <0x20000>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_DENVER>;
reg = <0x000>;
};
denver_1: cpu@1 {
compatible = "nvidia,tegra186-denver";
device_type = "cpu";
i-cache-size = <0x20000>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
d-cache-size = <0x10000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_DENVER>;
reg = <0x001>;
};
ca57_0: cpu@2 {
compatible = "arm,cortex-a57";
device_type = "cpu";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_A57>;
reg = <0x100>;
};
ca57_1: cpu@3 {
compatible = "arm,cortex-a57";
device_type = "cpu";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_A57>;
reg = <0x101>;
};
ca57_2: cpu@4 {
compatible = "arm,cortex-a57";
device_type = "cpu";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_A57>;
reg = <0x102>;
};
ca57_3: cpu@5 {
compatible = "arm,cortex-a57";
device_type = "cpu";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&L2_A57>;
reg = <0x103>;
};
L2_DENVER: l2-cache0 {
compatible = "cache";
cache-unified;
cache-level = <2>;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
};
L2_A57: l2-cache1 {
compatible = "cache";
cache-unified;
cache-level = <2>;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
};
};
pmu-a57 {
compatible = "arm,cortex-a57-pmu";
interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;
};
pmu-denver {
compatible = "nvidia,denver-pmu";
interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&denver_0 &denver_1>;
};
sound {
status = "disabled";
clocks = <&bpmp TEGRA186_CLK_PLLA>,
<&bpmp TEGRA186_CLK_PLL_A_OUT0>;
clock-names = "pll_a", "plla_out0";
assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>,
<&bpmp TEGRA186_CLK_PLL_A_OUT0>,
<&bpmp TEGRA186_CLK_AUD_MCLK>;
assigned-clock-parents = <0>,
<&bpmp TEGRA186_CLK_PLLA>,
<&bpmp TEGRA186_CLK_PLL_A_OUT0>;
/*
* PLLA supports dynamic ramp. Below initial rate is chosen
* for this to work and oscillate between base rates required
* for 8x and 11.025x sample rate streams.
*/
assigned-clock-rates = <258000000>;
iommus = <&smmu TEGRA186_SID_APE>;
};
thermal-zones {
/* Cortex-A57 cluster */
cpu-thermal {
polling-delay = <0>;
polling-delay-passive = <1000>;
thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
trips {
critical {
temperature = <101000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
};
};
/* Denver cluster */
aux-thermal {
polling-delay = <0>;
polling-delay-passive = <1000>;
thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
trips {
critical {
temperature = <101000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
};
};
gpu-thermal {
polling-delay = <0>;
polling-delay-passive = <1000>;
thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
trips {
critical {
temperature = <101000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
};
};
pll-thermal {
polling-delay = <0>;
polling-delay-passive = <1000>;
thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
trips {
critical {
temperature = <101000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
};
};
ao-thermal {
polling-delay = <0>;
polling-delay-passive = <1000>;
thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
trips {
critical {
temperature = <101000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&gic>;
always-on;
};
};
[ Dauer der Verarbeitung: 0.52 Sekunden
(vorverarbeitet)
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2026-04-07
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