Quelle xgene_pmu.c Sprache: unbekannt
// SPDX-License-Identifier: GPL-2.0-or-later /* * APM X - Gene SoC PMU ( Performance Monitor Unit ) * * Copyright ( c ) 2016 , Applied Micro Circuits Corporation * Author : Hoan Tran < hotran @ apm . com > * Tai Nguyen < ttnguyen @ apm . com > #include <linux/acpi.h>#include <linux/clk.h>#include <linux/cpuhotplug.h>#include <linux/cpumask.h>#include <linux/interrupt.h>#include <linux/io.h>#include <linux/mfd/syscon.h>#include <linux/module.h>#include <linux/of_address.h>#include <linux/perf_event.h>#include <linux/platform_device.h>#include <linux/property.h>#include <linux/regmap.h>#include <linux/slab.h>#define CSW_CSWCR 0 x0000#define CSW_CSWCR_DUALMCB_MASK BIT(0 )#define CSW_CSWCR_MCB0_ROUTING(x) (((x) & 0 x0C) >> 2 )#define CSW_CSWCR_MCB1_ROUTING(x) (((x) & 0 x30) >> 4 )#define MCBADDRMR 0 x0000#define MCBADDRMR_DUALMCU_MODE_MASK BIT(2 )#define PCPPMU_INTSTATUS_REG 0 x000#define PCPPMU_INTMASK_REG 0 x004#define PCPPMU_INTMASK 0 x0000000F#define PCPPMU_INTENMASK 0 xFFFFFFFF#define PCPPMU_INTCLRMASK 0 xFFFFFFF0#define PCPPMU_INT_MCU BIT(0 )#define PCPPMU_INT_MCB BIT(1 )#define PCPPMU_INT_L3C BIT(2 )#define PCPPMU_INT_IOB BIT(3 )#define PCPPMU_V3_INTMASK 0 x00FF33FF#define PCPPMU_V3_INTENMASK 0 xFFFFFFFF#define PCPPMU_V3_INTCLRMASK 0 xFF00CC00#define PCPPMU_V3_INT_MCU 0 x000000FF#define PCPPMU_V3_INT_MCB 0 x00000300#define PCPPMU_V3_INT_L3C 0 x00FF0000#define PCPPMU_V3_INT_IOB 0 x00003000#define PMU_MAX_COUNTERS 4 #define PMU_CNT_MAX_PERIOD 0 xFFFFFFFFULL#define PMU_V3_CNT_MAX_PERIOD 0 xFFFFFFFFFFFFFFFFULL#define PMU_OVERFLOW_MASK 0 xF#define PMU_PMCR_E BIT(0 )#define PMU_PMCR_P BIT(1 )#define PMU_PMEVCNTR0 0 x000#define PMU_PMEVCNTR1 0 x004#define PMU_PMEVCNTR2 0 x008#define PMU_PMEVCNTR3 0 x00C#define PMU_PMEVTYPER0 0 x400#define PMU_PMEVTYPER1 0 x404#define PMU_PMEVTYPER2 0 x408#define PMU_PMEVTYPER3 0 x40C#define PMU_PMAMR0 0 xA00#define PMU_PMAMR1 0 xA04#define PMU_PMCNTENSET 0 xC00#define PMU_PMCNTENCLR 0 xC20#define PMU_PMINTENSET 0 xC40#define PMU_PMINTENCLR 0 xC60#define PMU_PMOVSR 0 xC80#define PMU_PMCR 0 xE04/* PMU registers for V3 */ #define PMU_PMOVSCLR 0 xC80#define PMU_PMOVSSET 0 xCC0#define to_pmu_dev(p) container_of(p, struct xgene_pmu_dev, pmu)#define GET_CNTR(ev) (ev->hw.idx)#define GET_EVENTID(ev) (ev->hw.config & 0 xFFULL)#define GET_AGENTID(ev) (ev->hw.config_base & 0 xFFFFFFFFUL)#define GET_AGENT1ID(ev) ((ev->hw.config_base >> 32 ) & 0 xFFFFFFFFUL)struct hw_pmu_info {void __iomem *csr;struct xgene_pmu_dev {struct hw_pmu_info *inf;struct xgene_pmu *parent;struct pmu pmu;const struct attribute_group **attr_groups;struct perf_event *pmu_counter_event[PMU_MAX_COUNTERS];struct xgene_pmu_ops {void (*mask_int)(struct xgene_pmu *pmu);void (*unmask_int)(struct xgene_pmu *pmu);struct xgene_pmu_dev *pmu, int idx);void (*write_counter)(struct xgene_pmu_dev *pmu, int idx, u64 val);void (*write_evttype)(struct xgene_pmu_dev *pmu_dev, int idx, u32 val);void (*write_agentmsk)(struct xgene_pmu_dev *pmu_dev, u32 val);void (*write_agent1msk)(struct xgene_pmu_dev *pmu_dev, u32 val);void (*enable_counter)(struct xgene_pmu_dev *pmu_dev, int idx);void (*disable_counter)(struct xgene_pmu_dev *pmu_dev, int idx);void (*enable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx);void (*disable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx);void (*reset_counters)(struct xgene_pmu_dev *pmu_dev);void (*start_counters)(struct xgene_pmu_dev *pmu_dev);void (*stop_counters)(struct xgene_pmu_dev *pmu_dev);struct xgene_pmu {struct device *dev;struct hlist_node node;int version;void __iomem *pcppmu_csr;int irq;const struct xgene_pmu_ops *ops;struct list_head l3cpmus;struct list_head iobpmus;struct list_head mcbpmus;struct list_head mcpmus;struct xgene_pmu_dev_ctx {char *name;struct list_head next;struct xgene_pmu_dev *pmu_dev;struct hw_pmu_info inf;struct xgene_pmu_data {int id;enum xgene_pmu_version {1 ,enum xgene_pmu_dev_type {0 ,/* * sysfs format attributes #define XGENE_PMU_FORMAT_ATTR(_name, _config) \struct dev_ext_attribute[]) { \void *) _config, } \0 ].attr.attr)static struct attribute *l3c_pmu_format_attrs[] = {"config:0-7" ),"config1:0-9" ),static struct attribute *iob_pmu_format_attrs[] = {"config:0-7" ),"config1:0-63" ),static struct attribute *mcb_pmu_format_attrs[] = {"config:0-5" ),"config1:0-9" ),static struct attribute *mc_pmu_format_attrs[] = {"config:0-28" ),static const struct attribute_group l3c_pmu_format_attr_group = {"format" ,static const struct attribute_group iob_pmu_format_attr_group = {"format" ,static const struct attribute_group mcb_pmu_format_attr_group = {"format" ,static const struct attribute_group mc_pmu_format_attr_group = {"format" ,static struct attribute *l3c_pmu_v3_format_attrs[] = {"config:0-39" ),static struct attribute *iob_pmu_v3_format_attrs[] = {"config:0-47" ),static struct attribute *iob_slow_pmu_v3_format_attrs[] = {"config:0-16" ),static struct attribute *mcb_pmu_v3_format_attrs[] = {"config:0-35" ),static struct attribute *mc_pmu_v3_format_attrs[] = {"config:0-44" ),static const struct attribute_group l3c_pmu_v3_format_attr_group = {"format" ,static const struct attribute_group iob_pmu_v3_format_attr_group = {"format" ,static const struct attribute_group iob_slow_pmu_v3_format_attr_group = {"format" ,static const struct attribute_group mcb_pmu_v3_format_attr_group = {"format" ,static const struct attribute_group mc_pmu_v3_format_attr_group = {"format" ,/* * sysfs event attributes static ssize_t xgene_pmu_event_show(struct device *dev,struct device_attribute *attr, char *buf)struct perf_pmu_events_attr *pmu_attr =struct perf_pmu_events_attr, attr);return sysfs_emit(buf, "config=0x%llx\n" , pmu_attr->id);#define XGENE_PMU_EVENT_ATTR(_name, _config) \static struct attribute *l3c_pmu_events_attrs[] = {0 x00),64 , 0 x01),0 x02),0 x03),0 x06),not -need-replacement, 0 x07),0 x08),0 x09),0 x0a),0 x0b),0 x0c),0 x0d),0 x0e),0 x0f),static struct attribute *iob_pmu_events_attrs[] = {0 x00),64 , 0 x01),0 x02),0 x03),0 x04),0 x05),0 x06),0 x07),0 x10),0 x11),0 x13),0 x14),0 x16),static struct attribute *mcb_pmu_events_attrs[] = {0 x00),64 , 0 x01),0 x02),0 x03),0 x04),0 x05),static struct attribute *mc_pmu_events_attrs[] = {0 x00),64 , 0 x01),0 x02),0 x03),0 x04),0 x05),0 x06),0 x07),0 x08),0 x09),0 x0a),0 x0b),0 x0c),0 x0d),0 x0e),0 x0f),not -empty, 0 x10),0 x11),0 x12),0 x13),0 x14),0 x15),0 x16),0 x17),0 x18),0 x19),0 x1a),0 x1b),0 x1c),static const struct attribute_group l3c_pmu_events_attr_group = {"events" ,static const struct attribute_group iob_pmu_events_attr_group = {"events" ,static const struct attribute_group mcb_pmu_events_attr_group = {"events" ,static const struct attribute_group mc_pmu_events_attr_group = {"events" ,static struct attribute *l3c_pmu_v3_events_attrs[] = {0 x00),0 x01),0 x02),0 x03),0 x04),not -caused-replacement, 0 x05),0 x06),0 x07),0 x08),0 x09),0 x0a),0 x0b),0 x0c),0 x0d),0 x0e),0 x10),0 x11),0 x12),0 x13),0 x14),0 x15),0 x16),0 x17),0 x18),0 x19),0 x1a),0 x1b),0 x1c),0 x1d),0 x1e),0 x1f),0 x20),0 x21),0 x22),0 x23),0 x24),0 x25),0 x26),0 x27),static struct attribute *iob_fast_pmu_v3_events_attrs[] = {0 x00),0 x01),0 x02),0 x03),0 x04),0 x05),0 x06),0 x07),0 x08),0 x09),0 x0a),0 x0b),0 x10),0 x11),0 x12),0 x13),0 x14),0 x15),0 x16),0 x17),0 x18),0 x1b),0 x1c),0 x1d),0 x20),0 x21),0 x22),0 x23),0 x24),0 x25),0 x26),0 x28),0 x29),0 x2a),0 x2b),0 x2c),0 x2d),0 x2e),0 x2f),static struct attribute *iob_slow_pmu_v3_events_attrs[] = {0 x00),0 x01),0 x02),0 x03),0 x04),0 x07),0 x08),0 x09),0 x10),static struct attribute *mcb_pmu_v3_events_attrs[] = {0 x00),0 x01),0 x02),2 , 0 x03),0 x04),2 , 0 x05),0 x06),2 , 0 x07),0 x08),2 , 0 x09),for -rd-sent-to-spec-mcu, 0 x0a),for -rd-sent-to-spec-mcu, 0 x0b),for -rd-sent-to-spec-mcu, 0 x0c),0 x0d),2 , 0 x0e),0 x0f),0 x10),0 x11),0 x12),0 x13),0 x14),0 x15),0 x16),0 x17),0 x18),0 x19),0 x1a),0 x1b),0 x1c),0 x1d),0 x1e),0 x1f),0 x20),0 x21),0 x22),0 x23),static struct attribute *mc_pmu_v3_events_attrs[] = {0 x00),0 x01),0 x02),0 x03),0 x04),0 x05),0 x06),0 x07),0 x08),0 x09),0 x0a),0 x0b),0 x0c),0 x0d),0 x0e),0 x0f),0 x10),0 x11),0 x12),0 x13),0 x14),0 x15),0 x16),0 x17),0 x18),0 x19),0 x1a),0 x1b),0 x1c),0 x1d),0 x1e),0 x1f),0 x20),0 x21),0 x22),0 x23),0 x24),0 x25),0 x26),0 x27),0 x28),0 x29),0 x2a),0 x2b),0 x2c),static const struct attribute_group l3c_pmu_v3_events_attr_group = {"events" ,static const struct attribute_group iob_fast_pmu_v3_events_attr_group = {"events" ,static const struct attribute_group iob_slow_pmu_v3_events_attr_group = {"events" ,static const struct attribute_group mcb_pmu_v3_events_attr_group = {"events" ,static const struct attribute_group mc_pmu_v3_events_attr_group = {"events" ,/* * sysfs cpumask attributes static ssize_t cpumask_show(struct device *dev,struct device_attribute *attr, char *buf)struct xgene_pmu_dev *pmu_dev = to_pmu_dev(dev_get_drvdata(dev));return cpumap_print_to_pagebuf(true , buf, &pmu_dev->parent->cpu);static DEVICE_ATTR_RO(cpumask);static struct attribute *xgene_pmu_cpumask_attrs[] = {static const struct attribute_group pmu_cpumask_attr_group = {/* * Per PMU device attribute groups of PMU v1 and v2 static const struct attribute_group *l3c_pmu_attr_groups[] = {static const struct attribute_group *iob_pmu_attr_groups[] = {static const struct attribute_group *mcb_pmu_attr_groups[] = {static const struct attribute_group *mc_pmu_attr_groups[] = {/* * Per PMU device attribute groups of PMU v3 static const struct attribute_group *l3c_pmu_v3_attr_groups[] = {static const struct attribute_group *iob_fast_pmu_v3_attr_groups[] = {static const struct attribute_group *iob_slow_pmu_v3_attr_groups[] = {static const struct attribute_group *mcb_pmu_v3_attr_groups[] = {static const struct attribute_group *mc_pmu_v3_attr_groups[] = {static int get_next_avail_cntr(struct xgene_pmu_dev *pmu_dev)int cntr;if (cntr == pmu_dev->max_counters)return -ENOSPC;return cntr;static void clear_avail_cntr(struct xgene_pmu_dev *pmu_dev, int cntr)static inline void xgene_pmu_mask_int(struct xgene_pmu *xgene_pmu)static inline void xgene_pmu_v3_mask_int(struct xgene_pmu *xgene_pmu)static inline void xgene_pmu_unmask_int(struct xgene_pmu *xgene_pmu)static inline void xgene_pmu_v3_unmask_int(struct xgene_pmu *xgene_pmu)static inline u64 xgene_pmu_read_counter32(struct xgene_pmu_dev *pmu_dev,int idx)return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));static inline u64 xgene_pmu_read_counter64(struct xgene_pmu_dev *pmu_dev,int idx)/* * v3 has 64 - bit counter registers composed by 2 32 - bit registers * This can be a problem if the counter increases and carries * out of bit [ 31 ] between 2 reads . The extra reads would help * to prevent this issue . do {2 * idx + 1 );2 * idx);while (hi != xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1 ));return (((u64)hi << 32 ) | lo);static inline void struct xgene_pmu_dev *pmu_dev, int idx, u64 val)4 * idx));static inline void struct xgene_pmu_dev *pmu_dev, int idx, u64 val)/* v3 has 64-bit counter registers composed by 2 32-bit registers */ 2 * idx, cnt_lo);2 * idx + 1 , cnt_hi);static inline void struct xgene_pmu_dev *pmu_dev, int idx, u32 val)4 * idx));static inline void struct xgene_pmu_dev *pmu_dev, u32 val)static inline void struct xgene_pmu_dev *pmu_dev, u32 val) { }static inline void struct xgene_pmu_dev *pmu_dev, u32 val)static inline void struct xgene_pmu_dev *pmu_dev, u32 val) { }static inline void struct xgene_pmu_dev *pmu_dev, int idx)1 << idx;static inline void struct xgene_pmu_dev *pmu_dev, int idx)1 << idx;static inline void struct xgene_pmu_dev *pmu_dev, int idx)1 << idx;static inline void struct xgene_pmu_dev *pmu_dev, int idx)1 << idx;static inline void xgene_pmu_reset_counters(struct xgene_pmu_dev *pmu_dev)static inline void xgene_pmu_start_counters(struct xgene_pmu_dev *pmu_dev)static inline void xgene_pmu_stop_counters(struct xgene_pmu_dev *pmu_dev)static void xgene_perf_pmu_enable(struct pmu *pmu)struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);struct xgene_pmu *xgene_pmu = pmu_dev->parent;bool enabled = !bitmap_empty(pmu_dev->cntr_assign_mask,if (!enabled)return ;static void xgene_perf_pmu_disable(struct pmu *pmu)struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);struct xgene_pmu *xgene_pmu = pmu_dev->parent;static int xgene_perf_event_init(struct perf_event *event)struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);struct hw_perf_event *hw = &event->hw;struct perf_event *sibling;/* Test the event attr type check for PMU enumeration */ if (event->attr.type != event->pmu->type)return -ENOENT;/* * SOC PMU counters are shared across all cores . * Therefore , it does not support per - process mode . * Also , it does not support event sampling mode . if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)return -EINVAL;if (event->cpu < 0 )return -EINVAL;/* * Many perf core operations ( eg . events rotation ) operate on a * single CPU context . This is obvious for CPU PMUs , where one * expects the same sets of events being observed on all CPUs , * but can lead to issues for off - core PMUs , where each * event could be theoretically assigned to a different CPU . To * mitigate this , we enforce CPU assignment to one , selected * processor ( the one described in the " cpumask " attribute ) . /* * Each bit of the config1 field represents an agent from which the * request of the event come . The event is counted only if it ' s caused * by a request of an agent has the bit cleared . * By default , the event is counted for all agents . /* * We must NOT create groups containing mixed PMUs , although software * events are acceptable if (event->group_leader->pmu != event->pmu &&return -EINVAL;if (sibling->pmu != event->pmu &&return -EINVAL;return 0 ;static void xgene_perf_enable_event(struct perf_event *event)struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);struct xgene_pmu *xgene_pmu = pmu_dev->parent;if (pmu_dev->inf->type == PMU_TYPE_IOB)static void xgene_perf_disable_event(struct perf_event *event)struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);struct xgene_pmu *xgene_pmu = pmu_dev->parent;static void xgene_perf_event_set_period(struct perf_event *event)struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);struct xgene_pmu *xgene_pmu = pmu_dev->parent;struct hw_perf_event *hw = &event->hw;/* * For 32 bit counter , it has a period of 2 ^ 32 . To account for the * possibility of extreme interrupt latency we program for a period of * half that . Hopefully , we can handle the interrupt before another 2 ^ 31 * events occur and the counter overtakes its previous value . * For 64 bit counter , we don ' t expect it overflow . 1 ULL << 31 ;static void xgene_perf_event_update(struct perf_event *event)struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);struct xgene_pmu *xgene_pmu = pmu_dev->parent;struct hw_perf_event *hw = &event->hw;if (local64_cmpxchg(&hw->prev_count, prev_raw_count,goto again;static void xgene_perf_read(struct perf_event *event)static void xgene_perf_start(struct perf_event *event, int flags)struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);struct xgene_pmu *xgene_pmu = pmu_dev->parent;struct hw_perf_event *hw = &event->hw;if (WARN_ON_ONCE(!(hw->state & PERF_HES_STOPPED)))return ;0 ;if (flags & PERF_EF_RELOAD) {static void xgene_perf_stop(struct perf_event *event, int flags)struct hw_perf_event *hw = &event->hw;if (hw->state & PERF_HES_UPTODATE)return ;if (hw->state & PERF_HES_UPTODATE)return ;static int xgene_perf_add(struct perf_event *event, int flags)struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);struct hw_perf_event *hw = &event->hw;/* Allocate an event counter */ if (hw->idx < 0 )return -EAGAIN;/* Update counter event pointer for Interrupt handler */ if (flags & PERF_EF_START)return 0 ;static void xgene_perf_del(struct perf_event *event, int flags)struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);struct hw_perf_event *hw = &event->hw;/* clear the assigned counter */ static int xgene_init_perf(struct xgene_pmu_dev *pmu_dev, char *name)struct xgene_pmu *xgene_pmu;if (pmu_dev->parent->version == PCP_PMU_V3)else /* First version PMU supports only single event counter */ if (xgene_pmu->version == PCP_PMU_V1)1 ;else /* Perf driver registration */ struct pmu) {/* Hardware counter init */ return perf_pmu_register(&pmu_dev->pmu, name, -1 );static int struct xgene_pmu *xgene_pmu, struct xgene_pmu_dev_ctx *ctx)struct device *dev = xgene_pmu->dev;struct xgene_pmu_dev *pmu;sizeof (*pmu), GFP_KERNEL);if (!pmu)return -ENOMEM;switch (pmu->inf->type) {case PMU_TYPE_L3C:if (!(xgene_pmu->l3c_active_mask & pmu->inf->enable_mask))return -ENODEV;if (xgene_pmu->version == PCP_PMU_V3)else break ;case PMU_TYPE_IOB:if (xgene_pmu->version == PCP_PMU_V3)else break ;case PMU_TYPE_IOB_SLOW:if (xgene_pmu->version == PCP_PMU_V3)break ;case PMU_TYPE_MCB:if (!(xgene_pmu->mcb_active_mask & pmu->inf->enable_mask))return -ENODEV;if (xgene_pmu->version == PCP_PMU_V3)else break ;case PMU_TYPE_MC:if (!(xgene_pmu->mc_active_mask & pmu->inf->enable_mask))return -ENODEV;if (xgene_pmu->version == PCP_PMU_V3)else break ;default :return -EINVAL;if (xgene_init_perf(pmu, ctx->name)) {"%s PMU: Failed to init perf driver\n" , ctx->name);return -ENODEV;"%s PMU registered\n" , ctx->name);return 0 ;static void _xgene_pmu_isr(int irq, struct xgene_pmu_dev *pmu_dev)struct xgene_pmu *xgene_pmu = pmu_dev->parent;void __iomem *csr = pmu_dev->inf->csr;int idx;if (xgene_pmu->version == PCP_PMU_V3)else if (!pmovsr)goto out;/* Clear interrupt flag */ if (xgene_pmu->version == PCP_PMU_V1)0 x0, csr + PMU_PMOVSR);else if (xgene_pmu->version == PCP_PMU_V2)else for (idx = 0 ; idx < PMU_MAX_COUNTERS; idx++) {struct perf_event *event = pmu_dev->pmu_counter_event[idx];int overflowed = pmovsr & BIT(idx);/* Ignore if we don't have an event. */ if (!event || !overflowed)continue ;static irqreturn_t xgene_pmu_isr(int irq, void *dev_id)struct xgene_pmu_dev_ctx *ctx;struct xgene_pmu *xgene_pmu = dev_id;/* Get Interrupt PMU source */ if (xgene_pmu->version == PCP_PMU_V3) {else {if (val & intr_mcu) {if (val & intr_mcb) {if (val & intr_l3c) {if (val & intr_iob) {return IRQ_HANDLED;static int acpi_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,struct platform_device *pdev)void __iomem *csw_csr, *mcba_csr, *mcbb_csr;unsigned int reg;1 );if (IS_ERR(csw_csr)) {"ioremap failed for CSW CSR resource\n" );return PTR_ERR(csw_csr);2 );if (IS_ERR(mcba_csr)) {"ioremap failed for MCBA CSR resource\n" );return PTR_ERR(mcba_csr);3 );if (IS_ERR(mcbb_csr)) {"ioremap failed for MCBB CSR resource\n" );return PTR_ERR(mcbb_csr);0 x1;if (reg & CSW_CSWCR_DUALMCB_MASK) {/* Dual MCB active */ 0 x3;/* Probe all active MC(s) */ 0 xF : 0 x5;else {/* Single MCB active */ 0 x1;/* Probe all active MC(s) */ 0 x3 : 0 x1;return 0 ;static int acpi_pmu_v3_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,struct platform_device *pdev)void __iomem *csw_csr;unsigned int reg;1 );if (IS_ERR(csw_csr)) {"ioremap failed for CSW CSR resource\n" );return PTR_ERR(csw_csr);if (reg & CSW_CSWCR_DUALMCB_MASK) {/* Dual MCB active */ 0 x3;/* Probe all active L3C(s), maximum is 8 */ 0 xFF;/* Probe all active MC(s), maximum is 8 */ if ((mcb0routing == 0 x2) && (mcb1routing == 0 x2))0 xFF;else if ((mcb0routing == 0 x1) && (mcb1routing == 0 x1))0 x33;else 0 x11;else {/* Single MCB active */ 0 x1;/* Probe all active L3C(s), maximum is 4 */ 0 x0F;/* Probe all active MC(s), maximum is 4 */ if (mcb0routing == 0 x2)0 x0F;else if (mcb0routing == 0 x1)0 x03;else 0 x01;return 0 ;static int fdt_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,struct platform_device *pdev)struct regmap *csw_map, *mcba_map, *mcbb_map;struct device_node *np = pdev->dev.of_node;unsigned int reg;"regmap-csw" );if (IS_ERR(csw_map)) {"unable to get syscon regmap csw\n" );return PTR_ERR(csw_map);"regmap-mcba" );if (IS_ERR(mcba_map)) {"unable to get syscon regmap mcba\n" );return PTR_ERR(mcba_map);"regmap-mcbb" );if (IS_ERR(mcbb_map)) {"unable to get syscon regmap mcbb\n" );return PTR_ERR(mcbb_map);0 x1;if (regmap_read(csw_map, CSW_CSWCR, ®))return -EINVAL;if (reg & CSW_CSWCR_DUALMCB_MASK) {/* Dual MCB active */ 0 x3;/* Probe all active MC(s) */ if (regmap_read(mcbb_map, MCBADDRMR, ®))return 0 ;0 xF : 0 x5;else {/* Single MCB active */ 0 x1;/* Probe all active MC(s) */ if (regmap_read(mcba_map, MCBADDRMR, ®))return 0 ;0 x3 : 0 x1;return 0 ;static int xgene_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,struct platform_device *pdev)if (has_acpi_companion(&pdev->dev)) {if (xgene_pmu->version == PCP_PMU_V3)return acpi_pmu_v3_probe_active_mcb_mcu_l3c(xgene_pmu,else return acpi_pmu_probe_active_mcb_mcu_l3c(xgene_pmu,return fdt_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, pdev);static char *xgene_pmu_dev_name(struct device *dev, u32 type, int id)switch (type) {case PMU_TYPE_L3C:return devm_kasprintf(dev, GFP_KERNEL, "l3c%d" , id);case PMU_TYPE_IOB:return devm_kasprintf(dev, GFP_KERNEL, "iob%d" , id);case PMU_TYPE_IOB_SLOW:return devm_kasprintf(dev, GFP_KERNEL, "iob_slow%d" , id);case PMU_TYPE_MCB:return devm_kasprintf(dev, GFP_KERNEL, "mcb%d" , id);case PMU_TYPE_MC:return devm_kasprintf(dev, GFP_KERNEL, "mc%d" , id);default :return devm_kasprintf(dev, GFP_KERNEL, "unknown" );#if defined (CONFIG_ACPI)static struct struct xgene_pmu *xgene_pmu,struct acpi_device *adev, u32 type)struct device *dev = xgene_pmu->dev;struct list_head resource_list;struct xgene_pmu_dev_ctx *ctx;const union acpi_object *obj;struct hw_pmu_info *inf;void __iomem *dev_csr;struct resource res;struct resource_entry *rentry;int enable_bit;int rc;sizeof (*ctx), GFP_KERNEL);if (!ctx)return NULL;if (rc <= 0 ) {"PMU type %d: No resources found\n" , type);return NULL;if (resource_type(rentry->res) == IORESOURCE_MEM) {break ;if (rentry) {"PMU type %d: No memory resource found\n" , type);return NULL;if (IS_ERR(dev_csr)) {"PMU type %d: Fail to map resource\n" , type);return NULL;/* A PMU device node without enable-bit-index is always enabled */ "enable-bit-index" ,if (rc < 0 )0 ;else int ) obj->integer.value;if (!ctx->name) {"PMU type %d: Fail to get device name\n" , type);return NULL;1 << enable_bit;return ctx;static const struct acpi_device_id xgene_pmu_acpi_type_match[] = {"APMC0D5D" , PMU_TYPE_L3C},"APMC0D5E" , PMU_TYPE_IOB},"APMC0D5F" , PMU_TYPE_MCB},"APMC0D60" , PMU_TYPE_MC},"APMC0D84" , PMU_TYPE_L3C},"APMC0D85" , PMU_TYPE_IOB},"APMC0D86" , PMU_TYPE_IOB_SLOW},"APMC0D87" , PMU_TYPE_MCB},"APMC0D88" , PMU_TYPE_MC},static const struct acpi_device_id *xgene_pmu_acpi_match_type(const struct acpi_device_id *ids,struct acpi_device *adev)const struct acpi_device_id *match_id = NULL;const struct acpi_device_id *id;for (id = ids; id->id[0 ] || id->cls; id++) {if (!acpi_match_device_ids(adev, id))else if (match_id)break ;return match_id;static acpi_status acpi_pmu_dev_add(acpi_handle handle, u32 level,void *data, void **return_value)struct acpi_device *adev = acpi_fetch_acpi_dev(handle);const struct acpi_device_id *acpi_id;struct xgene_pmu *xgene_pmu = data;struct xgene_pmu_dev_ctx *ctx;if (!adev || acpi_bus_get_status(adev) || !adev->status.present)return AE_OK;if (!acpi_id)return AE_OK;if (!ctx)return AE_OK;if (xgene_pmu_dev_add(xgene_pmu, ctx)) {/* Can't add the PMU device, skip it */ return AE_OK;switch (ctx->inf.type) {case PMU_TYPE_L3C:break ;case PMU_TYPE_IOB:break ;case PMU_TYPE_IOB_SLOW:break ;case PMU_TYPE_MCB:break ;case PMU_TYPE_MC:break ;return AE_OK;static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,struct platform_device *pdev)struct device *dev = xgene_pmu->dev;if (!handle)return -EINVAL;1 ,if (ACPI_FAILURE(status)) {"failed to probe PMU devices\n" );return -ENODEV;return 0 ;#else static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,struct platform_device *pdev)return 0 ;#endif static struct struct xgene_pmu *xgene_pmu,struct device_node *np, u32 type)struct device *dev = xgene_pmu->dev;struct xgene_pmu_dev_ctx *ctx;struct hw_pmu_info *inf;void __iomem *dev_csr;struct resource res;int enable_bit;sizeof (*ctx), GFP_KERNEL);if (!ctx)return NULL;if (of_address_to_resource(np, 0 , &res) < 0 ) {"PMU type %d: No resource address found\n" , type);return NULL;if (IS_ERR(dev_csr)) {"PMU type %d: Fail to map resource\n" , type);return NULL;/* A PMU device node without enable-bit-index is always enabled */ if (of_property_read_u32(np, "enable-bit-index" , &enable_bit))0 ;if (!ctx->name) {"PMU type %d: Fail to get device name\n" , type);return NULL;1 << enable_bit;return ctx;static int fdt_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,struct platform_device *pdev)struct xgene_pmu_dev_ctx *ctx;struct device_node *np;if (!of_device_is_available(np))continue ;if (of_device_is_compatible(np, "apm,xgene-pmu-l3c" ))else if (of_device_is_compatible(np, "apm,xgene-pmu-iob" ))else if (of_device_is_compatible(np, "apm,xgene-pmu-mcb" ))else if (of_device_is_compatible(np, "apm,xgene-pmu-mc" ))else if (!ctx)continue ;if (xgene_pmu_dev_add(xgene_pmu, ctx)) {/* Can't add the PMU device, skip it */ continue ;switch (ctx->inf.type) {case PMU_TYPE_L3C:break ;case PMU_TYPE_IOB:break ;case PMU_TYPE_IOB_SLOW:break ;case PMU_TYPE_MCB:break ;case PMU_TYPE_MC:break ;return 0 ;static int xgene_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,struct platform_device *pdev)if (has_acpi_companion(&pdev->dev))return acpi_pmu_probe_pmu_dev(xgene_pmu, pdev);return fdt_pmu_probe_pmu_dev(xgene_pmu, pdev);static const struct xgene_pmu_data xgene_pmu_data = {static const struct xgene_pmu_data xgene_pmu_v2_data = {#ifdef CONFIG_ACPIstatic const struct xgene_pmu_data xgene_pmu_v3_data = {#endif static const struct xgene_pmu_ops xgene_pmu_ops = {static const struct xgene_pmu_ops xgene_pmu_v3_ops = {static const struct of_device_id xgene_pmu_of_match[] = {"apm,xgene-pmu" , .data = &xgene_pmu_data },"apm,xgene-pmu-v2" , .data = &xgene_pmu_v2_data },#ifdef CONFIG_ACPIstatic const struct acpi_device_id xgene_pmu_acpi_match[] = {"APMC0D5B" , (kernel_ulong_t)&xgene_pmu_data},"APMC0D5C" , (kernel_ulong_t)&xgene_pmu_v2_data},"APMC0D83" , (kernel_ulong_t)&xgene_pmu_v3_data},#endif static int xgene_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)struct xgene_pmu *xgene_pmu = hlist_entry_safe(node, struct xgene_pmu,if (cpumask_empty(&xgene_pmu->cpu))/* Overflow interrupt also should use the same CPU */ return 0 ;static int xgene_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)struct xgene_pmu *xgene_pmu = hlist_entry_safe(node, struct xgene_pmu,struct xgene_pmu_dev_ctx *ctx;unsigned int target;if (!cpumask_test_and_clear_cpu(cpu, &xgene_pmu->cpu))return 0 ;if (target >= nr_cpu_ids)return 0 ;/* Overflow interrupt also should use the same CPU */ return 0 ;static int xgene_pmu_probe(struct platform_device *pdev)const struct xgene_pmu_data *dev_data;struct xgene_pmu *xgene_pmu;int irq, rc;int version;/* Install a hook to update the reader CPU in case it goes offline */ "CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE" ,if (rc)return rc;sizeof (*xgene_pmu), GFP_KERNEL);if (!xgene_pmu)return -ENOMEM;if (!dev_data)return -ENODEV;if (version == PCP_PMU_V3)else "X-Gene PMU version %d\n" , xgene_pmu->version);0 );if (IS_ERR(xgene_pmu->pcppmu_csr)) {"ioremap failed for PCP PMU resource\n" );return PTR_ERR(xgene_pmu->pcppmu_csr);0 );if (irq < 0 )return -EINVAL;if (rc) {"Could not request IRQ %d\n" , irq);return rc;/* Check for active MCBs and MCUs */ if (rc) {"Unknown MCB/MCU active status\n" );0 x1;0 x1;/* Add this instance to the list used by the hotplug callback */ if (rc) {"Error %d registering hotplug" , rc);return rc;/* Walk through the tree for all PMU perf devices */ if (rc) {"No PMU perf devices found!\n" );goto out_unregister;/* Enable interrupt */ return 0 ;return rc;static void struct xgene_pmu *xgene_pmu, struct list_head *pmus)struct xgene_pmu_dev_ctx *ctx;static void xgene_pmu_remove(struct platform_device *pdev)struct xgene_pmu *xgene_pmu = dev_get_drvdata(&pdev->dev);static struct platform_driver xgene_pmu_driver = {"xgene-pmu" ,true ,
Messung V0.5 in Prozent C=98 H=98 G=97
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