// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Apple T7001 "A8X" SoC
*
* Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org>
* Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>
/ {
interrupt-parent = <&aic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &serial0;
};
clkref: clock-ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "clkref";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "apple,typhoon";
reg = <0x0 0x0>;
cpu-release-addr = <0 0>; /* To be filled in by loader */
performance-domains = <&cpufreq>;
operating-points-v2 = <&typhoon_opp>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
cpu1: cpu@1 {
compatible = "apple,typhoon";
reg = <0x0 0x1>;
cpu-release-addr = <0 0>; /* To be filled in by loader */
performance-domains = <&cpufreq>;
operating-points-v2 = <&typhoon_opp>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
cpu2: cpu@2 {
compatible = "apple,typhoon";
reg = <0x0 0x2>;
cpu-release-addr = <0 0>; /* To be filled by loader */
performance-domains = <&cpufreq>;
operating-points-v2 = <&typhoon_opp>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
l2_cache: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x200000>;
};
};
typhoon_opp: opp-table {
compatible = "operating-points-v2";
opp01 {
opp-hz = /bits/ 64 <300000000>;
opp-level = <1>;
clock-latency-ns = <300>;
};
opp02 {
opp-hz = /bits/ 64 <396000000>;
opp-level = <2>;
clock-latency-ns = <49000>;
};
opp03 {
opp-hz = /bits/ 64 <600000000>;
opp-level = <3>;
clock-latency-ns = <31000>;
};
opp04 {
opp-hz = /bits/ 64 <840000000>;
opp-level = <4>;
clock-latency-ns = <32000>;
};
opp05 {
opp-hz = /bits/ 64 <1128000000>;
opp-level = <5>;
clock-latency-ns = <32000>;
};
opp06 {
opp-hz = /bits/ 64 <1392000000>;
opp-level = <6>;
clock-latency-ns = <37000>;
};
opp07 {
opp-hz = /bits/ 64 <1512000000>;
opp-level = <7>;
clock-latency-ns = <41000>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
nonposted-mmio;
ranges;
cpufreq: performance-controller@202220000 {
compatible = "apple,t7000-cluster-cpufreq", "apple,s5l8960x-cluster-cpufreq";
reg = <0x2 0x02220000 0 0x1000>;
#performance-domain-cells = <0>;
};
serial0: serial@20a0c0000 {
compatible = "apple,s5l-uart";
reg = <0x2 0x0a0c0000 0x0 0x4000>;
reg-io-width = <4>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 158 IRQ_TYPE_LEVEL_HIGH>;
/* Use the bootloader-enabled clocks for now. */
clocks = <&clkref>, <&clkref>;
clock-names = "uart", "clk_uart_baud0";
power-domains = <&ps_uart0>;
status = "disabled";
};
pmgr: power-management@20e000000 {
compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2 0xe000000 0 0x24000>;
};
wdt: watchdog@20e027000 {
compatible = "apple,t7000-wdt", "apple,wdt";
reg = <0x2 0x0e027000 0x0 0x1000>;
clocks = <&clkref>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>;
};
aic: interrupt-controller@20e100000 {
compatible = "apple,t7000-aic", "apple,aic";
reg = <0x2 0x0e100000 0x0 0x100000>;
#interrupt-cells = <3>;
interrupt-controller;
power-domains = <&ps_aic>;
};
pinctrl: pinctrl@20e300000 {
compatible = "apple,t7000-pinctrl", "apple,pinctrl";
reg = <0x2 0x0e300000 0x0 0x100000>;
power-domains = <&ps_gpio>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 184>;
apple,npins = <184>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 62 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 63 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 64 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 65 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 66 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 67 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 68 IRQ_TYPE_LEVEL_HIGH>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&aic>;
interrupt-names = "phys", "virt";
/* Note that A8X doesn't actually have a hypervisor (EL2 is not implemented). */
interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
<AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>;
};
};
#include "t7001-pmgr.dtsi"
