/* SPDX-License-Identifier: GPL-2.0 */ /* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h * * Copyright 2008 Openmoko , Inc . * Copyright 2008 Simtec Electronics * Ben Dooks < ben @ simtec . co . uk > * http : //armlinux.simtec.co.uk/ * * S3C64XX - GPIO register definitions #ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__/* Base addresses for each of the banks */ #define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GPIO + (reg))#define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0 x0000)#define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0 x0020)#define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0 x0040)#define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0 x0060)#define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0 x0080)#define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0 x00A0)#define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0 x00C0)#define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0 x00E0)#define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0 x0100)#define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0 x0120)#define S3C64XX_GPK_BASE S3C64XX_GPIOREG(0 x0800)#define S3C64XX_GPL_BASE S3C64XX_GPIOREG(0 x0810)#define S3C64XX_GPM_BASE S3C64XX_GPIOREG(0 x0820)#define S3C64XX_GPN_BASE S3C64XX_GPIOREG(0 x0830)#define S3C64XX_GPO_BASE S3C64XX_GPIOREG(0 x0140)#define S3C64XX_GPP_BASE S3C64XX_GPIOREG(0 x0160)#define S3C64XX_GPQ_BASE S3C64XX_GPIOREG(0 x0180)/* SPCON */ #define S3C64XX_SPCON S3C64XX_GPIOREG(0 x1A0)#define S3C64XX_SPCON_DRVCON_CAM_MASK (0 x3 << 30 )#define S3C64XX_SPCON_DRVCON_CAM_SHIFT (30 )#define S3C64XX_SPCON_DRVCON_CAM_2mA (0 x0 << 30 )#define S3C64XX_SPCON_DRVCON_CAM_4mA (0 x1 << 30 )#define S3C64XX_SPCON_DRVCON_CAM_7mA (0 x2 << 30 )#define S3C64XX_SPCON_DRVCON_CAM_9mA (0 x3 << 30 )#define S3C64XX_SPCON_DRVCON_HSSPI_MASK (0 x3 << 28 )#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT (28 )#define S3C64XX_SPCON_DRVCON_HSSPI_2mA (0 x0 << 28 )#define S3C64XX_SPCON_DRVCON_HSSPI_4mA (0 x1 << 28 )#define S3C64XX_SPCON_DRVCON_HSSPI_7mA (0 x2 << 28 )#define S3C64XX_SPCON_DRVCON_HSSPI_9mA (0 x3 << 28 )#define S3C64XX_SPCON_DRVCON_HSMMC_MASK (0 x3 << 26 )#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT (26 )#define S3C64XX_SPCON_DRVCON_HSMMC_2mA (0 x0 << 26 )#define S3C64XX_SPCON_DRVCON_HSMMC_4mA (0 x1 << 26 )#define S3C64XX_SPCON_DRVCON_HSMMC_7mA (0 x2 << 26 )#define S3C64XX_SPCON_DRVCON_HSMMC_9mA (0 x3 << 26 )#define S3C64XX_SPCON_DRVCON_LCD_MASK (0 x3 << 24 )#define S3C64XX_SPCON_DRVCON_LCD_SHIFT (24 )#define S3C64XX_SPCON_DRVCON_LCD_2mA (0 x0 << 24 )#define S3C64XX_SPCON_DRVCON_LCD_4mA (0 x1 << 24 )#define S3C64XX_SPCON_DRVCON_LCD_7mA (0 x2 << 24 )#define S3C64XX_SPCON_DRVCON_LCD_9mA (0 x3 << 24 )#define S3C64XX_SPCON_DRVCON_MODEM_MASK (0 x3 << 22 )#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT (22 )#define S3C64XX_SPCON_DRVCON_MODEM_2mA (0 x0 << 22 )#define S3C64XX_SPCON_DRVCON_MODEM_4mA (0 x1 << 22 )#define S3C64XX_SPCON_DRVCON_MODEM_7mA (0 x2 << 22 )#define S3C64XX_SPCON_DRVCON_MODEM_9mA (0 x3 << 22 )#define S3C64XX_SPCON_nRSTOUT_OEN (1 << 21 )#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK (0 x3 << 18 )#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT (18 )#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA (0 x0 << 18 )#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA (0 x1 << 18 )#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA (0 x2 << 18 )#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA (0 x3 << 18 )#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK (0 x3 << 16 )#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT (16 )#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED (0 x0 << 16 )#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN (0 x1 << 16 )#define S3C64XX_SPCON_MEM1_DQS_PUD_UP (0 x2 << 16 )#define S3C64XX_SPCON_MEM1_D_PUD1_MASK (0 x3 << 14 )#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT (14 )#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED (0 x0 << 14 )#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN (0 x1 << 14 )#define S3C64XX_SPCON_MEM1_D_PUD1_UP (0 x2 << 14 )#define S3C64XX_SPCON_MEM1_D_PUD0_MASK (0 x3 << 12 )#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT (12 )#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED (0 x0 << 12 )#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN (0 x1 << 12 )#define S3C64XX_SPCON_MEM1_D_PUD0_UP (0 x2 << 12 )#define S3C64XX_SPCON_MEM0_D_PUD_MASK (0 x3 << 8 )#define S3C64XX_SPCON_MEM0_D_PUD_SHIFT (8 )#define S3C64XX_SPCON_MEM0_D_PUD_DISABLED (0 x0 << 8 )#define S3C64XX_SPCON_MEM0_D_PUD_DOWN (0 x1 << 8 )#define S3C64XX_SPCON_MEM0_D_PUD_UP (0 x2 << 8 )#define S3C64XX_SPCON_USBH_DMPD (1 << 7 )#define S3C64XX_SPCON_USBH_DPPD (1 << 6 )#define S3C64XX_SPCON_USBH_PUSW2 (1 << 5 )#define S3C64XX_SPCON_USBH_PUSW1 (1 << 4 )#define S3C64XX_SPCON_USBH_SUSPND (1 << 3 )#define S3C64XX_SPCON_LCD_SEL_MASK (0 x3 << 0 )#define S3C64XX_SPCON_LCD_SEL_SHIFT (0 )#define S3C64XX_SPCON_LCD_SEL_HOST (0 x0 << 0 )#define S3C64XX_SPCON_LCD_SEL_RGB (0 x1 << 0 )#define S3C64XX_SPCON_LCD_SEL_606_656 (0 x2 << 0 )/* External interrupt registers */ #define S3C64XX_EINT12CON S3C64XX_GPIOREG(0 x200)#define S3C64XX_EINT34CON S3C64XX_GPIOREG(0 x204)#define S3C64XX_EINT56CON S3C64XX_GPIOREG(0 x208)#define S3C64XX_EINT78CON S3C64XX_GPIOREG(0 x20C)#define S3C64XX_EINT9CON S3C64XX_GPIOREG(0 x210)#define S3C64XX_EINT12FLTCON S3C64XX_GPIOREG(0 x220)#define S3C64XX_EINT34FLTCON S3C64XX_GPIOREG(0 x224)#define S3C64XX_EINT56FLTCON S3C64XX_GPIOREG(0 x228)#define S3C64XX_EINT78FLTCON S3C64XX_GPIOREG(0 x22C)#define S3C64XX_EINT9FLTCON S3C64XX_GPIOREG(0 x230)#define S3C64XX_EINT12MASK S3C64XX_GPIOREG(0 x240)#define S3C64XX_EINT34MASK S3C64XX_GPIOREG(0 x244)#define S3C64XX_EINT56MASK S3C64XX_GPIOREG(0 x248)#define S3C64XX_EINT78MASK S3C64XX_GPIOREG(0 x24C)#define S3C64XX_EINT9MASK S3C64XX_GPIOREG(0 x250)#define S3C64XX_EINT12PEND S3C64XX_GPIOREG(0 x260)#define S3C64XX_EINT34PEND S3C64XX_GPIOREG(0 x264)#define S3C64XX_EINT56PEND S3C64XX_GPIOREG(0 x268)#define S3C64XX_EINT78PEND S3C64XX_GPIOREG(0 x26C)#define S3C64XX_EINT9PEND S3C64XX_GPIOREG(0 x270)#define S3C64XX_PRIORITY S3C64XX_GPIOREG(0 x280)#define S3C64XX_PRIORITY_ARB(x) (1 << (x))#define S3C64XX_SERVICE S3C64XX_GPIOREG(0 x284)#define S3C64XX_SERVICEPEND S3C64XX_GPIOREG(0 x288)#define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0 x900)#define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0 x904)#define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0 x910)#define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0 x914)#define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0 x918)#define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0 x91C)#define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0 x920)#define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0 x924)/* GPIO sleep configuration */ #define S3C64XX_SPCONSLP S3C64XX_GPIOREG(0 x880)#define S3C64XX_SPCONSLP_TDO_PULLDOWN (1 << 14 )#define S3C64XX_SPCONSLP_CKE1INIT (1 << 5 )#define S3C64XX_SPCONSLP_RSTOUT_MASK (0 x3 << 12 )#define S3C64XX_SPCONSLP_RSTOUT_OUT0 (0 x0 << 12 )#define S3C64XX_SPCONSLP_RSTOUT_OUT1 (0 x1 << 12 )#define S3C64XX_SPCONSLP_RSTOUT_HIZ (0 x2 << 12 )#define S3C64XX_SPCONSLP_KPCOL_MASK (0 x3 << 0 )#define S3C64XX_SPCONSLP_KPCOL_OUT0 (0 x0 << 0 )#define S3C64XX_SPCONSLP_KPCOL_OUT1 (0 x1 << 0 )#define S3C64XX_SPCONSLP_KPCOL_INP (0 x2 << 0 )#define S3C64XX_SLPEN S3C64XX_GPIOREG(0 x930)#define S3C64XX_SLPEN_USE_xSLP (1 << 0 )#define S3C64XX_SLPEN_CFG_BYSLPEN (1 << 1 )#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */
Messung V0.5 in Prozent C=97 H=85 G=91
¤ Dauer der Verarbeitung: 0.9 Sekunden
(vorverarbeitet am 2026-09-28)
¤ *© Formatika GbR, Deutschland
