/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP.
*
*/
#ifndef __DTS_IMX6SLL_PINFUNC_H
#define __DTS_IMX6SLL_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX6SLL_PAD_WDOG_B__WDOG1_B 0 x0014 0 x02DC 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0 x0014 0 x02DC 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_WDOG_B__UART5_RI_B 0 x0014 0 x02DC 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0 x0014 0 x02DC 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0 x0018 0 x02E0 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0 x0018 0 x02E0 0 x068C 0 x1 0 x0
#define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0 x0018 0 x02E0 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0 x0018 0 x02E0 0 x0560 0 x3 0 x0
#define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0 x0018 0 x02E0 0 x05AC 0 x4 0 x0
#define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0 x0018 0 x02E0 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_REF_CLK_24M__SD3_WP 0 x0018 0 x02E0 0 x0794 0 x6 0 x0
#define MX6SLL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0 x001C 0 x02E4 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0 x001C 0 x02E4 0 x0690 0 x1 0 x0
#define MX6SLL_PAD_REF_CLK_32K__PWM4_OUT 0 x001C 0 x02E4 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_REF_CLK_32K__USB_OTG1_ID 0 x001C 0 x02E4 0 x055C 0 x3 0 x0
#define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL 0 x001C 0 x02E4 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0 x001C 0 x02E4 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_REF_CLK_32K__SD3_CD_B 0 x001C 0 x02E4 0 x0780 0 x6 0 x0
#define MX6SLL_PAD_PWM1__PWM1_OUT 0 x0020 0 x02E8 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_PWM1__CCM_CLKO 0 x0020 0 x02E8 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_PWM1__AUDIO_CLK_OUT 0 x0020 0 x02E8 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_PWM1__CSI_MCLK 0 x0020 0 x02E8 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_PWM1__GPIO3_IO23 0 x0020 0 x02E8 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_PWM1__EPIT1_OUT 0 x0020 0 x02E8 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_KEY_COL0__KEY_COL0 0 x0024 0 x02EC 0 x06A0 0 x0 0 x0
#define MX6SLL_PAD_KEY_COL0__I2C2_SCL 0 x0024 0 x02EC 0 x0684 0 x1 0 x0
#define MX6SLL_PAD_KEY_COL0__LCD_DATA00 0 x0024 0 x02EC 0 x06D8 0 x2 0 x0
#define MX6SLL_PAD_KEY_COL0__SD1_CD_B 0 x0024 0 x02EC 0 x0770 0 x4 0 x1
#define MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0 x0024 0 x02EC 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_KEY_ROW0__KEY_ROW0 0 x0028 0 x02F0 0 x06C0 0 x0 0 x0
#define MX6SLL_PAD_KEY_ROW0__I2C2_SDA 0 x0028 0 x02F0 0 x0688 0 x1 0 x0
#define MX6SLL_PAD_KEY_ROW0__LCD_DATA01 0 x0028 0 x02F0 0 x06DC 0 x2 0 x0
#define MX6SLL_PAD_KEY_ROW0__SD1_WP 0 x0028 0 x02F0 0 x0774 0 x4 0 x1
#define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25 0 x0028 0 x02F0 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_KEY_COL1__KEY_COL1 0 x002C 0 x02F4 0 x06A4 0 x0 0 x0
#define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI 0 x002C 0 x02F4 0 x0658 0 x1 0 x1
#define MX6SLL_PAD_KEY_COL1__LCD_DATA02 0 x002C 0 x02F4 0 x06E0 0 x2 0 x0
#define MX6SLL_PAD_KEY_COL1__SD3_DATA4 0 x002C 0 x02F4 0 x0784 0 x4 0 x0
#define MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0 x002C 0 x02F4 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_KEY_ROW1__KEY_ROW1 0 x0030 0 x02F8 0 x06C4 0 x0 0 x0
#define MX6SLL_PAD_KEY_ROW1__ECSPI4_MISO 0 x0030 0 x02F8 0 x0654 0 x1 0 x1
#define MX6SLL_PAD_KEY_ROW1__LCD_DATA03 0 x0030 0 x02F8 0 x06E4 0 x2 0 x0
#define MX6SLL_PAD_KEY_ROW1__CSI_FIELD 0 x0030 0 x02F8 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_KEY_ROW1__SD3_DATA5 0 x0030 0 x02F8 0 x0788 0 x4 0 x0
#define MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0 x0030 0 x02F8 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_KEY_COL2__KEY_COL2 0 x0034 0 x02FC 0 x06A8 0 x0 0 x0
#define MX6SLL_PAD_KEY_COL2__ECSPI4_SS0 0 x0034 0 x02FC 0 x065C 0 x1 0 x1
#define MX6SLL_PAD_KEY_COL2__LCD_DATA04 0 x0034 0 x02FC 0 x06E8 0 x2 0 x0
#define MX6SLL_PAD_KEY_COL2__CSI_DATA12 0 x0034 0 x02FC 0 x05B8 0 x3 0 x1
#define MX6SLL_PAD_KEY_COL2__SD3_DATA6 0 x0034 0 x02FC 0 x078C 0 x4 0 x0
#define MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0 x0034 0 x02FC 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_KEY_ROW2__KEY_ROW2 0 x0038 0 x0300 0 x06C8 0 x0 0 x0
#define MX6SLL_PAD_KEY_ROW2__ECSPI4_SCLK 0 x0038 0 x0300 0 x0650 0 x1 0 x1
#define MX6SLL_PAD_KEY_ROW2__LCD_DATA05 0 x0038 0 x0300 0 x06EC 0 x2 0 x0
#define MX6SLL_PAD_KEY_ROW2__CSI_DATA13 0 x0038 0 x0300 0 x05BC 0 x3 0 x1
#define MX6SLL_PAD_KEY_ROW2__SD3_DATA7 0 x0038 0 x0300 0 x0790 0 x4 0 x0
#define MX6SLL_PAD_KEY_ROW2__GPIO3_IO29 0 x0038 0 x0300 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_KEY_COL3__KEY_COL3 0 x003C 0 x0304 0 x06AC 0 x0 0 x0
#define MX6SLL_PAD_KEY_COL3__AUD6_RXFS 0 x003C 0 x0304 0 x05A0 0 x1 0 x1
#define MX6SLL_PAD_KEY_COL3__LCD_DATA06 0 x003C 0 x0304 0 x06F0 0 x2 0 x0
#define MX6SLL_PAD_KEY_COL3__CSI_DATA14 0 x003C 0 x0304 0 x05C0 0 x3 0 x1
#define MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0 x003C 0 x0304 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_KEY_COL3__SD1_RESET 0 x003C 0 x0304 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_KEY_ROW3__KEY_ROW3 0 x0040 0 x0308 0 x06CC 0 x0 0 x1
#define MX6SLL_PAD_KEY_ROW3__AUD6_RXC 0 x0040 0 x0308 0 x059C 0 x1 0 x1
#define MX6SLL_PAD_KEY_ROW3__LCD_DATA07 0 x0040 0 x0308 0 x06F4 0 x2 0 x1
#define MX6SLL_PAD_KEY_ROW3__CSI_DATA15 0 x0040 0 x0308 0 x05C4 0 x3 0 x2
#define MX6SLL_PAD_KEY_ROW3__GPIO3_IO31 0 x0040 0 x0308 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_KEY_ROW3__SD1_VSELECT 0 x0040 0 x0308 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_KEY_COL4__KEY_COL4 0 x0044 0 x030C 0 x06B0 0 x0 0 x1
#define MX6SLL_PAD_KEY_COL4__AUD6_RXD 0 x0044 0 x030C 0 x0594 0 x1 0 x1
#define MX6SLL_PAD_KEY_COL4__LCD_DATA08 0 x0044 0 x030C 0 x06F8 0 x2 0 x1
#define MX6SLL_PAD_KEY_COL4__CSI_DATA16 0 x0044 0 x030C 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0 x0044 0 x030C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_KEY_COL4__USB_OTG1_PWR 0 x0044 0 x030C 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_KEY_ROW4__KEY_ROW4 0 x0048 0 x0310 0 x06D0 0 x0 0 x1
#define MX6SLL_PAD_KEY_ROW4__AUD6_TXC 0 x0048 0 x0310 0 x05A4 0 x1 0 x1
#define MX6SLL_PAD_KEY_ROW4__LCD_DATA09 0 x0048 0 x0310 0 x06FC 0 x2 0 x1
#define MX6SLL_PAD_KEY_ROW4__CSI_DATA17 0 x0048 0 x0310 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_KEY_ROW4__GPIO4_IO01 0 x0048 0 x0310 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_KEY_ROW4__USB_OTG1_OC 0 x0048 0 x0310 0 x076C 0 x6 0 x2
#define MX6SLL_PAD_KEY_COL5__KEY_COL5 0 x004C 0 x0314 0 x0694 0 x0 0 x1
#define MX6SLL_PAD_KEY_COL5__AUD6_TXFS 0 x004C 0 x0314 0 x05A8 0 x1 0 x1
#define MX6SLL_PAD_KEY_COL5__LCD_DATA10 0 x004C 0 x0314 0 x0700 0 x2 0 x0
#define MX6SLL_PAD_KEY_COL5__CSI_DATA18 0 x004C 0 x0314 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0 x004C 0 x0314 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_KEY_COL5__USB_OTG2_PWR 0 x004C 0 x0314 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_KEY_ROW5__KEY_ROW5 0 x0050 0 x0318 0 x06B4 0 x0 0 x2
#define MX6SLL_PAD_KEY_ROW5__AUD6_TXD 0 x0050 0 x0318 0 x0598 0 x1 0 x1
#define MX6SLL_PAD_KEY_ROW5__LCD_DATA11 0 x0050 0 x0318 0 x0704 0 x2 0 x1
#define MX6SLL_PAD_KEY_ROW5__CSI_DATA19 0 x0050 0 x0318 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0 x0050 0 x0318 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_KEY_ROW5__USB_OTG2_OC 0 x0050 0 x0318 0 x0768 0 x6 0 x3
#define MX6SLL_PAD_KEY_COL6__KEY_COL6 0 x0054 0 x031C 0 x0698 0 x0 0 x2
#define MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0 x0054 0 x031C 0 x075C 0 x1 0 x2
#define MX6SLL_PAD_KEY_COL6__UART4_DTE_TX 0 x0054 0 x031C 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_KEY_COL6__LCD_DATA12 0 x0054 0 x031C 0 x0708 0 x2 0 x1
#define MX6SLL_PAD_KEY_COL6__CSI_DATA20 0 x0054 0 x031C 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0 x0054 0 x031C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_KEY_COL6__SD3_RESET 0 x0054 0 x031C 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_KEY_ROW6__KEY_ROW6 0 x0058 0 x0320 0 x06B8 0 x0 0 x2
#define MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0 x0058 0 x0320 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_KEY_ROW6__UART4_DTE_RX 0 x0058 0 x0320 0 x075C 0 x1 0 x3
#define MX6SLL_PAD_KEY_ROW6__LCD_DATA13 0 x0058 0 x0320 0 x070C 0 x2 0 x1
#define MX6SLL_PAD_KEY_ROW6__CSI_DATA21 0 x0058 0 x0320 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0 x0058 0 x0320 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_KEY_ROW6__SD3_VSELECT 0 x0058 0 x0320 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_KEY_COL7__KEY_COL7 0 x005C 0 x0324 0 x069C 0 x0 0 x2
#define MX6SLL_PAD_KEY_COL7__UART4_DCE_RTS 0 x005C 0 x0324 0 x0758 0 x1 0 x2
#define MX6SLL_PAD_KEY_COL7__UART4_DTE_CTS 0 x005C 0 x0324 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_KEY_COL7__LCD_DATA14 0 x005C 0 x0324 0 x0710 0 x2 0 x1
#define MX6SLL_PAD_KEY_COL7__CSI_DATA22 0 x005C 0 x0324 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_KEY_COL7__GPIO4_IO06 0 x005C 0 x0324 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_KEY_COL7__SD1_WP 0 x005C 0 x0324 0 x0774 0 x6 0 x3
#define MX6SLL_PAD_KEY_ROW7__KEY_ROW7 0 x0060 0 x0328 0 x06BC 0 x0 0 x2
#define MX6SLL_PAD_KEY_ROW7__UART4_DCE_CTS 0 x0060 0 x0328 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_KEY_ROW7__UART4_DTE_RTS 0 x0060 0 x0328 0 x0758 0 x1 0 x3
#define MX6SLL_PAD_KEY_ROW7__LCD_DATA15 0 x0060 0 x0328 0 x0714 0 x2 0 x1
#define MX6SLL_PAD_KEY_ROW7__CSI_DATA23 0 x0060 0 x0328 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0 x0060 0 x0328 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_KEY_ROW7__SD1_CD_B 0 x0060 0 x0328 0 x0770 0 x6 0 x3
#define MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0 x0064 0 x032C 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_DATA00__ECSPI4_MOSI 0 x0064 0 x032C 0 x0658 0 x1 0 x2
#define MX6SLL_PAD_EPDC_DATA00__LCD_DATA24 0 x0064 0 x032C 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_DATA00__CSI_DATA00 0 x0064 0 x032C 0 x05C8 0 x3 0 x2
#define MX6SLL_PAD_EPDC_DATA00__GPIO1_IO07 0 x0064 0 x032C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0 x0068 0 x0330 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_DATA01__ECSPI4_MISO 0 x0068 0 x0330 0 x0654 0 x1 0 x2
#define MX6SLL_PAD_EPDC_DATA01__LCD_DATA25 0 x0068 0 x0330 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_DATA01__CSI_DATA01 0 x0068 0 x0330 0 x05CC 0 x3 0 x2
#define MX6SLL_PAD_EPDC_DATA01__GPIO1_IO08 0 x0068 0 x0330 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0 x006C 0 x0334 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_DATA02__ECSPI4_SS0 0 x006C 0 x0334 0 x065C 0 x1 0 x2
#define MX6SLL_PAD_EPDC_DATA02__LCD_DATA26 0 x006C 0 x0334 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0 x006C 0 x0334 0 x05D0 0 x3 0 x2
#define MX6SLL_PAD_EPDC_DATA02__GPIO1_IO09 0 x006C 0 x0334 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0 x0070 0 x0338 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_DATA03__ECSPI4_SCLK 0 x0070 0 x0338 0 x0650 0 x1 0 x2
#define MX6SLL_PAD_EPDC_DATA03__LCD_DATA27 0 x0070 0 x0338 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0 x0070 0 x0338 0 x05D4 0 x3 0 x2
#define MX6SLL_PAD_EPDC_DATA03__GPIO1_IO10 0 x0070 0 x0338 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0 x0074 0 x033C 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_DATA04__ECSPI4_SS1 0 x0074 0 x033C 0 x0660 0 x1 0 x1
#define MX6SLL_PAD_EPDC_DATA04__LCD_DATA28 0 x0074 0 x033C 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0 x0074 0 x033C 0 x05D8 0 x3 0 x2
#define MX6SLL_PAD_EPDC_DATA04__GPIO1_IO11 0 x0074 0 x033C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0 x0078 0 x0340 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_DATA05__ECSPI4_SS2 0 x0078 0 x0340 0 x0664 0 x1 0 x1
#define MX6SLL_PAD_EPDC_DATA05__LCD_DATA29 0 x0078 0 x0340 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0 x0078 0 x0340 0 x05DC 0 x3 0 x2
#define MX6SLL_PAD_EPDC_DATA05__GPIO1_IO12 0 x0078 0 x0340 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0 x007C 0 x0344 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_DATA06__ECSPI4_SS3 0 x007C 0 x0344 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_EPDC_DATA06__LCD_DATA30 0 x007C 0 x0344 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0 x007C 0 x0344 0 x05E0 0 x3 0 x2
#define MX6SLL_PAD_EPDC_DATA06__GPIO1_IO13 0 x007C 0 x0344 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0 x0080 0 x0348 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_DATA07__ECSPI4_RDY 0 x0080 0 x0348 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_EPDC_DATA07__LCD_DATA31 0 x0080 0 x0348 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0 x0080 0 x0348 0 x05E4 0 x3 0 x2
#define MX6SLL_PAD_EPDC_DATA07__GPIO1_IO14 0 x0080 0 x0348 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0 x0084 0 x034C 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_DATA08__ECSPI3_MOSI 0 x0084 0 x034C 0 x063C 0 x1 0 x2
#define MX6SLL_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 0 x0084 0 x034C 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_DATA08__GPIO1_IO15 0 x0084 0 x034C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0 x0088 0 x0350 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_DATA09__ECSPI3_MISO 0 x0088 0 x0350 0 x0638 0 x1 0 x2
#define MX6SLL_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 0 x0088 0 x0350 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_DATA09__GPIO1_IO16 0 x0088 0 x0350 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0 x008C 0 x0354 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_DATA10__ECSPI3_SS0 0 x008C 0 x0354 0 x0648 0 x1 0 x2
#define MX6SLL_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 0 x008C 0 x0354 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_DATA10__GPIO1_IO17 0 x008C 0 x0354 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0 x0090 0 x0358 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_DATA11__ECSPI3_SCLK 0 x0090 0 x0358 0 x0630 0 x1 0 x2
#define MX6SLL_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 0 x0090 0 x0358 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_DATA11__GPIO1_IO18 0 x0090 0 x0358 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0 x0094 0 x035C 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_DATA12__UART2_DCE_RX 0 x0094 0 x035C 0 x074C 0 x1 0 x4
#define MX6SLL_PAD_EPDC_DATA12__UART2_DTE_TX 0 x0094 0 x035C 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_EPDC_DATA12__EPDC_PWR_COM 0 x0094 0 x035C 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_DATA12__GPIO1_IO19 0 x0094 0 x035C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_DATA12__ECSPI3_SS1 0 x0094 0 x035C 0 x064C 0 x6 0 x1
#define MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0 x0098 0 x0360 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_DATA13__UART2_DCE_TX 0 x0098 0 x0360 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_EPDC_DATA13__UART2_DTE_RX 0 x0098 0 x0360 0 x074C 0 x1 0 x5
#define MX6SLL_PAD_EPDC_DATA13__EPDC_PWR_IRQ 0 x0098 0 x0360 0 x0668 0 x2 0 x0
#define MX6SLL_PAD_EPDC_DATA13__GPIO1_IO20 0 x0098 0 x0360 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_DATA13__ECSPI3_SS2 0 x0098 0 x0360 0 x0640 0 x6 0 x1
#define MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0 x009C 0 x0364 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_DATA14__UART2_DCE_RTS 0 x009C 0 x0364 0 x0748 0 x1 0 x4
#define MX6SLL_PAD_EPDC_DATA14__UART2_DTE_CTS 0 x009C 0 x0364 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_EPDC_DATA14__EPDC_PWR_STAT 0 x009C 0 x0364 0 x066C 0 x2 0 x0
#define MX6SLL_PAD_EPDC_DATA14__GPIO1_IO21 0 x009C 0 x0364 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_DATA14__ECSPI3_SS3 0 x009C 0 x0364 0 x0644 0 x6 0 x1
#define MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0 x00A0 0 x0368 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_DATA15__UART2_DCE_CTS 0 x00A0 0 x0368 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_EPDC_DATA15__UART2_DTE_RTS 0 x00A0 0 x0368 0 x0748 0 x1 0 x5
#define MX6SLL_PAD_EPDC_DATA15__EPDC_PWR_WAKE 0 x00A0 0 x0368 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_DATA15__GPIO1_IO22 0 x00A0 0 x0368 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_DATA15__ECSPI3_RDY 0 x00A0 0 x0368 0 x0634 0 x6 0 x1
#define MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0 x00A4 0 x036C 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0 x00A4 0 x036C 0 x0624 0 x1 0 x2
#define MX6SLL_PAD_EPDC_SDCLK__I2C2_SCL 0 x00A4 0 x036C 0 x0684 0 x2 0 x2
#define MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0 x00A4 0 x036C 0 x05E8 0 x3 0 x2
#define MX6SLL_PAD_EPDC_SDCLK__GPIO1_IO23 0 x00A4 0 x036C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0 x00A8 0 x0370 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_SDLE__ECSPI2_MISO 0 x00A8 0 x0370 0 x0620 0 x1 0 x2
#define MX6SLL_PAD_EPDC_SDLE__I2C2_SDA 0 x00A8 0 x0370 0 x0688 0 x2 0 x2
#define MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0 x00A8 0 x0370 0 x05EC 0 x3 0 x2
#define MX6SLL_PAD_EPDC_SDLE__GPIO1_IO24 0 x00A8 0 x0370 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0 x00AC 0 x0374 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_SDOE__ECSPI2_SS0 0 x00AC 0 x0374 0 x0628 0 x1 0 x1
#define MX6SLL_PAD_EPDC_SDOE__CSI_DATA10 0 x00AC 0 x0374 0 x05B0 0 x3 0 x2
#define MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0 x00AC 0 x0374 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0 x00B0 0 x0378 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0 x00B0 0 x0378 0 x061C 0 x1 0 x2
#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDCE4 0 x00B0 0 x0378 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_SDSHR__CSI_DATA11 0 x00B0 0 x0378 0 x05B4 0 x3 0 x2
#define MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0 x00B0 0 x0378 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0 x00B4 0 x037C 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_SDCE0__ECSPI2_SS1 0 x00B4 0 x037C 0 x062C 0 x1 0 x1
#define MX6SLL_PAD_EPDC_SDCE0__PWM3_OUT 0 x00B4 0 x037C 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_SDCE0__GPIO1_IO27 0 x00B4 0 x037C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_SDCE1__EPDC_SDCE1 0 x00B8 0 x0380 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_SDCE1__WDOG2_B 0 x00B8 0 x0380 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_EPDC_SDCE1__PWM4_OUT 0 x00B8 0 x0380 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_SDCE1__GPIO1_IO28 0 x00B8 0 x0380 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_SDCE2__EPDC_SDCE2 0 x00BC 0 x0384 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0 x00BC 0 x0384 0 x068C 0 x1 0 x2
#define MX6SLL_PAD_EPDC_SDCE2__PWM1_OUT 0 x00BC 0 x0384 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 0 x00BC 0 x0384 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_SDCE3__EPDC_SDCE3 0 x00C0 0 x0388 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0 x00C0 0 x0388 0 x0690 0 x1 0 x2
#define MX6SLL_PAD_EPDC_SDCE3__PWM2_OUT 0 x00C0 0 x0388 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 0 x00C0 0 x0388 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0 x00C4 0 x038C 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_GDCLK__ECSPI2_SS2 0 x00C4 0 x038C 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0 x00C4 0 x038C 0 x05F4 0 x3 0 x2
#define MX6SLL_PAD_EPDC_GDCLK__GPIO1_IO31 0 x00C4 0 x038C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_GDCLK__SD2_RESET 0 x00C4 0 x038C 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0 x00C8 0 x0390 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_GDOE__ECSPI2_SS3 0 x00C8 0 x0390 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0 x00C8 0 x0390 0 x05F0 0 x3 0 x2
#define MX6SLL_PAD_EPDC_GDOE__GPIO2_IO00 0 x00C8 0 x0390 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_GDOE__SD2_VSELECT 0 x00C8 0 x0390 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0 x00CC 0 x0394 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_GDRL__ECSPI2_RDY 0 x00CC 0 x0394 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0 x00CC 0 x0394 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_EPDC_GDRL__GPIO2_IO01 0 x00CC 0 x0394 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_GDRL__SD2_WP 0 x00CC 0 x0394 0 x077C 0 x6 0 x2
#define MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0 x00D0 0 x0398 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_GDSP__PWM4_OUT 0 x00D0 0 x0398 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0 x00D0 0 x0398 0 x05F8 0 x3 0 x2
#define MX6SLL_PAD_EPDC_GDSP__GPIO2_IO02 0 x00D0 0 x0398 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_GDSP__SD2_CD_B 0 x00D0 0 x0398 0 x0778 0 x6 0 x2
#define MX6SLL_PAD_EPDC_VCOM0__EPDC_VCOM0 0 x00D4 0 x039C 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_VCOM0__AUD5_RXFS 0 x00D4 0 x039C 0 x0588 0 x1 0 x1
#define MX6SLL_PAD_EPDC_VCOM0__UART3_DCE_RX 0 x00D4 0 x039C 0 x0754 0 x2 0 x4
#define MX6SLL_PAD_EPDC_VCOM0__UART3_DTE_TX 0 x00D4 0 x039C 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0 x00D4 0 x039C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_VCOM0__EPDC_SDCE5 0 x00D4 0 x039C 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_EPDC_VCOM1__EPDC_VCOM1 0 x00D8 0 x03A0 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_VCOM1__AUD5_RXD 0 x00D8 0 x03A0 0 x057C 0 x1 0 x1
#define MX6SLL_PAD_EPDC_VCOM1__UART3_DCE_TX 0 x00D8 0 x03A0 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_VCOM1__UART3_DTE_RX 0 x00D8 0 x03A0 0 x0754 0 x2 0 x5
#define MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0 x00D8 0 x03A0 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_VCOM1__EPDC_SDCE6 0 x00D8 0 x03A0 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_EPDC_BDR0__EPDC_BDR0 0 x00DC 0 x03A4 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_BDR0__UART3_DCE_RTS 0 x00DC 0 x03A4 0 x0750 0 x2 0 x2
#define MX6SLL_PAD_EPDC_BDR0__UART3_DTE_CTS 0 x00DC 0 x03A4 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_BDR0__GPIO2_IO05 0 x00DC 0 x03A4 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_BDR0__EPDC_SDCE7 0 x00DC 0 x03A4 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_EPDC_BDR1__EPDC_BDR1 0 x00E0 0 x03A8 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_BDR1__UART3_DCE_CTS 0 x00E0 0 x03A8 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_EPDC_BDR1__UART3_DTE_RTS 0 x00E0 0 x03A8 0 x0750 0 x2 0 x3
#define MX6SLL_PAD_EPDC_BDR1__GPIO2_IO06 0 x00E0 0 x03A8 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_BDR1__EPDC_SDCE8 0 x00E0 0 x03A8 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 0 x00E4 0 x03AC 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_PWR_CTRL0__AUD5_RXC 0 x00E4 0 x03AC 0 x0584 0 x1 0 x1
#define MX6SLL_PAD_EPDC_PWR_CTRL0__LCD_DATA16 0 x00E4 0 x03AC 0 x0718 0 x2 0 x1
#define MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0 x00E4 0 x03AC 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 0 x00E8 0 x03B0 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_PWR_CTRL1__AUD5_TXFS 0 x00E8 0 x03B0 0 x0590 0 x1 0 x1
#define MX6SLL_PAD_EPDC_PWR_CTRL1__LCD_DATA17 0 x00E8 0 x03B0 0 x071C 0 x2 0 x1
#define MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0 x00E8 0 x03B0 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 0 x00EC 0 x03B4 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_PWR_CTRL2__AUD5_TXD 0 x00EC 0 x03B4 0 x0580 0 x1 0 x1
#define MX6SLL_PAD_EPDC_PWR_CTRL2__LCD_DATA18 0 x00EC 0 x03B4 0 x0720 0 x2 0 x1
#define MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0 x00EC 0 x03B4 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 0 x00F0 0 x03B8 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_PWR_CTRL3__AUD5_TXC 0 x00F0 0 x03B8 0 x058C 0 x1 0 x1
#define MX6SLL_PAD_EPDC_PWR_CTRL3__LCD_DATA19 0 x00F0 0 x03B8 0 x0724 0 x2 0 x1
#define MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0 x00F0 0 x03B8 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0 x00F4 0 x03BC 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_PWR_COM__LCD_DATA20 0 x00F4 0 x03BC 0 x0728 0 x2 0 x1
#define MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0 x00F4 0 x03BC 0 x055C 0 x4 0 x4
#define MX6SLL_PAD_EPDC_PWR_COM__GPIO2_IO11 0 x00F4 0 x03BC 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_PWR_COM__SD3_RESET 0 x00F4 0 x03BC 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ 0 x00F8 0 x03C0 0 x0668 0 x0 0 x1
#define MX6SLL_PAD_EPDC_PWR_IRQ__LCD_DATA21 0 x00F8 0 x03C0 0 x072C 0 x2 0 x1
#define MX6SLL_PAD_EPDC_PWR_IRQ__USB_OTG2_ID 0 x00F8 0 x03C0 0 x0560 0 x4 0 x3
#define MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0 x00F8 0 x03C0 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_PWR_IRQ__SD3_VSELECT 0 x00F8 0 x03C0 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0 x00FC 0 x03C4 0 x066C 0 x0 0 x1
#define MX6SLL_PAD_EPDC_PWR_STAT__LCD_DATA22 0 x00FC 0 x03C4 0 x0730 0 x2 0 x1
#define MX6SLL_PAD_EPDC_PWR_STAT__ARM_EVENTI 0 x00FC 0 x03C4 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0 x00FC 0 x03C4 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_PWR_STAT__SD3_WP 0 x00FC 0 x03C4 0 x0794 0 x6 0 x2
#define MX6SLL_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE 0 x0100 0 x03C8 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_EPDC_PWR_WAKE__LCD_DATA23 0 x0100 0 x03C8 0 x0734 0 x2 0 x1
#define MX6SLL_PAD_EPDC_PWR_WAKE__ARM_EVENTO 0 x0100 0 x03C8 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0 x0100 0 x03C8 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_EPDC_PWR_WAKE__SD3_CD_B 0 x0100 0 x03C8 0 x0780 0 x6 0 x2
#define MX6SLL_PAD_LCD_CLK__LCD_CLK 0 x0104 0 x03CC 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_LCD_CLK__LCD_WR_RWN 0 x0104 0 x03CC 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_LCD_CLK__PWM4_OUT 0 x0104 0 x03CC 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0 x0104 0 x03CC 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0 x0108 0 x03D0 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_LCD_ENABLE__LCD_RD_E 0 x0108 0 x03D0 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_LCD_ENABLE__UART2_DCE_RX 0 x0108 0 x03D0 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_LCD_ENABLE__UART2_DTE_TX 0 x0108 0 x03D0 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0 x0108 0 x03D0 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0 x010C 0 x03D4 0 x06D4 0 x0 0 x0
#define MX6SLL_PAD_LCD_HSYNC__LCD_CS 0 x010C 0 x03D4 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_LCD_HSYNC__UART2_DCE_TX 0 x010C 0 x03D4 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_LCD_HSYNC__UART2_DTE_RX 0 x010C 0 x03D4 0 x074C 0 x4 0 x1
#define MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0 x010C 0 x03D4 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0 x010C 0 x03D4 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0 x0110 0 x03D8 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_LCD_VSYNC__LCD_RS 0 x0110 0 x03D8 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_LCD_VSYNC__UART2_DCE_RTS 0 x0110 0 x03D8 0 x0748 0 x4 0 x0
#define MX6SLL_PAD_LCD_VSYNC__UART2_DTE_CTS 0 x0110 0 x03D8 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0 x0110 0 x03D8 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0 x0110 0 x03D8 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_LCD_RESET__LCD_RESET 0 x0114 0 x03DC 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_LCD_RESET__LCD_BUSY 0 x0114 0 x03DC 0 x06D4 0 x2 0 x1
#define MX6SLL_PAD_LCD_RESET__UART2_DCE_CTS 0 x0114 0 x03DC 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_LCD_RESET__UART2_DTE_RTS 0 x0114 0 x03DC 0 x0748 0 x4 0 x1
#define MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0 x0114 0 x03DC 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_RESET__CCM_PMIC_READY 0 x0114 0 x03DC 0 x05AC 0 x6 0 x2
#define MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0 x0118 0 x03E0 0 x06D8 0 x0 0 x1
#define MX6SLL_PAD_LCD_DATA00__ECSPI1_MOSI 0 x0118 0 x03E0 0 x0608 0 x1 0 x0
#define MX6SLL_PAD_LCD_DATA00__USB_OTG2_ID 0 x0118 0 x03E0 0 x0560 0 x2 0 x2
#define MX6SLL_PAD_LCD_DATA00__PWM1_OUT 0 x0118 0 x03E0 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_LCD_DATA00__UART5_DTR_B 0 x0118 0 x03E0 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0 x0118 0 x03E0 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA00__ARM_TRACE00 0 x0118 0 x03E0 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_LCD_DATA00__SRC_BOOT_CFG00 0 x0118 0 x03E0 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0 x011C 0 x03E4 0 x06DC 0 x0 0 x1
#define MX6SLL_PAD_LCD_DATA01__ECSPI1_MISO 0 x011C 0 x03E4 0 x0604 0 x1 0 x0
#define MX6SLL_PAD_LCD_DATA01__USB_OTG1_ID 0 x011C 0 x03E4 0 x055C 0 x2 0 x3
#define MX6SLL_PAD_LCD_DATA01__PWM2_OUT 0 x011C 0 x03E4 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_LCD_DATA01__AUD4_RXFS 0 x011C 0 x03E4 0 x0570 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0 x011C 0 x03E4 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA01__ARM_TRACE01 0 x011C 0 x03E4 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_LCD_DATA01__SRC_BOOT_CFG01 0 x011C 0 x03E4 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0 x0120 0 x03E8 0 x06E0 0 x0 0 x1
#define MX6SLL_PAD_LCD_DATA02__ECSPI1_SS0 0 x0120 0 x03E8 0 x0614 0 x1 0 x0
#define MX6SLL_PAD_LCD_DATA02__EPIT2_OUT 0 x0120 0 x03E8 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_LCD_DATA02__PWM3_OUT 0 x0120 0 x03E8 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_LCD_DATA02__AUD4_RXC 0 x0120 0 x03E8 0 x056C 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0 x0120 0 x03E8 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA02__ARM_TRACE02 0 x0120 0 x03E8 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_LCD_DATA02__SRC_BOOT_CFG02 0 x0120 0 x03E8 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0 x0124 0 x03EC 0 x06E4 0 x0 0 x1
#define MX6SLL_PAD_LCD_DATA03__ECSPI1_SCLK 0 x0124 0 x03EC 0 x05FC 0 x1 0 x0
#define MX6SLL_PAD_LCD_DATA03__UART5_DSR_B 0 x0124 0 x03EC 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_LCD_DATA03__PWM4_OUT 0 x0124 0 x03EC 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_LCD_DATA03__AUD4_RXD 0 x0124 0 x03EC 0 x0564 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0 x0124 0 x03EC 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA03__ARM_TRACE03 0 x0124 0 x03EC 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_LCD_DATA03__SRC_BOOT_CFG03 0 x0124 0 x03EC 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0 x0128 0 x03F0 0 x06E8 0 x0 0 x1
#define MX6SLL_PAD_LCD_DATA04__ECSPI1_SS1 0 x0128 0 x03F0 0 x060C 0 x1 0 x1
#define MX6SLL_PAD_LCD_DATA04__CSI_VSYNC 0 x0128 0 x03F0 0 x05F8 0 x2 0 x0
#define MX6SLL_PAD_LCD_DATA04__WDOG2_RESET_B_DEB 0 x0128 0 x03F0 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_LCD_DATA04__AUD4_TXC 0 x0128 0 x03F0 0 x0574 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0 x0128 0 x03F0 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA04__ARM_TRACE04 0 x0128 0 x03F0 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_LCD_DATA04__SRC_BOOT_CFG04 0 x0128 0 x03F0 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0 x012C 0 x03F4 0 x06EC 0 x0 0 x1
#define MX6SLL_PAD_LCD_DATA05__ECSPI1_SS2 0 x012C 0 x03F4 0 x0610 0 x1 0 x1
#define MX6SLL_PAD_LCD_DATA05__CSI_HSYNC 0 x012C 0 x03F4 0 x05F0 0 x2 0 x0
#define MX6SLL_PAD_LCD_DATA05__AUD4_TXFS 0 x012C 0 x03F4 0 x0578 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0 x012C 0 x03F4 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA05__ARM_TRACE05 0 x012C 0 x03F4 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_LCD_DATA05__SRC_BOOT_CFG05 0 x012C 0 x03F4 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0 x0130 0 x03F8 0 x06F0 0 x0 0 x1
#define MX6SLL_PAD_LCD_DATA06__ECSPI1_SS3 0 x0130 0 x03F8 0 x0618 0 x1 0 x0
#define MX6SLL_PAD_LCD_DATA06__CSI_PIXCLK 0 x0130 0 x03F8 0 x05F4 0 x2 0 x0
#define MX6SLL_PAD_LCD_DATA06__AUD4_TXD 0 x0130 0 x03F8 0 x0568 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0 x0130 0 x03F8 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA06__ARM_TRACE06 0 x0130 0 x03F8 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_LCD_DATA06__SRC_BOOT_CFG06 0 x0130 0 x03F8 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0 x0134 0 x03FC 0 x06F4 0 x0 0 x0
#define MX6SLL_PAD_LCD_DATA07__ECSPI1_RDY 0 x0134 0 x03FC 0 x0600 0 x1 0 x0
#define MX6SLL_PAD_LCD_DATA07__CSI_MCLK 0 x0134 0 x03FC 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_LCD_DATA07__AUDIO_CLK_OUT 0 x0134 0 x03FC 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0 x0134 0 x03FC 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA07__ARM_TRACE07 0 x0134 0 x03FC 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_LCD_DATA07__SRC_BOOT_CFG07 0 x0134 0 x03FC 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0 x0138 0 x0400 0 x06F8 0 x0 0 x0
#define MX6SLL_PAD_LCD_DATA08__KEY_COL0 0 x0138 0 x0400 0 x06A0 0 x1 0 x1
#define MX6SLL_PAD_LCD_DATA08__CSI_DATA09 0 x0138 0 x0400 0 x05EC 0 x2 0 x0
#define MX6SLL_PAD_LCD_DATA08__ECSPI2_SCLK 0 x0138 0 x0400 0 x061C 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0 x0138 0 x0400 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA08__ARM_TRACE08 0 x0138 0 x0400 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_LCD_DATA08__SRC_BOOT_CFG08 0 x0138 0 x0400 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0 x013C 0 x0404 0 x06FC 0 x0 0 x0
#define MX6SLL_PAD_LCD_DATA09__KEY_ROW0 0 x013C 0 x0404 0 x06C0 0 x1 0 x1
#define MX6SLL_PAD_LCD_DATA09__CSI_DATA08 0 x013C 0 x0404 0 x05E8 0 x2 0 x0
#define MX6SLL_PAD_LCD_DATA09__ECSPI2_MOSI 0 x013C 0 x0404 0 x0624 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0 x013C 0 x0404 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA09__ARM_TRACE09 0 x013C 0 x0404 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_LCD_DATA09__SRC_BOOT_CFG09 0 x013C 0 x0404 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0 x0140 0 x0408 0 x0700 0 x0 0 x1
#define MX6SLL_PAD_LCD_DATA10__KEY_COL1 0 x0140 0 x0408 0 x06A4 0 x1 0 x1
#define MX6SLL_PAD_LCD_DATA10__CSI_DATA07 0 x0140 0 x0408 0 x05E4 0 x2 0 x0
#define MX6SLL_PAD_LCD_DATA10__ECSPI2_MISO 0 x0140 0 x0408 0 x0620 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0 x0140 0 x0408 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA10__ARM_TRACE10 0 x0140 0 x0408 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_LCD_DATA10__SRC_BOOT_CFG10 0 x0140 0 x0408 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0 x0144 0 x040C 0 x0704 0 x0 0 x0
#define MX6SLL_PAD_LCD_DATA11__KEY_ROW1 0 x0144 0 x040C 0 x06C4 0 x1 0 x1
#define MX6SLL_PAD_LCD_DATA11__CSI_DATA06 0 x0144 0 x040C 0 x05E0 0 x2 0 x0
#define MX6SLL_PAD_LCD_DATA11__ECSPI2_SS1 0 x0144 0 x040C 0 x062C 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0 x0144 0 x040C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA11__ARM_TRACE11 0 x0144 0 x040C 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_LCD_DATA11__SRC_BOOT_CFG11 0 x0144 0 x040C 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0 x0148 0 x0410 0 x0708 0 x0 0 x0
#define MX6SLL_PAD_LCD_DATA12__KEY_COL2 0 x0148 0 x0410 0 x06A8 0 x1 0 x1
#define MX6SLL_PAD_LCD_DATA12__CSI_DATA05 0 x0148 0 x0410 0 x05DC 0 x2 0 x0
#define MX6SLL_PAD_LCD_DATA12__UART5_DCE_RTS 0 x0148 0 x0410 0 x0760 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA12__UART5_DTE_CTS 0 x0148 0 x0410 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0 x0148 0 x0410 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA12__ARM_TRACE12 0 x0148 0 x0410 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_LCD_DATA12__SRC_BOOT_CFG12 0 x0148 0 x0410 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0 x014C 0 x0414 0 x070C 0 x0 0 x0
#define MX6SLL_PAD_LCD_DATA13__KEY_ROW2 0 x014C 0 x0414 0 x06C8 0 x1 0 x1
#define MX6SLL_PAD_LCD_DATA13__CSI_DATA04 0 x014C 0 x0414 0 x05D8 0 x2 0 x0
#define MX6SLL_PAD_LCD_DATA13__UART5_DCE_CTS 0 x014C 0 x0414 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA13__UART5_DTE_RTS 0 x014C 0 x0414 0 x0760 0 x4 0 x1
#define MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0 x014C 0 x0414 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA13__ARM_TRACE13 0 x014C 0 x0414 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_LCD_DATA13__SRC_BOOT_CFG13 0 x014C 0 x0414 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0 x0150 0 x0418 0 x0710 0 x0 0 x0
#define MX6SLL_PAD_LCD_DATA14__KEY_COL3 0 x0150 0 x0418 0 x06AC 0 x1 0 x1
#define MX6SLL_PAD_LCD_DATA14__CSI_DATA03 0 x0150 0 x0418 0 x05D4 0 x2 0 x0
#define MX6SLL_PAD_LCD_DATA14__UART5_DCE_RX 0 x0150 0 x0418 0 x0764 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA14__UART5_DTE_TX 0 x0150 0 x0418 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0 x0150 0 x0418 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA14__ARM_TRACE14 0 x0150 0 x0418 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_LCD_DATA14__SRC_BOOT_CFG14 0 x0150 0 x0418 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0 x0154 0 x041C 0 x0714 0 x0 0 x0
#define MX6SLL_PAD_LCD_DATA15__KEY_ROW3 0 x0154 0 x041C 0 x06CC 0 x1 0 x0
#define MX6SLL_PAD_LCD_DATA15__CSI_DATA02 0 x0154 0 x041C 0 x05D0 0 x2 0 x0
#define MX6SLL_PAD_LCD_DATA15__UART5_DCE_TX 0 x0154 0 x041C 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA15__UART5_DTE_RX 0 x0154 0 x041C 0 x0764 0 x4 0 x1
#define MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0 x0154 0 x041C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA15__ARM_TRACE15 0 x0154 0 x041C 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_LCD_DATA15__SRC_BOOT_CFG15 0 x0154 0 x041C 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0 x0158 0 x0420 0 x0718 0 x0 0 x0
#define MX6SLL_PAD_LCD_DATA16__KEY_COL4 0 x0158 0 x0420 0 x06B0 0 x1 0 x0
#define MX6SLL_PAD_LCD_DATA16__CSI_DATA01 0 x0158 0 x0420 0 x05CC 0 x2 0 x0
#define MX6SLL_PAD_LCD_DATA16__I2C2_SCL 0 x0158 0 x0420 0 x0684 0 x4 0 x1
#define MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0 x0158 0 x0420 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA16__SRC_BOOT_CFG24 0 x0158 0 x0420 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0 x015C 0 x0424 0 x071C 0 x0 0 x0
#define MX6SLL_PAD_LCD_DATA17__KEY_ROW4 0 x015C 0 x0424 0 x06D0 0 x1 0 x0
#define MX6SLL_PAD_LCD_DATA17__CSI_DATA00 0 x015C 0 x0424 0 x05C8 0 x2 0 x0
#define MX6SLL_PAD_LCD_DATA17__I2C2_SDA 0 x015C 0 x0424 0 x0688 0 x4 0 x1
#define MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0 x015C 0 x0424 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA17__SRC_BOOT_CFG25 0 x015C 0 x0424 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0 x0160 0 x0428 0 x0720 0 x0 0 x0
#define MX6SLL_PAD_LCD_DATA18__KEY_COL5 0 x0160 0 x0428 0 x0694 0 x1 0 x2
#define MX6SLL_PAD_LCD_DATA18__CSI_DATA15 0 x0160 0 x0428 0 x05C4 0 x2 0 x1
#define MX6SLL_PAD_LCD_DATA18__GPT_CAPTURE1 0 x0160 0 x0428 0 x0670 0 x4 0 x1
#define MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0 x0160 0 x0428 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA18__SRC_BOOT_CFG26 0 x0160 0 x0428 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0 x0164 0 x042C 0 x0724 0 x0 0 x0
#define MX6SLL_PAD_LCD_DATA19__KEY_ROW5 0 x0164 0 x042C 0 x06B4 0 x1 0 x1
#define MX6SLL_PAD_LCD_DATA19__CSI_DATA14 0 x0164 0 x042C 0 x05C0 0 x2 0 x2
#define MX6SLL_PAD_LCD_DATA19__GPT_CAPTURE2 0 x0164 0 x042C 0 x0674 0 x4 0 x1
#define MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0 x0164 0 x042C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA19__SRC_BOOT_CFG27 0 x0164 0 x042C 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0 x0168 0 x0430 0 x0728 0 x0 0 x0
#define MX6SLL_PAD_LCD_DATA20__KEY_COL6 0 x0168 0 x0430 0 x0698 0 x1 0 x1
#define MX6SLL_PAD_LCD_DATA20__CSI_DATA13 0 x0168 0 x0430 0 x05BC 0 x2 0 x2
#define MX6SLL_PAD_LCD_DATA20__GPT_COMPARE1 0 x0168 0 x0430 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0 x0168 0 x0430 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA20__SRC_BOOT_CFG28 0 x0168 0 x0430 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0 x016C 0 x0434 0 x072C 0 x0 0 x0
#define MX6SLL_PAD_LCD_DATA21__KEY_ROW6 0 x016C 0 x0434 0 x06B8 0 x1 0 x1
#define MX6SLL_PAD_LCD_DATA21__CSI_DATA12 0 x016C 0 x0434 0 x05B8 0 x2 0 x2
#define MX6SLL_PAD_LCD_DATA21__GPT_COMPARE2 0 x016C 0 x0434 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0 x016C 0 x0434 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA21__SRC_BOOT_CFG29 0 x016C 0 x0434 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0 x0170 0 x0438 0 x0730 0 x0 0 x0
#define MX6SLL_PAD_LCD_DATA22__KEY_COL7 0 x0170 0 x0438 0 x069C 0 x1 0 x1
#define MX6SLL_PAD_LCD_DATA22__CSI_DATA11 0 x0170 0 x0438 0 x05B4 0 x2 0 x1
#define MX6SLL_PAD_LCD_DATA22__GPT_COMPARE3 0 x0170 0 x0438 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0 x0170 0 x0438 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA22__SRC_BOOT_CFG30 0 x0170 0 x0438 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0 x0174 0 x043C 0 x0734 0 x0 0 x0
#define MX6SLL_PAD_LCD_DATA23__KEY_ROW7 0 x0174 0 x043C 0 x06BC 0 x1 0 x1
#define MX6SLL_PAD_LCD_DATA23__CSI_DATA10 0 x0174 0 x043C 0 x05B0 0 x2 0 x1
#define MX6SLL_PAD_LCD_DATA23__GPT_CLKIN 0 x0174 0 x043C 0 x0678 0 x4 0 x1
#define MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0 x0174 0 x043C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_LCD_DATA23__SRC_BOOT_CFG31 0 x0174 0 x043C 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_AUD_RXFS__AUD3_RXFS 0 x0178 0 x0440 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_AUD_RXFS__I2C1_SCL 0 x0178 0 x0440 0 x067C 0 x1 0 x1
#define MX6SLL_PAD_AUD_RXFS__UART3_DCE_RX 0 x0178 0 x0440 0 x0754 0 x2 0 x0
#define MX6SLL_PAD_AUD_RXFS__UART3_DTE_TX 0 x0178 0 x0440 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0 x0178 0 x0440 0 x068C 0 x4 0 x1
#define MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 0 x0178 0 x0440 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_AUD_RXFS__ECSPI3_SS0 0 x0178 0 x0440 0 x0648 0 x6 0 x0
#define MX6SLL_PAD_AUD_RXFS__MBIST_BEND 0 x0178 0 x0440 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_AUD_RXC__AUD3_RXC 0 x017C 0 x0444 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_AUD_RXC__I2C1_SDA 0 x017C 0 x0444 0 x0680 0 x1 0 x1
#define MX6SLL_PAD_AUD_RXC__UART3_DCE_TX 0 x017C 0 x0444 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_AUD_RXC__UART3_DTE_RX 0 x017C 0 x0444 0 x0754 0 x2 0 x1
#define MX6SLL_PAD_AUD_RXC__I2C3_SDA 0 x017C 0 x0444 0 x0690 0 x4 0 x1
#define MX6SLL_PAD_AUD_RXC__GPIO1_IO01 0 x017C 0 x0444 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_AUD_RXC__ECSPI3_SS1 0 x017C 0 x0444 0 x064C 0 x6 0 x0
#define MX6SLL_PAD_AUD_RXD__AUD3_RXD 0 x0180 0 x0448 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_AUD_RXD__ECSPI3_MOSI 0 x0180 0 x0448 0 x063C 0 x1 0 x0
#define MX6SLL_PAD_AUD_RXD__UART4_DCE_RX 0 x0180 0 x0448 0 x075C 0 x2 0 x0
#define MX6SLL_PAD_AUD_RXD__UART4_DTE_TX 0 x0180 0 x0448 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_AUD_RXD__SD1_LCTL 0 x0180 0 x0448 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_AUD_RXD__GPIO1_IO02 0 x0180 0 x0448 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_AUD_TXC__AUD3_TXC 0 x0184 0 x044C 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_AUD_TXC__ECSPI3_MISO 0 x0184 0 x044C 0 x0638 0 x1 0 x0
#define MX6SLL_PAD_AUD_TXC__UART4_DCE_TX 0 x0184 0 x044C 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_AUD_TXC__UART4_DTE_RX 0 x0184 0 x044C 0 x075C 0 x2 0 x1
#define MX6SLL_PAD_AUD_TXC__SD2_LCTL 0 x0184 0 x044C 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_AUD_TXC__GPIO1_IO03 0 x0184 0 x044C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0 x0188 0 x0450 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_AUD_TXFS__PWM3_OUT 0 x0188 0 x0450 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_AUD_TXFS__UART4_DCE_RTS 0 x0188 0 x0450 0 x0758 0 x2 0 x0
#define MX6SLL_PAD_AUD_TXFS__UART4_DTE_CTS 0 x0188 0 x0450 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_AUD_TXFS__SD3_LCTL 0 x0188 0 x0450 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_AUD_TXFS__GPIO1_IO04 0 x0188 0 x0450 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_AUD_TXD__AUD3_TXD 0 x018C 0 x0454 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_AUD_TXD__ECSPI3_SCLK 0 x018C 0 x0454 0 x0630 0 x1 0 x0
#define MX6SLL_PAD_AUD_TXD__UART4_DCE_CTS 0 x018C 0 x0454 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_AUD_TXD__UART4_DTE_RTS 0 x018C 0 x0454 0 x0758 0 x2 0 x1
#define MX6SLL_PAD_AUD_TXD__GPIO1_IO05 0 x018C 0 x0454 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0 x0190 0 x0458 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_AUD_MCLK__PWM4_OUT 0 x0190 0 x0458 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_AUD_MCLK__ECSPI3_RDY 0 x0190 0 x0458 0 x0634 0 x2 0 x0
#define MX6SLL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0 x0190 0 x0458 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_AUD_MCLK__GPIO1_IO06 0 x0190 0 x0458 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0 x0190 0 x0458 0 x073C 0 x6 0 x1
#define MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0 x0194 0 x045C 0 x0744 0 x0 0 x0
#define MX6SLL_PAD_UART1_RXD__UART1_DTE_TX 0 x0194 0 x045C 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_UART1_RXD__PWM1_OUT 0 x0194 0 x045C 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_UART1_RXD__UART4_DCE_RX 0 x0194 0 x045C 0 x075C 0 x2 0 x4
#define MX6SLL_PAD_UART1_RXD__UART4_DTE_TX 0 x0194 0 x045C 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_UART1_RXD__UART5_DCE_RX 0 x0194 0 x045C 0 x0764 0 x4 0 x6
#define MX6SLL_PAD_UART1_RXD__UART5_DTE_TX 0 x0194 0 x045C 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_UART1_RXD__GPIO3_IO16 0 x0194 0 x045C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0 x0198 0 x0460 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_UART1_TXD__UART1_DTE_RX 0 x0198 0 x0460 0 x0744 0 x0 0 x1
#define MX6SLL_PAD_UART1_TXD__PWM2_OUT 0 x0198 0 x0460 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_UART1_TXD__UART4_DCE_TX 0 x0198 0 x0460 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_UART1_TXD__UART4_DTE_RX 0 x0198 0 x0460 0 x075C 0 x2 0 x5
#define MX6SLL_PAD_UART1_TXD__UART5_DCE_TX 0 x0198 0 x0460 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_UART1_TXD__UART5_DTE_RX 0 x0198 0 x0460 0 x0764 0 x4 0 x7
#define MX6SLL_PAD_UART1_TXD__GPIO3_IO17 0 x0198 0 x0460 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_UART1_TXD__UART5_DCD_B 0 x0198 0 x0460 0 x0000 0 x7 0 x0
#define MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0 x019C 0 x0464 0 x067C 0 x0 0 x0
#define MX6SLL_PAD_I2C1_SCL__UART1_DCE_RTS 0 x019C 0 x0464 0 x0740 0 x1 0 x0
#define MX6SLL_PAD_I2C1_SCL__UART1_DTE_CTS 0 x019C 0 x0464 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_I2C1_SCL__ECSPI3_SS2 0 x019C 0 x0464 0 x0640 0 x2 0 x0
#define MX6SLL_PAD_I2C1_SCL__SD3_RESET 0 x019C 0 x0464 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0 x019C 0 x0464 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_I2C1_SCL__ECSPI1_SS1 0 x019C 0 x0464 0 x060C 0 x6 0 x0
#define MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0 x01A0 0 x0468 0 x0680 0 x0 0 x0
#define MX6SLL_PAD_I2C1_SDA__UART1_DCE_CTS 0 x01A0 0 x0468 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_I2C1_SDA__UART1_DTE_RTS 0 x01A0 0 x0468 0 x0740 0 x1 0 x1
#define MX6SLL_PAD_I2C1_SDA__ECSPI3_SS3 0 x01A0 0 x0468 0 x0644 0 x2 0 x0
#define MX6SLL_PAD_I2C1_SDA__SD3_VSELECT 0 x01A0 0 x0468 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0 x01A0 0 x0468 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_I2C1_SDA__ECSPI1_SS2 0 x01A0 0 x0468 0 x0610 0 x6 0 x0
#define MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0 x01A4 0 x046C 0 x0684 0 x0 0 x3
#define MX6SLL_PAD_I2C2_SCL__AUD4_RXFS 0 x01A4 0 x046C 0 x0570 0 x1 0 x2
#define MX6SLL_PAD_I2C2_SCL__SPDIF_IN 0 x01A4 0 x046C 0 x0738 0 x2 0 x2
#define MX6SLL_PAD_I2C2_SCL__SD3_WP 0 x01A4 0 x046C 0 x0794 0 x4 0 x3
#define MX6SLL_PAD_I2C2_SCL__GPIO3_IO14 0 x01A4 0 x046C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_I2C2_SCL__ECSPI1_RDY 0 x01A4 0 x046C 0 x0600 0 x6 0 x1
#define MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0 x01A8 0 x0470 0 x0688 0 x0 0 x3
#define MX6SLL_PAD_I2C2_SDA__AUD4_RXC 0 x01A8 0 x0470 0 x056C 0 x1 0 x2
#define MX6SLL_PAD_I2C2_SDA__SPDIF_OUT 0 x01A8 0 x0470 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_I2C2_SDA__SD3_CD_B 0 x01A8 0 x0470 0 x0780 0 x4 0 x3
#define MX6SLL_PAD_I2C2_SDA__GPIO3_IO15 0 x01A8 0 x0470 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0 x01AC 0 x0474 0 x05FC 0 x0 0 x1
#define MX6SLL_PAD_ECSPI1_SCLK__AUD4_TXD 0 x01AC 0 x0474 0 x0568 0 x1 0 x1
#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0 x01AC 0 x0474 0 x0764 0 x2 0 x2
#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0 x01AC 0 x0474 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0 x01AC 0 x0474 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_ECSPI1_SCLK__SD2_RESET 0 x01AC 0 x0474 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0 x01AC 0 x0474 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0 x01AC 0 x0474 0 x0768 0 x6 0 x1
#define MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0 x01B0 0 x0478 0 x0608 0 x0 0 x1
#define MX6SLL_PAD_ECSPI1_MOSI__AUD4_TXC 0 x01B0 0 x0478 0 x0574 0 x1 0 x1
#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0 x01B0 0 x0478 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0 x01B0 0 x0478 0 x0764 0 x2 0 x3
#define MX6SLL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0 x01B0 0 x0478 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_ECSPI1_MOSI__SD2_VSELECT 0 x01B0 0 x0478 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_ECSPI1_MOSI__GPIO4_IO09 0 x01B0 0 x0478 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0 x01B4 0 x047C 0 x0604 0 x0 0 x1
#define MX6SLL_PAD_ECSPI1_MISO__AUD4_TXFS 0 x01B4 0 x047C 0 x0578 0 x1 0 x1
#define MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0 x01B4 0 x047C 0 x0760 0 x2 0 x2
#define MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0 x01B4 0 x047C 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_ECSPI1_MISO__EPDC_BDR0 0 x01B4 0 x047C 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_ECSPI1_MISO__SD2_WP 0 x01B4 0 x047C 0 x077C 0 x4 0 x0
#define MX6SLL_PAD_ECSPI1_MISO__GPIO4_IO10 0 x01B4 0 x047C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_ECSPI1_SS0__ECSPI1_SS0 0 x01B8 0 x0480 0 x0614 0 x0 0 x1
#define MX6SLL_PAD_ECSPI1_SS0__AUD4_RXD 0 x01B8 0 x0480 0 x0564 0 x1 0 x1
#define MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0 x01B8 0 x0480 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0 x01B8 0 x0480 0 x0760 0 x2 0 x3
#define MX6SLL_PAD_ECSPI1_SS0__EPDC_BDR1 0 x01B8 0 x0480 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_ECSPI1_SS0__SD2_CD_B 0 x01B8 0 x0480 0 x0778 0 x4 0 x0
#define MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0 x01B8 0 x0480 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0 x01B8 0 x0480 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0 x01BC 0 x0484 0 x061C 0 x0 0 x1
#define MX6SLL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0 x01BC 0 x0484 0 x073C 0 x1 0 x2
#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DCE_RX 0 x01BC 0 x0484 0 x0754 0 x2 0 x2
#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DTE_TX 0 x01BC 0 x0484 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0 x01BC 0 x0484 0 x05F4 0 x3 0 x1
#define MX6SLL_PAD_ECSPI2_SCLK__SD1_RESET 0 x01BC 0 x0484 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_ECSPI2_SCLK__GPIO4_IO12 0 x01BC 0 x0484 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0 x01BC 0 x0484 0 x0768 0 x6 0 x2
#define MX6SLL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0 x01C0 0 x0488 0 x0624 0 x0 0 x1
#define MX6SLL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0 x01C0 0 x0488 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DCE_TX 0 x01C0 0 x0488 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DTE_RX 0 x01C0 0 x0488 0 x0754 0 x2 0 x3
#define MX6SLL_PAD_ECSPI2_MOSI__CSI_HSYNC 0 x01C0 0 x0488 0 x05F0 0 x3 0 x1
#define MX6SLL_PAD_ECSPI2_MOSI__SD1_VSELECT 0 x01C0 0 x0488 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0 x01C0 0 x0488 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_ECSPI2_MISO__ECSPI2_MISO 0 x01C4 0 x048C 0 x0620 0 x0 0 x1
#define MX6SLL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0 x01C4 0 x048C 0 x0000 0 x1 0 x0
#define MX6SLL_PAD_ECSPI2_MISO__UART3_DCE_RTS 0 x01C4 0 x048C 0 x0750 0 x2 0 x0
#define MX6SLL_PAD_ECSPI2_MISO__UART3_DTE_CTS 0 x01C4 0 x048C 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_ECSPI2_MISO__CSI_MCLK 0 x01C4 0 x048C 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_ECSPI2_MISO__SD1_WP 0 x01C4 0 x048C 0 x0774 0 x4 0 x2
#define MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0 x01C4 0 x048C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_ECSPI2_MISO__USB_OTG1_OC 0 x01C4 0 x048C 0 x076C 0 x6 0 x1
#define MX6SLL_PAD_ECSPI2_SS0__ECSPI2_SS0 0 x01C8 0 x0490 0 x0628 0 x0 0 x0
#define MX6SLL_PAD_ECSPI2_SS0__ECSPI1_SS3 0 x01C8 0 x0490 0 x0618 0 x1 0 x1
#define MX6SLL_PAD_ECSPI2_SS0__UART3_DCE_CTS 0 x01C8 0 x0490 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_ECSPI2_SS0__UART3_DTE_RTS 0 x01C8 0 x0490 0 x0750 0 x2 0 x1
#define MX6SLL_PAD_ECSPI2_SS0__CSI_VSYNC 0 x01C8 0 x0490 0 x05F8 0 x3 0 x1
#define MX6SLL_PAD_ECSPI2_SS0__SD1_CD_B 0 x01C8 0 x0490 0 x0770 0 x4 0 x2
#define MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0 x01C8 0 x0490 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0 x01C8 0 x0490 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_SD1_CLK__SD1_CLK 0 x01CC 0 x0494 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD1_CLK__KEY_COL0 0 x01CC 0 x0494 0 x06A0 0 x2 0 x2
#define MX6SLL_PAD_SD1_CLK__EPDC_SDCE4 0 x01CC 0 x0494 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0 x01CC 0 x0494 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD1_CMD__SD1_CMD 0 x01D0 0 x0498 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD1_CMD__KEY_ROW0 0 x01D0 0 x0498 0 x06C0 0 x2 0 x2
#define MX6SLL_PAD_SD1_CMD__EPDC_SDCE5 0 x01D0 0 x0498 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_SD1_CMD__GPIO5_IO14 0 x01D0 0 x0498 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0 x01D4 0 x049C 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD1_DATA0__KEY_COL1 0 x01D4 0 x049C 0 x06A4 0 x2 0 x2
#define MX6SLL_PAD_SD1_DATA0__EPDC_SDCE6 0 x01D4 0 x049C 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0 x01D4 0 x049C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0 x01D8 0 x04A0 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD1_DATA1__KEY_ROW1 0 x01D8 0 x04A0 0 x06C4 0 x2 0 x2
#define MX6SLL_PAD_SD1_DATA1__EPDC_SDCE7 0 x01D8 0 x04A0 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0 x01D8 0 x04A0 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0 x01DC 0 x04A4 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD1_DATA2__KEY_COL2 0 x01DC 0 x04A4 0 x06A8 0 x2 0 x2
#define MX6SLL_PAD_SD1_DATA2__EPDC_SDCE8 0 x01DC 0 x04A4 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0 x01DC 0 x04A4 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0 x01E0 0 x04A8 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD1_DATA3__KEY_ROW2 0 x01E0 0 x04A8 0 x06C8 0 x2 0 x2
#define MX6SLL_PAD_SD1_DATA3__EPDC_SDCE9 0 x01E0 0 x04A8 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0 x01E0 0 x04A8 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0 x01E4 0 x04AC 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD1_DATA4__KEY_COL3 0 x01E4 0 x04AC 0 x06AC 0 x2 0 x2
#define MX6SLL_PAD_SD1_DATA4__EPDC_SDCLK_N 0 x01E4 0 x04AC 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_SD1_DATA4__UART4_DCE_RX 0 x01E4 0 x04AC 0 x075C 0 x4 0 x6
#define MX6SLL_PAD_SD1_DATA4__UART4_DTE_TX 0 x01E4 0 x04AC 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0 x01E4 0 x04AC 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0 x01E8 0 x04B0 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD1_DATA5__KEY_ROW3 0 x01E8 0 x04B0 0 x06CC 0 x2 0 x2
#define MX6SLL_PAD_SD1_DATA5__EPDC_SDOED 0 x01E8 0 x04B0 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_SD1_DATA5__UART4_DCE_TX 0 x01E8 0 x04B0 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_SD1_DATA5__UART4_DTE_RX 0 x01E8 0 x04B0 0 x075C 0 x4 0 x7
#define MX6SLL_PAD_SD1_DATA5__GPIO5_IO09 0 x01E8 0 x04B0 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0 x01EC 0 x04B4 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD1_DATA6__KEY_COL4 0 x01EC 0 x04B4 0 x06B0 0 x2 0 x2
#define MX6SLL_PAD_SD1_DATA6__EPDC_SDOEZ 0 x01EC 0 x04B4 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_SD1_DATA6__UART4_DCE_RTS 0 x01EC 0 x04B4 0 x0758 0 x4 0 x4
#define MX6SLL_PAD_SD1_DATA6__UART4_DTE_CTS 0 x01EC 0 x04B4 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0 x01EC 0 x04B4 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0 x01F0 0 x04B8 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD1_DATA7__KEY_ROW4 0 x01F0 0 x04B8 0 x06D0 0 x2 0 x2
#define MX6SLL_PAD_SD1_DATA7__CCM_PMIC_READY 0 x01F0 0 x04B8 0 x05AC 0 x3 0 x3
#define MX6SLL_PAD_SD1_DATA7__UART4_DCE_CTS 0 x01F0 0 x04B8 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_SD1_DATA7__UART4_DTE_RTS 0 x01F0 0 x04B8 0 x0758 0 x4 0 x5
#define MX6SLL_PAD_SD1_DATA7__GPIO5_IO10 0 x01F0 0 x04B8 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD2_RESET__SD2_RESET 0 x01F4 0 x04BC 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD2_RESET__WDOG2_B 0 x01F4 0 x04BC 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0 x01F4 0 x04BC 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_SD2_RESET__CSI_MCLK 0 x01F4 0 x04BC 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0 x01F4 0 x04BC 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD2_CLK__SD2_CLK 0 x01F8 0 x04C0 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD2_CLK__AUD4_RXFS 0 x01F8 0 x04C0 0 x0570 0 x1 0 x1
#define MX6SLL_PAD_SD2_CLK__ECSPI3_SCLK 0 x01F8 0 x04C0 0 x0630 0 x2 0 x1
#define MX6SLL_PAD_SD2_CLK__CSI_DATA00 0 x01F8 0 x04C0 0 x05C8 0 x3 0 x1
#define MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0 x01F8 0 x04C0 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD2_CMD__SD2_CMD 0 x01FC 0 x04C4 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD2_CMD__AUD4_RXC 0 x01FC 0 x04C4 0 x056C 0 x1 0 x1
#define MX6SLL_PAD_SD2_CMD__ECSPI3_SS0 0 x01FC 0 x04C4 0 x0648 0 x2 0 x1
#define MX6SLL_PAD_SD2_CMD__CSI_DATA01 0 x01FC 0 x04C4 0 x05CC 0 x3 0 x1
#define MX6SLL_PAD_SD2_CMD__EPIT1_OUT 0 x01FC 0 x04C4 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0 x01FC 0 x04C4 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0 x0200 0 x04C8 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD2_DATA0__AUD4_RXD 0 x0200 0 x04C8 0 x0564 0 x1 0 x2
#define MX6SLL_PAD_SD2_DATA0__ECSPI3_MOSI 0 x0200 0 x04C8 0 x063C 0 x2 0 x1
#define MX6SLL_PAD_SD2_DATA0__CSI_DATA02 0 x0200 0 x04C8 0 x05D0 0 x3 0 x1
#define MX6SLL_PAD_SD2_DATA0__UART5_DCE_RTS 0 x0200 0 x04C8 0 x0760 0 x4 0 x4
#define MX6SLL_PAD_SD2_DATA0__UART5_DTE_CTS 0 x0200 0 x04C8 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0 x0200 0 x04C8 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0 x0204 0 x04CC 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD2_DATA1__AUD4_TXC 0 x0204 0 x04CC 0 x0574 0 x1 0 x2
#define MX6SLL_PAD_SD2_DATA1__ECSPI3_MISO 0 x0204 0 x04CC 0 x0638 0 x2 0 x1
#define MX6SLL_PAD_SD2_DATA1__CSI_DATA03 0 x0204 0 x04CC 0 x05D4 0 x3 0 x1
#define MX6SLL_PAD_SD2_DATA1__UART5_DCE_CTS 0 x0204 0 x04CC 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_SD2_DATA1__UART5_DTE_RTS 0 x0204 0 x04CC 0 x0760 0 x4 0 x5
#define MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0 x0204 0 x04CC 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0 x0208 0 x04D0 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD2_DATA2__AUD4_TXFS 0 x0208 0 x04D0 0 x0578 0 x1 0 x2
#define MX6SLL_PAD_SD2_DATA2__CSI_DATA04 0 x0208 0 x04D0 0 x05D8 0 x3 0 x1
#define MX6SLL_PAD_SD2_DATA2__UART5_DCE_RX 0 x0208 0 x04D0 0 x0764 0 x4 0 x4
#define MX6SLL_PAD_SD2_DATA2__UART5_DTE_TX 0 x0208 0 x04D0 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0 x0208 0 x04D0 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0 x020C 0 x04D4 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD2_DATA3__AUD4_TXD 0 x020C 0 x04D4 0 x0568 0 x1 0 x2
#define MX6SLL_PAD_SD2_DATA3__CSI_DATA05 0 x020C 0 x04D4 0 x05DC 0 x3 0 x1
#define MX6SLL_PAD_SD2_DATA3__UART5_DCE_TX 0 x020C 0 x04D4 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_SD2_DATA3__UART5_DTE_RX 0 x020C 0 x04D4 0 x0764 0 x4 0 x5
#define MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0 x020C 0 x04D4 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0 x0210 0 x04D8 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD2_DATA4__SD3_DATA4 0 x0210 0 x04D8 0 x0784 0 x1 0 x1
#define MX6SLL_PAD_SD2_DATA4__UART2_DCE_RX 0 x0210 0 x04D8 0 x074C 0 x2 0 x2
#define MX6SLL_PAD_SD2_DATA4__UART2_DTE_TX 0 x0210 0 x04D8 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_SD2_DATA4__CSI_DATA06 0 x0210 0 x04D8 0 x05E0 0 x3 0 x1
#define MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0 x0210 0 x04D8 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_SD2_DATA4__GPIO5_IO02 0 x0210 0 x04D8 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0 x0214 0 x04DC 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD2_DATA5__SD3_DATA5 0 x0214 0 x04DC 0 x0788 0 x1 0 x1
#define MX6SLL_PAD_SD2_DATA5__UART2_DCE_TX 0 x0214 0 x04DC 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_SD2_DATA5__UART2_DTE_RX 0 x0214 0 x04DC 0 x074C 0 x2 0 x3
#define MX6SLL_PAD_SD2_DATA5__CSI_DATA07 0 x0214 0 x04DC 0 x05E4 0 x3 0 x1
#define MX6SLL_PAD_SD2_DATA5__SPDIF_IN 0 x0214 0 x04DC 0 x0738 0 x4 0 x1
#define MX6SLL_PAD_SD2_DATA5__GPIO4_IO31 0 x0214 0 x04DC 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0 x0218 0 x04E0 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD2_DATA6__SD3_DATA6 0 x0218 0 x04E0 0 x078C 0 x1 0 x1
#define MX6SLL_PAD_SD2_DATA6__UART2_DCE_RTS 0 x0218 0 x04E0 0 x0748 0 x2 0 x2
#define MX6SLL_PAD_SD2_DATA6__UART2_DTE_CTS 0 x0218 0 x04E0 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_SD2_DATA6__CSI_DATA08 0 x0218 0 x04E0 0 x05E8 0 x3 0 x1
#define MX6SLL_PAD_SD2_DATA6__SD2_WP 0 x0218 0 x04E0 0 x077C 0 x4 0 x1
#define MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0 x0218 0 x04E0 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0 x021C 0 x04E4 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD2_DATA7__SD3_DATA7 0 x021C 0 x04E4 0 x0790 0 x1 0 x1
#define MX6SLL_PAD_SD2_DATA7__UART2_DCE_CTS 0 x021C 0 x04E4 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_SD2_DATA7__UART2_DTE_RTS 0 x021C 0 x04E4 0 x0748 0 x2 0 x3
#define MX6SLL_PAD_SD2_DATA7__CSI_DATA09 0 x021C 0 x04E4 0 x05EC 0 x3 0 x1
#define MX6SLL_PAD_SD2_DATA7__SD2_CD_B 0 x021C 0 x04E4 0 x0778 0 x4 0 x1
#define MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0 x021C 0 x04E4 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD3_CLK__SD3_CLK 0 x0220 0 x04E8 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD3_CLK__AUD5_RXFS 0 x0220 0 x04E8 0 x0588 0 x1 0 x0
#define MX6SLL_PAD_SD3_CLK__KEY_COL5 0 x0220 0 x04E8 0 x0694 0 x2 0 x0
#define MX6SLL_PAD_SD3_CLK__CSI_DATA10 0 x0220 0 x04E8 0 x05B0 0 x3 0 x0
#define MX6SLL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0 x0220 0 x04E8 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0 x0220 0 x04E8 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD3_CLK__USB_OTG1_PWR 0 x0220 0 x04E8 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_SD3_CMD__SD3_CMD 0 x0224 0 x04EC 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD3_CMD__AUD5_RXC 0 x0224 0 x04EC 0 x0584 0 x1 0 x0
#define MX6SLL_PAD_SD3_CMD__KEY_ROW5 0 x0224 0 x04EC 0 x06B4 0 x2 0 x0
#define MX6SLL_PAD_SD3_CMD__CSI_DATA11 0 x0224 0 x04EC 0 x05B4 0 x3 0 x0
#define MX6SLL_PAD_SD3_CMD__USB_OTG2_ID 0 x0224 0 x04EC 0 x0560 0 x4 0 x1
#define MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0 x0224 0 x04EC 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD3_CMD__USB_OTG2_PWR 0 x0224 0 x04EC 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0 x0228 0 x04F0 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD3_DATA0__AUD5_RXD 0 x0228 0 x04F0 0 x057C 0 x1 0 x0
#define MX6SLL_PAD_SD3_DATA0__KEY_COL6 0 x0228 0 x04F0 0 x0698 0 x2 0 x0
#define MX6SLL_PAD_SD3_DATA0__CSI_DATA12 0 x0228 0 x04F0 0 x05B8 0 x3 0 x0
#define MX6SLL_PAD_SD3_DATA0__USB_OTG1_ID 0 x0228 0 x04F0 0 x055C 0 x4 0 x1
#define MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0 x0228 0 x04F0 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0 x022C 0 x04F4 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD3_DATA1__AUD5_TXC 0 x022C 0 x04F4 0 x058C 0 x1 0 x0
#define MX6SLL_PAD_SD3_DATA1__KEY_ROW6 0 x022C 0 x04F4 0 x06B8 0 x2 0 x0
#define MX6SLL_PAD_SD3_DATA1__CSI_DATA13 0 x022C 0 x04F4 0 x05BC 0 x3 0 x0
#define MX6SLL_PAD_SD3_DATA1__SD1_VSELECT 0 x022C 0 x04F4 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0 x022C 0 x04F4 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD3_DATA1__JTAG_DE_B 0 x022C 0 x04F4 0 x0000 0 x6 0 x0
#define MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0 x0230 0 x04F8 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD3_DATA2__AUD5_TXFS 0 x0230 0 x04F8 0 x0590 0 x1 0 x0
#define MX6SLL_PAD_SD3_DATA2__KEY_COL7 0 x0230 0 x04F8 0 x069C 0 x2 0 x0
#define MX6SLL_PAD_SD3_DATA2__CSI_DATA14 0 x0230 0 x04F8 0 x05C0 0 x3 0 x0
#define MX6SLL_PAD_SD3_DATA2__EPIT1_OUT 0 x0230 0 x04F8 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0 x0230 0 x04F8 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD3_DATA2__USB_OTG2_OC 0 x0230 0 x04F8 0 x0768 0 x6 0 x0
#define MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0 x0234 0 x04FC 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_SD3_DATA3__AUD5_TXD 0 x0234 0 x04FC 0 x0580 0 x1 0 x0
#define MX6SLL_PAD_SD3_DATA3__KEY_ROW7 0 x0234 0 x04FC 0 x06BC 0 x2 0 x0
#define MX6SLL_PAD_SD3_DATA3__CSI_DATA15 0 x0234 0 x04FC 0 x05C4 0 x3 0 x0
#define MX6SLL_PAD_SD3_DATA3__EPIT2_OUT 0 x0234 0 x04FC 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0 x0234 0 x04FC 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_SD3_DATA3__USB_OTG1_OC 0 x0234 0 x04FC 0 x076C 0 x6 0 x0
#define MX6SLL_PAD_GPIO4_IO20__SD1_STROBE 0 x0238 0 x0500 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_GPIO4_IO20__AUD6_RXFS 0 x0238 0 x0500 0 x05A0 0 x2 0 x0
#define MX6SLL_PAD_GPIO4_IO20__ECSPI4_SS0 0 x0238 0 x0500 0 x065C 0 x3 0 x0
#define MX6SLL_PAD_GPIO4_IO20__GPT_CAPTURE1 0 x0238 0 x0500 0 x0670 0 x4 0 x0
#define MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0 x0238 0 x0500 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0 x023C 0 x0504 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_GPIO4_IO21__AUD6_RXC 0 x023C 0 x0504 0 x059C 0 x2 0 x0
#define MX6SLL_PAD_GPIO4_IO21__ECSPI4_SCLK 0 x023C 0 x0504 0 x0650 0 x3 0 x0
#define MX6SLL_PAD_GPIO4_IO21__GPT_CAPTURE2 0 x023C 0 x0504 0 x0674 0 x4 0 x0
#define MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0 x023C 0 x0504 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_GPIO4_IO19__SD3_STROBE 0 x0240 0 x0508 0 x0000 0 x0 0 x0
#define MX6SLL_PAD_GPIO4_IO19__AUD6_RXD 0 x0240 0 x0508 0 x0594 0 x2 0 x0
#define MX6SLL_PAD_GPIO4_IO19__ECSPI4_MOSI 0 x0240 0 x0508 0 x0658 0 x3 0 x0
#define MX6SLL_PAD_GPIO4_IO19__GPT_COMPARE1 0 x0240 0 x0508 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0 x0240 0 x0508 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_GPIO4_IO25__AUD6_TXC 0 x0244 0 x050C 0 x05A4 0 x2 0 x0
#define MX6SLL_PAD_GPIO4_IO25__ECSPI4_MISO 0 x0244 0 x050C 0 x0654 0 x3 0 x0
#define MX6SLL_PAD_GPIO4_IO25__GPT_COMPARE2 0 x0244 0 x050C 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0 x0244 0 x050C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_GPIO4_IO18__AUD6_TXFS 0 x0248 0 x0510 0 x05A8 0 x2 0 x0
#define MX6SLL_PAD_GPIO4_IO18__ECSPI4_SS1 0 x0248 0 x0510 0 x0660 0 x3 0 x0
#define MX6SLL_PAD_GPIO4_IO18__GPT_COMPARE3 0 x0248 0 x0510 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0 x0248 0 x0510 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_GPIO4_IO24__AUD6_TXD 0 x024C 0 x0514 0 x0598 0 x2 0 x0
#define MX6SLL_PAD_GPIO4_IO24__ECSPI4_SS2 0 x024C 0 x0514 0 x0664 0 x3 0 x0
#define MX6SLL_PAD_GPIO4_IO24__GPT_CLKIN 0 x024C 0 x0514 0 x0678 0 x4 0 x0
#define MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0 x024C 0 x0514 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_GPIO4_IO23__AUDIO_CLK_OUT 0 x0250 0 x0518 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_GPIO4_IO23__SD1_RESET 0 x0250 0 x0518 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_GPIO4_IO23__SD3_RESET 0 x0250 0 x0518 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0 x0250 0 x0518 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_GPIO4_IO17__USB_OTG1_ID 0 x0254 0 x051C 0 x055C 0 x2 0 x2
#define MX6SLL_PAD_GPIO4_IO17__SD1_VSELECT 0 x0254 0 x051C 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_GPIO4_IO17__SD3_VSELECT 0 x0254 0 x051C 0 x0000 0 x4 0 x0
#define MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0 x0254 0 x051C 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_GPIO4_IO22__SPDIF_IN 0 x0258 0 x0520 0 x0738 0 x2 0 x0
#define MX6SLL_PAD_GPIO4_IO22__SD1_WP 0 x0258 0 x0520 0 x0774 0 x3 0 x0
#define MX6SLL_PAD_GPIO4_IO22__SD3_WP 0 x0258 0 x0520 0 x0794 0 x4 0 x1
#define MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0 x0258 0 x0520 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_GPIO4_IO16__SPDIF_OUT 0 x025C 0 x0524 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_GPIO4_IO16__SD1_CD_B 0 x025C 0 x0524 0 x0770 0 x3 0 x0
#define MX6SLL_PAD_GPIO4_IO16__SD3_CD_B 0 x025C 0 x0524 0 x0780 0 x4 0 x1
#define MX6SLL_PAD_GPIO4_IO16__GPIO4_IO16 0 x025C 0 x0524 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_GPIO4_IO26__WDOG1_B 0 x0260 0 x0528 0 x0000 0 x2 0 x0
#define MX6SLL_PAD_GPIO4_IO26__PWM4_OUT 0 x0260 0 x0528 0 x0000 0 x3 0 x0
#define MX6SLL_PAD_GPIO4_IO26__CCM_PMIC_READY 0 x0260 0 x0528 0 x05AC 0 x4 0 x1
#define MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0 x0260 0 x0528 0 x0000 0 x5 0 x0
#define MX6SLL_PAD_GPIO4_IO26__SPDIF_EXT_CLK 0 x0260 0 x0528 0 x073C 0 x6 0 x0
#endif /* __DTS_IMX6SLL_PINFUNC_H */
Messung V0.5 in Prozent C=96 H=94 G=94
¤ Dauer der Verarbeitung: 0.31 Sekunden
(vorverarbeitet am 2026-06-08)
¤
*© Formatika GbR, Deutschland