/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#ifndef __DTS_IMX6DL_PINFUNC_H
#define __DTS_IMX6DL_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0 x04c 0 x360 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0 x04c 0 x360 0 x000 0 x1 0 x0
#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0 x04c 0 x360 0 x7f8 0 x2 0 x0
#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0 x04c 0 x360 0 x000 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0 x04c 0 x360 0 x8fc 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0 x04c 0 x360 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0 x04c 0 x360 0 x000 0 x7 0 x0
#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0 x050 0 x364 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0 x050 0 x364 0 x000 0 x1 0 x0
#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0 x050 0 x364 0 x800 0 x2 0 x0
#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0 x050 0 x364 0 x8fc 0 x3 0 x1
#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0 x050 0 x364 0 x000 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0 x050 0 x364 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0 x050 0 x364 0 x000 0 x7 0 x0
#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0 x054 0 x368 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0 x054 0 x368 0 x000 0 x1 0 x0
#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0 x054 0 x368 0 x000 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0 x054 0 x368 0 x914 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0 x054 0 x368 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0 x054 0 x368 0 x000 0 x7 0 x0
#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0 x058 0 x36c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0 x058 0 x36c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0 x058 0 x36c 0 x914 0 x3 0 x1
#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0 x058 0 x36c 0 x000 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0 x058 0 x36c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0 x058 0 x36c 0 x000 0 x7 0 x0
#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0 x05c 0 x370 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0 x05c 0 x370 0 x000 0 x1 0 x0
#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0 x05c 0 x370 0 x000 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0 x05c 0 x370 0 x91c 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0 x05c 0 x370 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0 x05c 0 x370 0 x000 0 x7 0 x0
#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0 x060 0 x374 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0 x060 0 x374 0 x000 0 x1 0 x0
#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0 x060 0 x374 0 x91c 0 x3 0 x1
#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0 x060 0 x374 0 x000 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0 x060 0 x374 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0 x060 0 x374 0 x000 0 x7 0 x0
#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0 x064 0 x378 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0 x064 0 x378 0 x000 0 x1 0 x0
#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0 x064 0 x378 0 x910 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0 x064 0 x378 0 x000 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0 x064 0 x378 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0 x064 0 x378 0 x000 0 x7 0 x0
#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0 x068 0 x37c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0 x068 0 x37c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0 x068 0 x37c 0 x000 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0 x068 0 x37c 0 x910 0 x3 0 x1
#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0 x068 0 x37c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0 x068 0 x37c 0 x000 0 x7 0 x0
#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0 x06c 0 x380 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0 x06c 0 x380 0 x000 0 x1 0 x0
#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0 x06c 0 x380 0 x918 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0 x06c 0 x380 0 x000 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0 x06c 0 x380 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0 x06c 0 x380 0 x000 0 x7 0 x0
#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0 x070 0 x384 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0 x070 0 x384 0 x000 0 x1 0 x0
#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0 x070 0 x384 0 x000 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0 x070 0 x384 0 x918 0 x3 0 x1
#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0 x070 0 x384 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0 x074 0 x388 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0 x074 0 x388 0 x000 0 x1 0 x0
#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0 x074 0 x388 0 x7d8 0 x2 0 x0
#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0 x074 0 x388 0 x8c0 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0 x074 0 x388 0 x000 0 x4 0 x0
#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0 x074 0 x388 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0 x074 0 x388 0 x000 0 x7 0 x0
#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0 x078 0 x38c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0 x078 0 x38c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0 x078 0 x38c 0 x7e0 0 x2 0 x0
#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0 x078 0 x38c 0 x8cc 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0 x078 0 x38c 0 x000 0 x4 0 x0
#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0 x078 0 x38c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0 x078 0 x38c 0 x000 0 x7 0 x0
#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0 x07c 0 x390 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0 x07c 0 x390 0 x000 0 x1 0 x0
#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0 x07c 0 x390 0 x7dc 0 x2 0 x0
#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0 x07c 0 x390 0 x8c4 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0 x07c 0 x390 0 x000 0 x4 0 x0
#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0 x07c 0 x390 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0 x07c 0 x390 0 x000 0 x7 0 x0
#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0 x080 0 x394 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0 x080 0 x394 0 x000 0 x1 0 x0
#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0 x080 0 x394 0 x7e4 0 x2 0 x0
#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0 x080 0 x394 0 x8d0 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0 x080 0 x394 0 x000 0 x4 0 x0
#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0 x080 0 x394 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0 x080 0 x394 0 x000 0 x7 0 x0
#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0 x084 0 x398 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0 x084 0 x398 0 x000 0 x1 0 x0
#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0 x084 0 x398 0 x7f4 0 x2 0 x0
#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0 x084 0 x398 0 x8c8 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0 x084 0 x398 0 x86c 0 x4 0 x0
#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0 x084 0 x398 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0 x084 0 x398 0 x000 0 x7 0 x0
#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0 x088 0 x39c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0 x088 0 x39c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0 x088 0 x39c 0 x7fc 0 x2 0 x0
#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0 x088 0 x39c 0 x8d4 0 x3 0 x0
#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0 x088 0 x39c 0 x868 0 x4 0 x0
#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0 x088 0 x39c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0 x088 0 x39c 0 x000 0 x7 0 x0
#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0 x08c 0 x3a0 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0 x08c 0 x3a0 0 x000 0 x1 0 x0
#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0 x08c 0 x3a0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0 x08c 0 x3a0 0 x000 0 x7 0 x0
#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0 x090 0 x3a4 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0 x090 0 x3a4 0 x000 0 x3 0 x0
#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0 x090 0 x3a4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0 x090 0 x3a4 0 x000 0 x7 0 x0
#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0 x094 0 x3a8 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0 x094 0 x3a8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0 x094 0 x3a8 0 x000 0 x7 0 x0
#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0 x098 0 x3ac 0 x000 0 x0 0 x0
#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0 x098 0 x3ac 0 x000 0 x1 0 x0
#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0 x098 0 x3ac 0 x000 0 x5 0 x0
#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0 x098 0 x3ac 0 x000 0 x7 0 x0
#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0 x09c 0 x3b0 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DI0_DISP_CLK__LCD_CLK 0 x09c 0 x3b0 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0 x09c 0 x3b0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0 x09c 0 x3b0 0 x000 0 x8 0 x0
#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0 x0a0 0 x3b4 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DI0_PIN15__LCD_ENABLE 0 x0a0 0 x3b4 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0 x0a0 0 x3b4 0 x000 0 x2 0 x0
#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0 x0a0 0 x3b4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DI0_PIN15__LCD_RD_E 0 x0a0 0 x3b4 0 x000 0 x8 0 x0
#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0 x0a4 0 x3b8 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DI0_PIN2__LCD_HSYNC 0 x0a4 0 x3b8 0 x8d8 0 x1 0 x0
#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0 x0a4 0 x3b8 0 x000 0 x2 0 x0
#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0 x0a4 0 x3b8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DI0_PIN2__LCD_RS 0 x0a4 0 x3b8 0 x000 0 x8 0 x0
#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0 x0a8 0 x3bc 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DI0_PIN3__LCD_VSYNC 0 x0a8 0 x3bc 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0 x0a8 0 x3bc 0 x000 0 x2 0 x0
#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0 x0a8 0 x3bc 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DI0_PIN3__LCD_CS 0 x0a8 0 x3bc 0 x000 0 x8 0 x0
#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0 x0ac 0 x3c0 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DI0_PIN4__LCD_BUSY 0 x0ac 0 x3c0 0 x8d8 0 x1 0 x1
#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0 x0ac 0 x3c0 0 x000 0 x2 0 x0
#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0 x0ac 0 x3c0 0 x92c 0 x3 0 x0
#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0 x0ac 0 x3c0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DI0_PIN4__LCD_RESET 0 x0ac 0 x3c0 0 x000 0 x8 0 x0
#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0 x0b0 0 x3c4 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT0__LCD_DATA00 0 x0b0 0 x3c4 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0 x0b0 0 x3c4 0 x000 0 x2 0 x0
#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0 x0b0 0 x3c4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0 x0b4 0 x3c8 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT1__LCD_DATA01 0 x0b4 0 x3c8 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0 x0b4 0 x3c8 0 x000 0 x2 0 x0
#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0 x0b4 0 x3c8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0 x0b8 0 x3cc 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT10__LCD_DATA10 0 x0b8 0 x3cc 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0 x0b8 0 x3cc 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0 x0bc 0 x3d0 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT11__LCD_DATA11 0 x0bc 0 x3d0 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0 x0bc 0 x3d0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0 x0c0 0 x3d4 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT12__LCD_DATA12 0 x0c0 0 x3d4 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0 x0c0 0 x3d4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0 x0c4 0 x3d8 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT13__LCD_DATA13 0 x0c4 0 x3d8 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0 x0c4 0 x3d8 0 x7bc 0 x3 0 x0
#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0 x0c4 0 x3d8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0 x0c8 0 x3dc 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT14__LCD_DATA14 0 x0c8 0 x3dc 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0 x0c8 0 x3dc 0 x7b8 0 x3 0 x0
#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0 x0c8 0 x3dc 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0 x0cc 0 x3e0 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT15__LCD_DATA15 0 x0cc 0 x3e0 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0 x0cc 0 x3e0 0 x7e8 0 x2 0 x0
#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0 x0cc 0 x3e0 0 x804 0 x3 0 x0
#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0 x0cc 0 x3e0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0 x0d0 0 x3e4 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT16__LCD_DATA16 0 x0d0 0 x3e4 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0 x0d0 0 x3e4 0 x7fc 0 x2 0 x1
#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0 x0d0 0 x3e4 0 x7c0 0 x3 0 x0
#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0 x0d0 0 x3e4 0 x8e8 0 x4 0 x0
#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0 x0d0 0 x3e4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0 x0d4 0 x3e8 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT17__LCD_DATA17 0 x0d4 0 x3e8 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0 x0d4 0 x3e8 0 x7f8 0 x2 0 x1
#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0 x0d4 0 x3e8 0 x7b4 0 x3 0 x0
#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0 x0d4 0 x3e8 0 x8ec 0 x4 0 x0
#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0 x0d4 0 x3e8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0 x0d8 0 x3ec 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT18__LCD_DATA18 0 x0d8 0 x3ec 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0 x0d8 0 x3ec 0 x800 0 x2 0 x1
#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0 x0d8 0 x3ec 0 x7c4 0 x3 0 x0
#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0 x0d8 0 x3ec 0 x7a4 0 x4 0 x0
#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0 x0d8 0 x3ec 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0 x0d8 0 x3ec 0 x000 0 x7 0 x0
#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0 x0dc 0 x3f0 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT19__LCD_DATA19 0 x0dc 0 x3f0 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0 x0dc 0 x3f0 0 x7f4 0 x2 0 x1
#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0 x0dc 0 x3f0 0 x7b0 0 x3 0 x0
#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0 x0dc 0 x3f0 0 x7a0 0 x4 0 x0
#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0 x0dc 0 x3f0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0 x0dc 0 x3f0 0 x000 0 x7 0 x0
#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0 x0e0 0 x3f4 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT2__LCD_DATA02 0 x0e0 0 x3f4 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0 x0e0 0 x3f4 0 x000 0 x2 0 x0
#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0 x0e0 0 x3f4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0 x0e4 0 x3f8 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT20__LCD_DATA20 0 x0e4 0 x3f8 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0 x0e4 0 x3f8 0 x7d8 0 x2 0 x1
#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0 x0e4 0 x3f8 0 x7a8 0 x3 0 x0
#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0 x0e4 0 x3f8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0 x0e8 0 x3fc 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT21__LCD_DATA21 0 x0e8 0 x3fc 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0 x0e8 0 x3fc 0 x7e0 0 x2 0 x1
#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0 x0e8 0 x3fc 0 x79c 0 x3 0 x0
#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0 x0e8 0 x3fc 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0 x0ec 0 x400 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT22__LCD_DATA22 0 x0ec 0 x400 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0 x0ec 0 x400 0 x7dc 0 x2 0 x1
#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0 x0ec 0 x400 0 x7ac 0 x3 0 x0
#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0 x0ec 0 x400 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0 x0f0 0 x404 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT23__LCD_DATA23 0 x0f0 0 x404 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0 x0f0 0 x404 0 x7e4 0 x2 0 x1
#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0 x0f0 0 x404 0 x798 0 x3 0 x0
#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0 x0f0 0 x404 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0 x0f4 0 x408 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT3__LCD_DATA03 0 x0f4 0 x408 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0 x0f4 0 x408 0 x000 0 x2 0 x0
#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0 x0f4 0 x408 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0 x0f8 0 x40c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT4__LCD_DATA04 0 x0f8 0 x40c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0 x0f8 0 x40c 0 x000 0 x2 0 x0
#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0 x0f8 0 x40c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0 x0fc 0 x410 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT5__LCD_DATA05 0 x0fc 0 x410 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0 x0fc 0 x410 0 x000 0 x2 0 x0
#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0 x0fc 0 x410 0 x000 0 x3 0 x0
#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0 x0fc 0 x410 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0 x100 0 x414 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT6__LCD_DATA06 0 x100 0 x414 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0 x100 0 x414 0 x000 0 x2 0 x0
#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0 x100 0 x414 0 x000 0 x3 0 x0
#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0 x100 0 x414 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0 x104 0 x418 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT7__LCD_DATA07 0 x104 0 x418 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0 x104 0 x418 0 x000 0 x2 0 x0
#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0 x104 0 x418 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0 x108 0 x41c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT8__LCD_DATA08 0 x108 0 x41c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0 x108 0 x41c 0 x000 0 x2 0 x0
#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0 x108 0 x41c 0 x000 0 x3 0 x0
#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0 x108 0 x41c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0 x10c 0 x420 0 x000 0 x0 0 x0
#define MX6QDL_PAD_DISP0_DAT9__LCD_DATA09 0 x10c 0 x420 0 x000 0 x1 0 x0
#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0 x10c 0 x420 0 x000 0 x2 0 x0
#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0 x10c 0 x420 0 x000 0 x3 0 x0
#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0 x10c 0 x420 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0 x110 0 x4e0 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0 x110 0 x4e0 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0 x110 0 x4e0 0 x8b8 0 x2 0 x0
#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0 x110 0 x4e0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0 x110 0 x4e0 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_A16__EPDC_DATA00 0 x110 0 x4e0 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0 x114 0 x4e4 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0 x114 0 x4e4 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0 x114 0 x4e4 0 x890 0 x2 0 x0
#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0 x114 0 x4e4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0 x114 0 x4e4 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_A17__EPDC_PWR_STAT 0 x114 0 x4e4 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0 x118 0 x4e8 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0 x118 0 x4e8 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0 x118 0 x4e8 0 x894 0 x2 0 x0
#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0 x118 0 x4e8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0 x118 0 x4e8 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_A18__EPDC_PWR_CTRL0 0 x118 0 x4e8 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0 x11c 0 x4ec 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0 x11c 0 x4ec 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0 x11c 0 x4ec 0 x898 0 x2 0 x0
#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0 x11c 0 x4ec 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0 x11c 0 x4ec 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_A19__EPDC_PWR_CTRL1 0 x11c 0 x4ec 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0 x120 0 x4f0 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0 x120 0 x4f0 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0 x120 0 x4f0 0 x89c 0 x2 0 x0
#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0 x120 0 x4f0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0 x120 0 x4f0 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_A20__EPDC_PWR_CTRL2 0 x120 0 x4f0 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0 x124 0 x4f4 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0 x124 0 x4f4 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0 x124 0 x4f4 0 x8a0 0 x2 0 x0
#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0 x124 0 x4f4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0 x124 0 x4f4 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0 x124 0 x4f4 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0 x128 0 x4f8 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0 x128 0 x4f8 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0 x128 0 x4f8 0 x8a4 0 x2 0 x0
#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0 x128 0 x4f8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0 x128 0 x4f8 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_A22__EPDC_GDSP 0 x128 0 x4f8 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0 x12c 0 x4fc 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0 x12c 0 x4fc 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0 x12c 0 x4fc 0 x8a8 0 x2 0 x0
#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0 x12c 0 x4fc 0 x000 0 x4 0 x0
#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0 x12c 0 x4fc 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0 x12c 0 x4fc 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_A23__EPDC_GDOE 0 x12c 0 x4fc 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0 x130 0 x500 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0 x130 0 x500 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0 x130 0 x500 0 x8ac 0 x2 0 x0
#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0 x130 0 x500 0 x000 0 x4 0 x0
#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0 x130 0 x500 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0 x130 0 x500 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_A24__EPDC_GDRL 0 x130 0 x500 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0 x134 0 x504 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0 x134 0 x504 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0 x134 0 x504 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0 x134 0 x504 0 x000 0 x3 0 x0
#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0 x134 0 x504 0 x000 0 x4 0 x0
#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0 x134 0 x504 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0 x134 0 x504 0 x85c 0 x6 0 x0
#define MX6QDL_PAD_EIM_A25__EPDC_DATA15 0 x134 0 x504 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_A25__EIM_ACLK_FREERUN 0 x134 0 x504 0 x000 0 x9 0 x0
#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0 x138 0 x508 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0 x138 0 x508 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0 x138 0 x508 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_BCLK__EPDC_SDCE9 0 x138 0 x508 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0 x13c 0 x50c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0 x13c 0 x50c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0 x13c 0 x50c 0 x7f4 0 x2 0 x2
#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0 x13c 0 x50c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0 x13c 0 x50c 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0 x140 0 x510 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0 x140 0 x510 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0 x140 0 x510 0 x7fc 0 x2 0 x2
#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0 x140 0 x510 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_CS1__EPDC_DATA08 0 x140 0 x510 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0 x144 0 x514 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0 x144 0 x514 0 x7d8 0 x1 0 x2
#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0 x144 0 x514 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0 x144 0 x514 0 x8a8 0 x3 0 x1
#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0 x144 0 x514 0 x864 0 x4 0 x0
#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0 x144 0 x514 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0 x144 0 x514 0 x874 0 x6 0 x0
#define MX6QDL_PAD_EIM_D16__EPDC_DATA10 0 x144 0 x514 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0 x148 0 x518 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0 x148 0 x518 0 x7dc 0 x1 0 x2
#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0 x148 0 x518 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0 x148 0 x518 0 x8b8 0 x3 0 x1
#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0 x148 0 x518 0 x000 0 x4 0 x0
#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0 x148 0 x518 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0 x148 0 x518 0 x878 0 x6 0 x0
#define MX6QDL_PAD_EIM_D17__EPDC_VCOM0 0 x148 0 x518 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0 x14c 0 x51c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0 x14c 0 x51c 0 x7e0 0 x1 0 x2
#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0 x14c 0 x51c 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0 x14c 0 x51c 0 x8a4 0 x3 0 x1
#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0 x14c 0 x51c 0 x000 0 x4 0 x0
#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0 x14c 0 x51c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0 x14c 0 x51c 0 x87c 0 x6 0 x0
#define MX6QDL_PAD_EIM_D18__EPDC_VCOM1 0 x14c 0 x51c 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0 x150 0 x520 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0 x150 0 x520 0 x7e8 0 x1 0 x1
#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0 x150 0 x520 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0 x150 0 x520 0 x8a0 0 x3 0 x1
#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0 x150 0 x520 0 x000 0 x4 0 x0
#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0 x150 0 x520 0 x8f8 0 x4 0 x0
#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0 x150 0 x520 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0 x150 0 x520 0 x000 0 x6 0 x0
#define MX6QDL_PAD_EIM_D19__EPDC_DATA12 0 x150 0 x520 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0 x154 0 x524 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0 x154 0 x524 0 x808 0 x1 0 x0
#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0 x154 0 x524 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0 x154 0 x524 0 x89c 0 x3 0 x1
#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0 x154 0 x524 0 x8f8 0 x4 0 x1
#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0 x154 0 x524 0 x000 0 x4 0 x0
#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0 x154 0 x524 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0 x154 0 x524 0 x000 0 x6 0 x0
#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0 x158 0 x528 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0 x158 0 x528 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0 x158 0 x528 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_D21__IPU1_CSI1_DATA11 0 x158 0 x528 0 x88c 0 x3 0 x0
#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0 x158 0 x528 0 x920 0 x4 0 x0
#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0 x158 0 x528 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0 x158 0 x528 0 x868 0 x6 0 x1
#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0 x158 0 x528 0 x8f0 0 x7 0 x0
#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0 x15c 0 x52c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0 x15c 0 x52c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0 x15c 0 x52c 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_D22__IPU1_CSI1_DATA10 0 x15c 0 x52c 0 x888 0 x3 0 x0
#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0 x15c 0 x52c 0 x000 0 x4 0 x0
#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0 x15c 0 x52c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0 x15c 0 x52c 0 x000 0 x6 0 x0
#define MX6QDL_PAD_EIM_D22__EPDC_SDCE6 0 x15c 0 x52c 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0 x160 0 x530 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0 x160 0 x530 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0 x160 0 x530 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0 x160 0 x530 0 x908 0 x2 0 x0
#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0 x160 0 x530 0 x000 0 x3 0 x0
#define MX6QDL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0 x160 0 x530 0 x8b0 0 x4 0 x0
#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0 x160 0 x530 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0 x160 0 x530 0 x000 0 x6 0 x0
#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0 x160 0 x530 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_D23__EPDC_DATA11 0 x160 0 x530 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0 x164 0 x534 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0 x164 0 x534 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0 x164 0 x534 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0 x164 0 x534 0 x90c 0 x2 0 x0
#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0 x164 0 x534 0 x7ec 0 x3 0 x0
#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0 x164 0 x534 0 x000 0 x4 0 x0
#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0 x164 0 x534 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0 x164 0 x534 0 x7bc 0 x6 0 x1
#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0 x164 0 x534 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_D24__EPDC_SDCE7 0 x164 0 x534 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0 x168 0 x538 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0 x168 0 x538 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0 x168 0 x538 0 x90c 0 x2 0 x1
#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0 x168 0 x538 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0 x168 0 x538 0 x7f0 0 x3 0 x0
#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0 x168 0 x538 0 x000 0 x4 0 x0
#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0 x168 0 x538 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0 x168 0 x538 0 x7b8 0 x6 0 x1
#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0 x168 0 x538 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_D25__EPDC_SDCE8 0 x168 0 x538 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0 x16c 0 x53c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0 x16c 0 x53c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0 x16c 0 x53c 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0 x16c 0 x53c 0 x898 0 x3 0 x1
#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0 x16c 0 x53c 0 x000 0 x4 0 x0
#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0 x16c 0 x53c 0 x904 0 x4 0 x0
#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0 x16c 0 x53c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0 x16c 0 x53c 0 x000 0 x6 0 x0
#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0 x16c 0 x53c 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_D26__EPDC_SDOED 0 x16c 0 x53c 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0 x170 0 x540 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0 x170 0 x540 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0 x170 0 x540 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0 x170 0 x540 0 x894 0 x3 0 x1
#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0 x170 0 x540 0 x904 0 x4 0 x1
#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0 x170 0 x540 0 x000 0 x4 0 x0
#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0 x170 0 x540 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0 x170 0 x540 0 x000 0 x6 0 x0
#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0 x170 0 x540 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_D27__EPDC_SDOE 0 x170 0 x540 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0 x174 0 x544 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0 x174 0 x544 0 x86c 0 x1 0 x1
#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0 x174 0 x544 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_D28__IPU1_CSI1_DATA12 0 x174 0 x544 0 x890 0 x3 0 x1
#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0 x174 0 x544 0 x000 0 x4 0 x0
#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0 x174 0 x544 0 x900 0 x4 0 x0
#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0 x174 0 x544 0 x900 0 x4 0 x0
#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0 x174 0 x544 0 x000 0 x4 0 x0
#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0 x174 0 x544 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0 x174 0 x544 0 x000 0 x6 0 x0
#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0 x174 0 x544 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_D28__EPDC_PWR_CTRL3 0 x174 0 x544 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0 x178 0 x548 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0 x178 0 x548 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0 x178 0 x548 0 x808 0 x2 0 x1
#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0 x178 0 x548 0 x900 0 x4 0 x1
#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0 x178 0 x548 0 x000 0 x4 0 x0
#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0 x178 0 x548 0 x000 0 x4 0 x0
#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0 x178 0 x548 0 x900 0 x4 0 x1
#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0 x178 0 x548 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0 x178 0 x548 0 x8bc 0 x6 0 x0
#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0 x178 0 x548 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_D29__EPDC_PWR_WAKE 0 x178 0 x548 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0 x17c 0 x54c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0 x17c 0 x54c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0 x17c 0 x54c 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0 x17c 0 x54c 0 x000 0 x3 0 x0
#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0 x17c 0 x54c 0 x000 0 x4 0 x0
#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0 x17c 0 x54c 0 x908 0 x4 0 x1
#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0 x17c 0 x54c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0 x17c 0 x54c 0 x924 0 x6 0 x0
#define MX6QDL_PAD_EIM_D30__EPDC_SDOEZ 0 x17c 0 x54c 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0 x180 0 x550 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0 x180 0 x550 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0 x180 0 x550 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0 x180 0 x550 0 x000 0 x3 0 x0
#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0 x180 0 x550 0 x908 0 x4 0 x2
#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0 x180 0 x550 0 x000 0 x4 0 x0
#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0 x180 0 x550 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0 x180 0 x550 0 x000 0 x6 0 x0
#define MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0 x180 0 x550 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_D31__EIM_ACLK_FREERUN 0 x180 0 x550 0 x000 0 x9 0 x0
#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0 x184 0 x554 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0 x184 0 x554 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0 x184 0 x554 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0 x184 0 x554 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0 x184 0 x554 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_DA0__EPDC_SDCLK_N 0 x184 0 x554 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0 x188 0 x558 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0 x188 0 x558 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0 x188 0 x558 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0 x188 0 x558 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0 x188 0 x558 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0 x188 0 x558 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0 x18c 0 x55c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0 x18c 0 x55c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0 x18c 0 x55c 0 x8b0 0 x2 0 x1
#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0 x18c 0 x55c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0 x18c 0 x55c 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0 x18c 0 x55c 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0 x190 0 x560 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0 x190 0 x560 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0 x190 0 x560 0 x8b4 0 x2 0 x0
#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0 x190 0 x560 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0 x190 0 x560 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0 x190 0 x560 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0 x194 0 x564 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0 x194 0 x564 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0 x194 0 x564 0 x8bc 0 x2 0 x1
#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0 x194 0 x564 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0 x194 0 x564 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0 x194 0 x564 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0 x198 0 x568 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0 x198 0 x568 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0 x198 0 x568 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0 x198 0 x568 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_DA13__EPDC_DATA13 0 x198 0 x568 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0 x19c 0 x56c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0 x19c 0 x56c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0 x19c 0 x56c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0 x19c 0 x56c 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_DA14__EPDC_DATA14 0 x19c 0 x56c 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0 x1a0 0 x570 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0 x1a0 0 x570 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0 x1a0 0 x570 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0 x1a0 0 x570 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0 x1a0 0 x570 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_DA15__EPDC_DATA09 0 x1a0 0 x570 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0 x1a4 0 x574 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0 x1a4 0 x574 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0 x1a4 0 x574 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0 x1a4 0 x574 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0 x1a4 0 x574 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0 x1a4 0 x574 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0 x1a8 0 x578 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0 x1a8 0 x578 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0 x1a8 0 x578 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0 x1a8 0 x578 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0 x1a8 0 x578 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_DA3__EPDC_BDR1 0 x1a8 0 x578 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0 x1ac 0 x57c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0 x1ac 0 x57c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0 x1ac 0 x57c 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0 x1ac 0 x57c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0 x1ac 0 x57c 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0 x1ac 0 x57c 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0 x1b0 0 x580 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0 x1b0 0 x580 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0 x1b0 0 x580 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0 x1b0 0 x580 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0 x1b0 0 x580 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0 x1b0 0 x580 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0 x1b4 0 x584 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0 x1b4 0 x584 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0 x1b4 0 x584 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0 x1b4 0 x584 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0 x1b4 0 x584 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0 x1b4 0 x584 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0 x1b8 0 x588 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0 x1b8 0 x588 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0 x1b8 0 x588 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0 x1b8 0 x588 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0 x1b8 0 x588 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_DA7__EPDC_SDCE3 0 x1b8 0 x588 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0 x1bc 0 x58c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0 x1bc 0 x58c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0 x1bc 0 x58c 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0 x1bc 0 x58c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0 x1bc 0 x58c 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_DA8__EPDC_SDCE4 0 x1bc 0 x58c 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0 x1c0 0 x590 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0 x1c0 0 x590 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0 x1c0 0 x590 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0 x1c0 0 x590 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0 x1c0 0 x590 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_DA9__EPDC_SDCE5 0 x1c0 0 x590 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0 x1c4 0 x594 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0 x1c4 0 x594 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0 x1c4 0 x594 0 x88c 0 x2 0 x1
#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0 x1c4 0 x594 0 x7d4 0 x4 0 x0
#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0 x1c4 0 x594 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0 x1c4 0 x594 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_EB0__EPDC_PWR_COM 0 x1c4 0 x594 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0 x1c8 0 x598 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0 x1c8 0 x598 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0 x1c8 0 x598 0 x888 0 x2 0 x1
#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0 x1c8 0 x598 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0 x1c8 0 x598 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0 x1c8 0 x598 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0 x1cc 0 x59c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0 x1cc 0 x59c 0 x7e4 0 x1 0 x2
#define MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0 x1cc 0 x59c 0 x8ac 0 x3 0 x1
#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0 x1cc 0 x59c 0 x860 0 x4 0 x0
#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0 x1cc 0 x59c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0 x1cc 0 x59c 0 x870 0 x6 0 x0
#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0 x1cc 0 x59c 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0 x1cc 0 x59c 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0 x1d0 0 x5a0 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0 x1d0 0 x5a0 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0 x1d0 0 x5a0 0 x908 0 x2 0 x3
#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0 x1d0 0 x5a0 0 x000 0 x2 0 x0
#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0 x1d0 0 x5a0 0 x000 0 x3 0 x0
#define MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0 x1d0 0 x5a0 0 x8b4 0 x4 0 x1
#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0 x1d0 0 x5a0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0 x1d0 0 x5a0 0 x000 0 x6 0 x0
#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0 x1d0 0 x5a0 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_EB3__EPDC_SDCE0 0 x1d0 0 x5a0 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0 x1d0 0 x5a0 0 x000 0 x9 0 x0
#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0 x1d4 0 x5a4 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0 x1d4 0 x5a4 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0 x1d4 0 x5a4 0 x804 0 x2 0 x1
#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0 x1d4 0 x5a4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0 x1d4 0 x5a4 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0 x1d4 0 x5a4 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0 x1d8 0 x5a8 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0 x1d8 0 x5a8 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0 x1d8 0 x5a8 0 x7f8 0 x2 0 x2
#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0 x1d8 0 x5a8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_OE__EPDC_PWR_IRQ 0 x1d8 0 x5a8 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_RW__EIM_RW 0 x1dc 0 x5ac 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0 x1dc 0 x5ac 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0 x1dc 0 x5ac 0 x800 0 x2 0 x2
#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0 x1dc 0 x5ac 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0 x1dc 0 x5ac 0 x000 0 x7 0 x0
#define MX6QDL_PAD_EIM_RW__EPDC_DATA07 0 x1dc 0 x5ac 0 x000 0 x8 0 x0
#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0 x1e0 0 x5b0 0 x000 0 x0 0 x0
#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0 x1e0 0 x5b0 0 x000 0 x1 0 x0
#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0 x1e0 0 x5b0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0 x1e0 0 x5b0 0 x000 0 x7 0 x0
#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0 x1e4 0 x5b4 0 x828 0 x1 0 x0
#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0 x1e4 0 x5b4 0 x840 0 x2 0 x0
#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0 x1e4 0 x5b4 0 x8f4 0 x3 0 x0
#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0 x1e4 0 x5b4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0 x1e8 0 x5b8 0 x8e0 0 x0 0 x0
#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0 x1e8 0 x5b8 0 x000 0 x1 0 x0
#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0 x1e8 0 x5b8 0 x858 0 x2 0 x0
#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0 x1e8 0 x5b8 0 x000 0 x4 0 x0
#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0 x1e8 0 x5b8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0 x1ec 0 x5bc 0 x810 0 x1 0 x0
#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0 x1ec 0 x5bc 0 x83c 0 x2 0 x0
#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0 x1ec 0 x5bc 0 x000 0 x4 0 x0
#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0 x1ec 0 x5bc 0 x000 0 x5 0 x0
#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0 x1ec 0 x5bc 0 x000 0 x6 0 x0
#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0 x1f0 0 x5c0 0 x000 0 x1 0 x0
#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0 x1f0 0 x5c0 0 x82c 0 x2 0 x0
#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0 x1f0 0 x5c0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0 x1f0 0 x5c0 0 x000 0 x6 0 x0
#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0 x1f4 0 x5c4 0 x790 0 x0 0 x0
#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0 x1f4 0 x5c4 0 x000 0 x1 0 x0
#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0 x1f4 0 x5c4 0 x834 0 x2 0 x0
#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0 x1f4 0 x5c4 0 x8f0 0 x3 0 x1
#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0 x1f4 0 x5c4 0 x000 0 x4 0 x0
#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0 x1f4 0 x5c4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0 x1f8 0 x5c8 0 x000 0 x0 0 x0
#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0 x1f8 0 x5c8 0 x818 0 x1 0 x0
#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0 x1f8 0 x5c8 0 x838 0 x2 0 x0
#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0 x1f8 0 x5c8 0 x000 0 x3 0 x0
#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0 x1f8 0 x5c8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0 x1fc 0 x5cc 0 x8e4 0 x0 0 x0
#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0 x1fc 0 x5cc 0 x81c 0 x1 0 x0
#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0 x1fc 0 x5cc 0 x830 0 x2 0 x0
#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0 x1fc 0 x5cc 0 x000 0 x4 0 x0
#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0 x1fc 0 x5cc 0 x000 0 x5 0 x0
#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0 x200 0 x5d0 0 x000 0 x1 0 x0
#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0 x200 0 x5d0 0 x850 0 x2 0 x0
#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0 x200 0 x5d0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_ENET_TX_EN__I2C4_SCL 0 x200 0 x5d0 0 x880 0 x9 0 x0
#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0 x204 0 x5d4 0 x000 0 x1 0 x0
#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0 x204 0 x5d4 0 x854 0 x2 0 x0
#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0 x204 0 x5d4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0 x208 0 x5d8 0 x8dc 0 x0 0 x0
#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0 x208 0 x5d8 0 x000 0 x1 0 x0
#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0 x208 0 x5d8 0 x84c 0 x2 0 x0
#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0 x208 0 x5d8 0 x000 0 x4 0 x0
#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0 x208 0 x5d8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_ENET_TXD1__I2C4_SDA 0 x208 0 x5d8 0 x884 0 x9 0 x0
#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0 x20c 0 x5dc 0 x000 0 x0 0 x0
#define MX6QDL_PAD_GPIO_0__KEY_COL5 0 x20c 0 x5dc 0 x8c0 0 x2 0 x1
#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0 x20c 0 x5dc 0 x794 0 x3 0 x0
#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0 x20c 0 x5dc 0 x000 0 x4 0 x0
#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0 x20c 0 x5dc 0 x000 0 x5 0 x0
#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0 x20c 0 x5dc 0 x000 0 x6 0 x0
#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0 x20c 0 x5dc 0 x000 0 x7 0 x0
#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0 x210 0 x5e0 0 x83c 0 x0 0 x1
#define MX6QDL_PAD_GPIO_1__WDOG2_B 0 x210 0 x5e0 0 x000 0 x1 0 x0
#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0 x210 0 x5e0 0 x8cc 0 x2 0 x1
#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0 x210 0 x5e0 0 x790 0 x3 0 x1
#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0 x210 0 x5e0 0 x000 0 x4 0 x0
#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0 x210 0 x5e0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0 x210 0 x5e0 0 x000 0 x6 0 x0
#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0 x214 0 x5e4 0 x850 0 x0 0 x1
#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0 x214 0 x5e4 0 x000 0 x1 0 x0
#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0 x214 0 x5e4 0 x80c 0 x2 0 x0
#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0 x214 0 x5e4 0 x000 0 x3 0 x0
#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0 x214 0 x5e4 0 x8f0 0 x4 0 x2
#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0 x214 0 x5e4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0 x214 0 x5e4 0 x87c 0 x6 0 x1
#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0 x214 0 x5e4 0 x000 0 x7 0 x0
#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0 x218 0 x5e8 0 x844 0 x0 0 x0
#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0 x218 0 x5e8 0 x000 0 x1 0 x0
#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0 x218 0 x5e8 0 x7d4 0 x2 0 x1
#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0 x218 0 x5e8 0 x8e8 0 x3 0 x1
#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0 x218 0 x5e8 0 x000 0 x4 0 x0
#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0 x218 0 x5e8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0 x21c 0 x5ec 0 x848 0 x0 0 x0
#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0 x21c 0 x5ec 0 x814 0 x1 0 x0
#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0 x21c 0 x5ec 0 x000 0 x2 0 x0
#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0 x21c 0 x5ec 0 x8ec 0 x3 0 x1
#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0 x21c 0 x5ec 0 x794 0 x4 0 x1
#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0 x21c 0 x5ec 0 x000 0 x5 0 x0
#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0 x21c 0 x5ec 0 x000 0 x6 0 x0
#define MX6QDL_PAD_GPIO_19__KEY_COL5 0 x220 0 x5f0 0 x8c0 0 x0 0 x2
#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0 x220 0 x5f0 0 x000 0 x1 0 x0
#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0 x220 0 x5f0 0 x000 0 x2 0 x0
#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0 x220 0 x5f0 0 x000 0 x3 0 x0
#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0 x220 0 x5f0 0 x000 0 x4 0 x0
#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0 x220 0 x5f0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0 x220 0 x5f0 0 x000 0 x6 0 x0
#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0 x224 0 x5f4 0 x830 0 x0 0 x1
#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0 x224 0 x5f4 0 x8d0 0 x2 0 x1
#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0 x224 0 x5f4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_GPIO_2__SD2_WP 0 x224 0 x5f4 0 x000 0 x6 0 x0
#define MX6QDL_PAD_GPIO_2__MLB_DATA 0 x224 0 x5f4 0 x8e0 0 x7 0 x1
#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0 x228 0 x5f8 0 x834 0 x0 0 x1
#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0 x228 0 x5f8 0 x878 0 x2 0 x1
#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0 x228 0 x5f8 0 x000 0 x3 0 x0
#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0 x228 0 x5f8 0 x000 0 x4 0 x0
#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0 x228 0 x5f8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0 x228 0 x5f8 0 x924 0 x6 0 x1
#define MX6QDL_PAD_GPIO_3__MLB_CLK 0 x228 0 x5f8 0 x8dc 0 x7 0 x1
#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0 x22c 0 x5fc 0 x838 0 x0 0 x1
#define MX6QDL_PAD_GPIO_4__KEY_COL7 0 x22c 0 x5fc 0 x8c8 0 x2 0 x1
#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0 x22c 0 x5fc 0 x000 0 x5 0 x0
#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0 x22c 0 x5fc 0 x000 0 x6 0 x0
#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0 x230 0 x600 0 x84c 0 x0 0 x1
#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0 x230 0 x600 0 x8d4 0 x2 0 x1
#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0 x230 0 x600 0 x000 0 x3 0 x0
#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0 x230 0 x600 0 x000 0 x5 0 x0
#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0 x230 0 x600 0 x878 0 x6 0 x2
#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0 x230 0 x600 0 x000 0 x7 0 x0
#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0 x234 0 x604 0 x840 0 x0 0 x1
#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0 x234 0 x604 0 x03c 0 x11 0 xff000609
#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0 x234 0 x604 0 x87c 0 x2 0 x2
#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0 x234 0 x604 0 x000 0 x5 0 x0
#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0 x234 0 x604 0 x000 0 x6 0 x0
#define MX6QDL_PAD_GPIO_6__MLB_SIG 0 x234 0 x604 0 x8e4 0 x7 0 x1
#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0 x238 0 x608 0 x854 0 x0 0 x1
#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0 x238 0 x608 0 x000 0 x2 0 x0
#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0 x238 0 x608 0 x000 0 x3 0 x0
#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0 x238 0 x608 0 x000 0 x4 0 x0
#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0 x238 0 x608 0 x904 0 x4 0 x2
#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0 x238 0 x608 0 x000 0 x5 0 x0
#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0 x238 0 x608 0 x000 0 x6 0 x0
#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0 x238 0 x608 0 x000 0 x7 0 x0
#define MX6QDL_PAD_GPIO_7__I2C4_SCL 0 x238 0 x608 0 x880 0 x8 0 x1
#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0 x23c 0 x60c 0 x858 0 x0 0 x1
#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0 x23c 0 x60c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0 x23c 0 x60c 0 x000 0 x2 0 x0
#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0 x23c 0 x60c 0 x7c8 0 x3 0 x0
#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0 x23c 0 x60c 0 x904 0 x4 0 x3
#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0 x23c 0 x60c 0 x000 0 x4 0 x0
#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0 x23c 0 x60c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0 x23c 0 x60c 0 x000 0 x6 0 x0
#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0 x23c 0 x60c 0 x000 0 x7 0 x0
#define MX6QDL_PAD_GPIO_8__I2C4_SDA 0 x23c 0 x60c 0 x884 0 x8 0 x1
#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0 x240 0 x610 0 x82c 0 x0 0 x1
#define MX6QDL_PAD_GPIO_9__WDOG1_B 0 x240 0 x610 0 x000 0 x1 0 x0
#define MX6QDL_PAD_GPIO_9__KEY_COL6 0 x240 0 x610 0 x8c4 0 x2 0 x1
#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0 x240 0 x610 0 x000 0 x3 0 x0
#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0 x240 0 x610 0 x000 0 x4 0 x0
#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0 x240 0 x610 0 x000 0 x5 0 x0
#define MX6QDL_PAD_GPIO_9__SD1_WP 0 x240 0 x610 0 x92c 0 x6 0 x1
#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0 x244 0 x62c 0 x7d8 0 x0 0 x3
#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0 x244 0 x62c 0 x824 0 x1 0 x0
#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0 x244 0 x62c 0 x7c0 0 x2 0 x1
#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0 x244 0 x62c 0 x000 0 x3 0 x0
#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0 x244 0 x62c 0 x000 0 x4 0 x0
#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0 x244 0 x62c 0 x914 0 x4 0 x2
#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0 x244 0 x62c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0 x244 0 x62c 0 x000 0 x6 0 x0
#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0 x248 0 x630 0 x7dc 0 x0 0 x3
#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0 x248 0 x630 0 x810 0 x1 0 x1
#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0 x248 0 x630 0 x7c4 0 x2 0 x1
#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0 x248 0 x630 0 x000 0 x3 0 x0
#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0 x248 0 x630 0 x000 0 x4 0 x0
#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0 x248 0 x630 0 x91c 0 x4 0 x2
#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0 x248 0 x630 0 x000 0 x5 0 x0
#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0 x248 0 x630 0 x000 0 x6 0 x0
#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0 x24c 0 x634 0 x7e8 0 x0 0 x2
#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0 x24c 0 x634 0 x820 0 x1 0 x0
#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0 x24c 0 x634 0 x000 0 x2 0 x0
#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0 x24c 0 x634 0 x000 0 x3 0 x0
#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0 x24c 0 x634 0 x000 0 x4 0 x0
#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0 x24c 0 x634 0 x000 0 x5 0 x0
#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0 x24c 0 x634 0 x000 0 x6 0 x0
#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0 x250 0 x638 0 x7f0 0 x0 0 x1
#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0 x250 0 x638 0 x000 0 x1 0 x0
#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0 x250 0 x638 0 x860 0 x2 0 x1
#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0 x250 0 x638 0 x000 0 x3 0 x0
#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0 x250 0 x638 0 x870 0 x4 0 x1
#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0 x250 0 x638 0 x000 0 x5 0 x0
#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0 x250 0 x638 0 x8f0 0 x6 0 x3
#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0 x254 0 x63c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0 x254 0 x63c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0 x254 0 x63c 0 x920 0 x2 0 x1
#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0 x254 0 x63c 0 x000 0 x3 0 x0
#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0 x254 0 x63c 0 x918 0 x4 0 x2
#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0 x254 0 x63c 0 x000 0 x4 0 x0
#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0 x254 0 x63c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0 x258 0 x640 0 x7e0 0 x0 0 x3
#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0 x258 0 x640 0 x000 0 x1 0 x0
#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0 x258 0 x640 0 x7b4 0 x2 0 x1
#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0 x258 0 x640 0 x000 0 x3 0 x0
#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0 x258 0 x640 0 x914 0 x4 0 x3
#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0 x258 0 x640 0 x000 0 x4 0 x0
#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0 x258 0 x640 0 x000 0 x5 0 x0
#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0 x258 0 x640 0 x000 0 x6 0 x0
#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0 x25c 0 x644 0 x7e4 0 x0 0 x3
#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0 x25c 0 x644 0 x000 0 x1 0 x0
#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0 x25c 0 x644 0 x7b0 0 x2 0 x1
#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0 x25c 0 x644 0 x000 0 x3 0 x0
#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0 x25c 0 x644 0 x91c 0 x4 0 x3
#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0 x25c 0 x644 0 x000 0 x4 0 x0
#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0 x25c 0 x644 0 x000 0 x5 0 x0
#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0 x25c 0 x644 0 x000 0 x6 0 x0
#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0 x260 0 x648 0 x7ec 0 x0 0 x1
#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0 x260 0 x648 0 x000 0 x1 0 x0
#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0 x260 0 x648 0 x7c8 0 x2 0 x1
#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0 x260 0 x648 0 x000 0 x3 0 x0
#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0 x260 0 x648 0 x000 0 x4 0 x0
#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0 x260 0 x648 0 x000 0 x5 0 x0
#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0 x260 0 x648 0 x85c 0 x6 0 x1
#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0 x264 0 x64c 0 x794 0 x1 0 x2
#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0 x264 0 x64c 0 x864 0 x2 0 x1
#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0 x264 0 x64c 0 x000 0 x3 0 x0
#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0 x264 0 x64c 0 x874 0 x4 0 x1
#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0 x264 0 x64c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0 x264 0 x64c 0 x000 0 x6 0 x0
#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0 x268 0 x650 0 x7cc 0 x0 0 x0
#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0 x268 0 x650 0 x000 0 x1 0 x0
#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0 x268 0 x650 0 x000 0 x2 0 x0
#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0 x268 0 x650 0 x000 0 x3 0 x0
#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0 x268 0 x650 0 x000 0 x4 0 x0
#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0 x268 0 x650 0 x918 0 x4 0 x3
#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0 x268 0 x650 0 x000 0 x5 0 x0
#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0 x26c 0 x654 0 x000 0 x0 0 x0
#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0 x26c 0 x654 0 x000 0 x1 0 x0
#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0 x26c 0 x654 0 x000 0 x5 0 x0
#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0 x270 0 x658 0 x000 0 x0 0 x0
#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0 x270 0 x658 0 x000 0 x5 0 x0
#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0 x274 0 x65c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0 x274 0 x65c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0 x278 0 x660 0 x000 0 x0 0 x0
#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0 x278 0 x660 0 x000 0 x1 0 x0
#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0 x278 0 x660 0 x000 0 x2 0 x0
#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0 x278 0 x660 0 x000 0 x5 0 x0
#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0 x27c 0 x664 0 x000 0 x0 0 x0
#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0 x27c 0 x664 0 x000 0 x1 0 x0
#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0 x27c 0 x664 0 x844 0 x2 0 x1
#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0 x27c 0 x664 0 x000 0 x3 0 x0
#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0 x27c 0 x664 0 x000 0 x4 0 x0
#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0 x27c 0 x664 0 x000 0 x5 0 x0
#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0 x280 0 x668 0 x000 0 x0 0 x0
#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0 x280 0 x668 0 x000 0 x1 0 x0
#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0 x280 0 x668 0 x848 0 x2 0 x1
#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0 x280 0 x668 0 x000 0 x3 0 x0
#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0 x280 0 x668 0 x000 0 x5 0 x0
#define MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0 x280 0 x668 0 x884 0 x9 0 x2
#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0 x284 0 x66c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0 x284 0 x66c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0 x284 0 x66c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0 x288 0 x670 0 x000 0 x0 0 x0
#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0 x288 0 x670 0 x000 0 x1 0 x0
#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0 x288 0 x670 0 x000 0 x5 0 x0
#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0 x28c 0 x674 0 x000 0 x0 0 x0
#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0 x28c 0 x674 0 x000 0 x1 0 x0
#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0 x28c 0 x674 0 x000 0 x5 0 x0
#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0 x290 0 x678 0 x000 0 x0 0 x0
#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0 x290 0 x678 0 x000 0 x1 0 x0
#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0 x290 0 x678 0 x000 0 x5 0 x0
#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0 x294 0 x67c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0 x294 0 x67c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0 x294 0 x67c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0 x298 0 x680 0 x000 0 x0 0 x0
#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0 x298 0 x680 0 x000 0 x1 0 x0
#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0 x298 0 x680 0 x000 0 x5 0 x0
#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0 x29c 0 x684 0 x000 0 x0 0 x0
#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0 x29c 0 x684 0 x000 0 x1 0 x0
#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0 x29c 0 x684 0 x000 0 x5 0 x0
#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0 x2a0 0 x688 0 x000 0 x0 0 x0
#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0 x2a0 0 x688 0 x000 0 x1 0 x0
#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0 x2a0 0 x688 0 x000 0 x5 0 x0
#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0 x2a4 0 x68c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0 x2a4 0 x68c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0 x2a8 0 x690 0 x000 0 x0 0 x0
#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0 x2a8 0 x690 0 x000 0 x5 0 x0
#define MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0 x2a8 0 x690 0 x880 0 x9 0 x2
#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0 x2ac 0 x694 0 x000 0 x0 0 x0
#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0 x2ac 0 x694 0 x818 0 x1 0 x1
#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0 x2ac 0 x694 0 x000 0 x5 0 x0
#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0 x2b0 0 x698 0 x000 0 x0 0 x0
#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0 x2b0 0 x698 0 x81c 0 x1 0 x1
#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0 x2b0 0 x698 0 x000 0 x5 0 x0
#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0 x2b4 0 x69c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0 x2b4 0 x69c 0 x820 0 x1 0 x1
#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0 x2b4 0 x69c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0 x2b8 0 x6a0 0 x000 0 x0 0 x0
#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0 x2b8 0 x6a0 0 x824 0 x1 0 x1
#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0 x2b8 0 x6a0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0 x2bc 0 x6a4 0 x000 0 x0 0 x0
#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0 x2bc 0 x6a4 0 x828 0 x1 0 x1
#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0 x2bc 0 x6a4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0 x2c0 0 x6a8 0 x000 0 x0 0 x0
#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0 x2c0 0 x6a8 0 x814 0 x1 0 x1
#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0 x2c0 0 x6a8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0 x2c4 0 x6ac 0 x000 0 x0 0 x0
#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0 x2c4 0 x6ac 0 x000 0 x1 0 x0
#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0 x2c4 0 x6ac 0 x000 0 x5 0 x0
#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0 x2c8 0 x6b0 0 x000 0 x0 0 x0
#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0 x2c8 0 x6b0 0 x000 0 x1 0 x0
#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0 x2c8 0 x6b0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0 x2cc 0 x6b4 0 x000 0 x0 0 x0
#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0 x2cc 0 x6b4 0 x000 0 x1 0 x0
#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0 x2cc 0 x6b4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0 x2d0 0 x6b8 0 x000 0 x0 0 x0
#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0 x2d0 0 x6b8 0 x000 0 x1 0 x0
#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0 x2d0 0 x6b8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0 x2d4 0 x6bc 0 x000 0 x0 0 x0
#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0 x2d4 0 x6bc 0 x000 0 x1 0 x0
#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0 x2d4 0 x6bc 0 x000 0 x5 0 x0
#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0 x2d4 0 x6bc 0 x80c 0 x7 0 x1
#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0 x2d8 0 x6c0 0 x000 0 x0 0 x0
#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0 x2d8 0 x6c0 0 x000 0 x1 0 x0
#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0 x2d8 0 x6c0 0 x8f4 0 x2 0 x1
#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0 x2d8 0 x6c0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0 x2d8 0 x6c0 0 x000 0 x7 0 x0
#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0 x2dc 0 x6c4 0 x928 0 x0 0 x1
#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0 x2dc 0 x6c4 0 x000 0 x2 0 x0
#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0 x2dc 0 x6c4 0 x000 0 x3 0 x0
#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0 x2dc 0 x6c4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0 x2e0 0 x6c8 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0 x2e0 0 x6c8 0 x000 0 x2 0 x0
#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0 x2e0 0 x6c8 0 x000 0 x3 0 x0
#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0 x2e0 0 x6c8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0 x2e4 0 x6cc 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0 x2e4 0 x6cc 0 x000 0 x3 0 x0
#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0 x2e4 0 x6cc 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0 x2e8 0 x6d0 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0 x2e8 0 x6d0 0 x000 0 x2 0 x0
#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0 x2e8 0 x6d0 0 x000 0 x3 0 x0
#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0 x2e8 0 x6d0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0 x2ec 0 x6d4 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0 x2ec 0 x6d4 0 x000 0 x2 0 x0
#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0 x2ec 0 x6d4 0 x000 0 x3 0 x0
#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0 x2ec 0 x6d4 0 x000 0 x4 0 x0
#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0 x2ec 0 x6d4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0 x2ec 0 x6d4 0 x000 0 x6 0 x0
#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0 x2f0 0 x6d8 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0 x2f0 0 x6d8 0 x000 0 x2 0 x0
#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0 x2f0 0 x6d8 0 x000 0 x3 0 x0
#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0 x2f0 0 x6d8 0 x000 0 x4 0 x0
#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0 x2f0 0 x6d8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0 x2f0 0 x6d8 0 x000 0 x6 0 x0
#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0 x2f4 0 x6dc 0 x930 0 x0 0 x1
#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0 x2f4 0 x6dc 0 x8c0 0 x2 0 x3
#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0 x2f4 0 x6dc 0 x7a4 0 x3 0 x1
#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0 x2f4 0 x6dc 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0 x2f8 0 x6e0 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0 x2f8 0 x6e0 0 x8cc 0 x2 0 x2
#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0 x2f8 0 x6e0 0 x7a0 0 x3 0 x1
#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0 x2f8 0 x6e0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0 x2fc 0 x6e4 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0 x2fc 0 x6e4 0 x798 0 x3 0 x1
#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0 x2fc 0 x6e4 0 x8d4 0 x4 0 x2
#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0 x2fc 0 x6e4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0 x2fc 0 x6e4 0 x000 0 x6 0 x0
#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0 x300 0 x6e8 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0 x300 0 x6e8 0 x000 0 x2 0 x0
#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0 x300 0 x6e8 0 x7ac 0 x3 0 x1
#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0 x300 0 x6e8 0 x8c8 0 x4 0 x2
#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0 x300 0 x6e8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0 x304 0 x6ec 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0 x304 0 x6ec 0 x000 0 x2 0 x0
#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0 x304 0 x6ec 0 x79c 0 x3 0 x1
#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0 x304 0 x6ec 0 x8d0 0 x4 0 x2
#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0 x304 0 x6ec 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0 x308 0 x6f0 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0 x308 0 x6f0 0 x8c4 0 x2 0 x2
#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0 x308 0 x6f0 0 x7a8 0 x3 0 x1
#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0 x308 0 x6f0 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0 x30c 0 x6f4 0 x934 0 x0 0 x1
#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0 x30c 0 x6f4 0 x900 0 x1 0 x2
#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0 x30c 0 x6f4 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0 x30c 0 x6f4 0 x7c8 0 x2 0 x2
#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0 x30c 0 x6f4 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0 x310 0 x6f8 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0 x310 0 x6f8 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0 x310 0 x6f8 0 x900 0 x1 0 x3
#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0 x310 0 x6f8 0 x000 0 x2 0 x0
#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0 x310 0 x6f8 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0 x314 0 x6fc 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0 x314 0 x6fc 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0 x314 0 x6fc 0 x8f8 0 x1 0 x2
#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0 x314 0 x6fc 0 x000 0 x2 0 x0
#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0 x314 0 x6fc 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0 x318 0 x700 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0 x318 0 x700 0 x8f8 0 x1 0 x3
#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0 x318 0 x700 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0 x318 0 x700 0 x7cc 0 x2 0 x1
#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0 x318 0 x700 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0 x31c 0 x704 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0 x31c 0 x704 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0 x320 0 x708 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0 x320 0 x708 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0 x320 0 x708 0 x908 0 x1 0 x4
#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0 x320 0 x708 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0 x324 0 x70c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0 x324 0 x70c 0 x904 0 x1 0 x4
#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0 x324 0 x70c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0 x324 0 x70c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0 x328 0 x710 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0 x328 0 x710 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0 x328 0 x710 0 x904 0 x1 0 x5
#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0 x328 0 x710 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0 x32c 0 x714 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0 x32c 0 x714 0 x8fc 0 x1 0 x2
#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0 x32c 0 x714 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0 x32c 0 x714 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0 x330 0 x718 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0 x330 0 x718 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0 x330 0 x718 0 x8fc 0 x1 0 x3
#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0 x330 0 x718 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD3_RST__SD3_RESET 0 x334 0 x71c 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0 x334 0 x71c 0 x908 0 x1 0 x5
#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0 x334 0 x71c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0 x334 0 x71c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0 x338 0 x720 0 x938 0 x0 0 x1
#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0 x338 0 x720 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0 x338 0 x720 0 x90c 0 x2 0 x2
#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0 x338 0 x720 0 x000 0 x2 0 x0
#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0 x338 0 x720 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0 x33c 0 x724 0 x000 0 x0 0 x0
#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0 x33c 0 x724 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0 x33c 0 x724 0 x000 0 x2 0 x0
#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0 x33c 0 x724 0 x90c 0 x2 0 x3
#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0 x33c 0 x724 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0 x340 0 x728 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0 x340 0 x728 0 x000 0 x2 0 x0
#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0 x340 0 x728 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0 x344 0 x72c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0 x344 0 x72c 0 x000 0 x2 0 x0
#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0 x344 0 x72c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0 x348 0 x730 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0 x348 0 x730 0 x000 0 x2 0 x0
#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0 x348 0 x730 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0 x34c 0 x734 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0 x34c 0 x734 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0 x350 0 x738 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0 x350 0 x738 0 x904 0 x2 0 x6
#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0 x350 0 x738 0 x000 0 x2 0 x0
#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0 x350 0 x738 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0 x354 0 x73c 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0 x354 0 x73c 0 x900 0 x2 0 x4
#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0 x354 0 x73c 0 x000 0 x2 0 x0
#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0 x354 0 x73c 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0 x358 0 x740 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0 x358 0 x740 0 x000 0 x2 0 x0
#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0 x358 0 x740 0 x900 0 x2 0 x5
#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0 x358 0 x740 0 x000 0 x5 0 x0
#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0 x35c 0 x744 0 x000 0 x1 0 x0
#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0 x35c 0 x744 0 x000 0 x2 0 x0
#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0 x35c 0 x744 0 x904 0 x2 0 x7
#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0 x35c 0 x744 0 x000 0 x5 0 x0
#endif /* __DTS_IMX6DL_PINFUNC_H */
Messung V0.5 in Prozent C=96 H=94 G=94
¤ Dauer der Verarbeitung: 0.14 Sekunden
(vorverarbeitet am 2026-06-08)
¤
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