// SPDX-License-Identifier: GPL-2.0 /* * linux / arch / alpha / kernel / err_titan . c * * Copyright ( C ) 2000 Jeff Wiedemeier ( Compaq Computer Corporation ) * * Error handling code supporting TITAN systems #include <linux/init.h>#include <linux/pci.h>#include <linux/sched.h>#include <asm /io.h>#include <asm /core_titan.h>#include <asm /hwrpb.h>#include <asm /smp.h>#include <asm /err_common.h>#include <asm /err_ev6.h>#include <asm /irq_regs.h>#include "err_impl.h" #include "proto.h" static int int print)#ifdef CONFIG_VERBOSE_MCHECKchar *src;int nxs = 0 ;#endif int status = MCHK_DISPOSITION_REPORT;#define TITAN__CCHIP_MISC__NXM (1 UL << 28 )#define TITAN__CCHIP_MISC__NXS__S (29 )#define TITAN__CCHIP_MISC__NXS__M (0 x7)if (!(c_misc & TITAN__CCHIP_MISC__NXM))return MCHK_DISPOSITION_UNKNOWN_ERROR;#ifdef CONFIG_VERBOSE_MCHECKif (!print)return status;switch (nxs) {case 0 : /* CPU 0 */ case 1 : /* CPU 1 */ case 2 : /* CPU 2 */ case 3 : /* CPU 3 */ "CPU" ;/* num is already the CPU number */ break ;case 4 : /* Pchip 0 */ case 5 : /* Pchip 1 */ "Pchip" ;4 ;break ;default :/* reserved */ "Unknown, NXS =" ;/* leave num untouched */ break ;"%s Non-existent memory access from: %s %d\n" , #endif /* CONFIG_VERBOSE_MCHECK */ return status;static int int which, u64 serror, int print)int status = MCHK_DISPOSITION_REPORT;#ifdef CONFIG_VERBOSE_MCHECKstatic const char * const serror_src[] = {"GPCI" , "APCI" , "AGP HP" , "AGP LP" static const char * const serror_cmd[] = {"DMA Read" , "DMA RMW" , "SGTE Read" , "Reserved" #endif /* CONFIG_VERBOSE_MCHECK */ #define TITAN__PCHIP_SERROR__LOST_UECC (1 UL << 0 )#define TITAN__PCHIP_SERROR__UECC (1 UL << 1 )#define TITAN__PCHIP_SERROR__CRE (1 UL << 2 )#define TITAN__PCHIP_SERROR__NXIO (1 UL << 3 )#define TITAN__PCHIP_SERROR__LOST_CRE (1 UL << 4 )#define TITAN__PCHIP_SERROR__ECCMASK (TITAN__PCHIP_SERROR__UECC | \#define TITAN__PCHIP_SERROR__ERRMASK (TITAN__PCHIP_SERROR__LOST_UECC | \#define TITAN__PCHIP_SERROR__SRC__S (52 )#define TITAN__PCHIP_SERROR__SRC__M (0 x3)#define TITAN__PCHIP_SERROR__CMD__S (54 )#define TITAN__PCHIP_SERROR__CMD__M (0 x3)#define TITAN__PCHIP_SERROR__SYN__S (56 )#define TITAN__PCHIP_SERROR__SYN__M (0 xff)#define TITAN__PCHIP_SERROR__ADDR__S (15 )#define TITAN__PCHIP_SERROR__ADDR__M (0 xffffffffUL)if (!(serror & TITAN__PCHIP_SERROR__ERRMASK))return MCHK_DISPOSITION_UNKNOWN_ERROR;#ifdef CONFIG_VERBOSE_MCHECKif (!print)return status;"%s PChip %d SERROR: %016llx\n" ,if (serror & TITAN__PCHIP_SERROR__ECCMASK) {"%s %sorrectable ECC Error:\n" " Source: %-6s Command: %-8s Syndrome: 0x%08x\n" " Address: 0x%llx\n" ,"Unc" : "C" ,unsigned )EXTRACT(serror, TITAN__PCHIP_SERROR__SYN),if (serror & TITAN__PCHIP_SERROR__NXIO)"%s Non Existent I/O Error\n" , err_print_prefix);if (serror & TITAN__PCHIP_SERROR__LOST_UECC)"%s Lost Uncorrectable ECC Error\n" , if (serror & TITAN__PCHIP_SERROR__LOST_CRE)"%s Lost Correctable ECC Error\n" , err_print_prefix);#endif /* CONFIG_VERBOSE_MCHECK */ return status;static int int which, int port, u64 perror, int print)int cmd;unsigned long addr;int status = MCHK_DISPOSITION_REPORT;#ifdef CONFIG_VERBOSE_MCHECKstatic const char * const perror_cmd[] = {"Interrupt Acknowledge" , "Special Cycle" ,"I/O Read" , "I/O Write" ,"Reserved" , "Reserved" ,"Memory Read" , "Memory Write" ,"Reserved" , "Reserved" ,"Configuration Read" , "Configuration Write" ,"Memory Read Multiple" , "Dual Address Cycle" ,"Memory Read Line" , "Memory Write and Invalidate" #endif /* CONFIG_VERBOSE_MCHECK */ #define TITAN__PCHIP_PERROR__LOST (1 UL << 0 )#define TITAN__PCHIP_PERROR__SERR (1 UL << 1 )#define TITAN__PCHIP_PERROR__PERR (1 UL << 2 )#define TITAN__PCHIP_PERROR__DCRTO (1 UL << 3 )#define TITAN__PCHIP_PERROR__SGE (1 UL << 4 )#define TITAN__PCHIP_PERROR__APE (1 UL << 5 )#define TITAN__PCHIP_PERROR__TA (1 UL << 6 )#define TITAN__PCHIP_PERROR__DPE (1 UL << 7 )#define TITAN__PCHIP_PERROR__NDS (1 UL << 8 )#define TITAN__PCHIP_PERROR__IPTPR (1 UL << 9 )#define TITAN__PCHIP_PERROR__IPTPW (1 UL << 10 )#define TITAN__PCHIP_PERROR__ERRMASK (TITAN__PCHIP_PERROR__LOST | \#define TITAN__PCHIP_PERROR__DAC (1 UL << 47 )#define TITAN__PCHIP_PERROR__MWIN (1 UL << 48 )#define TITAN__PCHIP_PERROR__CMD__S (52 )#define TITAN__PCHIP_PERROR__CMD__M (0 x0f)#define TITAN__PCHIP_PERROR__ADDR__S (14 )#define TITAN__PCHIP_PERROR__ADDR__M (0 x1fffffffful)if (!(perror & TITAN__PCHIP_PERROR__ERRMASK))return MCHK_DISPOSITION_UNKNOWN_ERROR;2 ;/* * Initializing the BIOS on a video card on a bus without * a south bridge ( subtractive decode agent ) can result in * master aborts as the BIOS probes the capabilities of the * card . XFree86 does such initialization . If the error * is a master abort ( No DevSel as PCI Master ) and the command * is an I / O read or write below the address where we start * assigning PCI I / O spaces ( SRM uses 0 x1000 ) , then mark the * error as dismissable so starting XFree86 doesn ' t result * in a series of uncorrectable errors being reported . Also * dismiss master aborts to VGA frame buffer space * ( 0 xA0000 - 0 xC0000 ) and legacy BIOS space ( 0 xC0000 - 0 x100000 ) * for the same reason . * * Also mark the error dismissible if it looks like the right * error but only the Lost bit is set . Since the BIOS initialization * can cause multiple master aborts and the error interrupt can * be handled on a different CPU than the BIOS code is run on , * it is possible for a second master abort to occur between the * time the PALcode reads PERROR and the time it writes PERROR * to acknowledge the error . If this timing happens , a second * error will be signalled after the first , and if no additional * errors occur , will look like a Lost error with no additional * errors on the same transaction as the previous error . if (((perror & TITAN__PCHIP_PERROR__NDS) || 0 xE) == 2 ) && (addr < 0 x1000)) ||0 xE) == 6 ) && (addr >= 0 xA0000) && (addr < 0 x100000)))) {#ifdef CONFIG_VERBOSE_MCHECKif (!print) return status;"%s PChip %d %cPERROR: %016llx\n" ,'A' : 'G' , perror);if (perror & TITAN__PCHIP_PERROR__IPTPW)"%s Invalid Peer-to-Peer Write\n" , err_print_prefix);if (perror & TITAN__PCHIP_PERROR__IPTPR)"%s Invalid Peer-to-Peer Read\n" , err_print_prefix);if (perror & TITAN__PCHIP_PERROR__NDS)"%s No DEVSEL as PCI Master [Master Abort]\n" ,if (perror & TITAN__PCHIP_PERROR__DPE)"%s Data Parity Error\n" , err_print_prefix);if (perror & TITAN__PCHIP_PERROR__TA)"%s Target Abort\n" , err_print_prefix);if (perror & TITAN__PCHIP_PERROR__APE)"%s Address Parity Error\n" , err_print_prefix);if (perror & TITAN__PCHIP_PERROR__SGE)"%s Scatter-Gather Error, Invalid PTE\n" , if (perror & TITAN__PCHIP_PERROR__DCRTO)"%s Delayed-Completion Retry Timeout\n" , if (perror & TITAN__PCHIP_PERROR__PERR)"%s PERR Asserted\n" , err_print_prefix);if (perror & TITAN__PCHIP_PERROR__SERR)"%s SERR Asserted\n" , err_print_prefix);if (perror & TITAN__PCHIP_PERROR__LOST)"%s Lost Error\n" , err_print_prefix);"%s Command: 0x%x - %s\n" " Address: 0x%lx\n" ,if (perror & TITAN__PCHIP_PERROR__DAC)"%s Dual Address Cycle\n" , err_print_prefix);if (perror & TITAN__PCHIP_PERROR__MWIN)"%s Hit in Monster Window\n" , err_print_prefix);#endif /* CONFIG_VERBOSE_MCHECK */ return status;static int int which, u64 agperror, int print)int status = MCHK_DISPOSITION_REPORT;#ifdef CONFIG_VERBOSE_MCHECKint cmd, len;unsigned long addr;static const char * const agperror_cmd[] = {"Read (low-priority)" , "Read (high-priority)" ,"Write (low-priority)" , "Write (high-priority)" ,"Reserved" , "Reserved" ,"Flush" , "Fence" #endif /* CONFIG_VERBOSE_MCHECK */ #define TITAN__PCHIP_AGPERROR__LOST (1 UL << 0 )#define TITAN__PCHIP_AGPERROR__LPQFULL (1 UL << 1 )#define TITAN__PCHIP_AGPERROR__HPQFULL (1 UL << 2 )#define TITAN__PCHIP_AGPERROR__RESCMD (1 UL << 3 )#define TITAN__PCHIP_AGPERROR__IPTE (1 UL << 4 )#define TITAN__PCHIP_AGPERROR__PTP (1 UL << 5 )#define TITAN__PCHIP_AGPERROR__NOWINDOW (1 UL << 6 )#define TITAN__PCHIP_AGPERROR__ERRMASK (TITAN__PCHIP_AGPERROR__LOST | \#define TITAN__PCHIP_AGPERROR__DAC (1 UL << 48 )#define TITAN__PCHIP_AGPERROR__MWIN (1 UL << 49 )#define TITAN__PCHIP_AGPERROR__FENCE (1 UL << 59 )#define TITAN__PCHIP_AGPERROR__CMD__S (50 )#define TITAN__PCHIP_AGPERROR__CMD__M (0 x07)#define TITAN__PCHIP_AGPERROR__ADDR__S (15 )#define TITAN__PCHIP_AGPERROR__ADDR__M (0 xffffffffUL)#define TITAN__PCHIP_AGPERROR__LEN__S (53 )#define TITAN__PCHIP_AGPERROR__LEN__M (0 x3f)if (!(agperror & TITAN__PCHIP_AGPERROR__ERRMASK))return MCHK_DISPOSITION_UNKNOWN_ERROR;#ifdef CONFIG_VERBOSE_MCHECKif (!print)return status;3 ;"%s PChip %d AGPERROR: %016llx\n" , err_print_prefix,if (agperror & TITAN__PCHIP_AGPERROR__NOWINDOW)"%s No Window\n" , err_print_prefix);if (agperror & TITAN__PCHIP_AGPERROR__PTP)"%s Peer-to-Peer set\n" , err_print_prefix);if (agperror & TITAN__PCHIP_AGPERROR__IPTE)"%s Invalid PTE\n" , err_print_prefix);if (agperror & TITAN__PCHIP_AGPERROR__RESCMD)"%s Reserved Command\n" , err_print_prefix);if (agperror & TITAN__PCHIP_AGPERROR__HPQFULL)"%s HP Transaction Received while Queue Full\n" , if (agperror & TITAN__PCHIP_AGPERROR__LPQFULL)"%s LP Transaction Received while Queue Full\n" , if (agperror & TITAN__PCHIP_AGPERROR__LOST)"%s Lost Error\n" , err_print_prefix);"%s Command: 0x%x - %s, %d Quadwords%s\n" " Address: 0x%lx\n" ,", FENCE" : "" ,if (agperror & TITAN__PCHIP_AGPERROR__DAC)"%s Dual Address Cycle\n" , err_print_prefix);if (agperror & TITAN__PCHIP_AGPERROR__MWIN)"%s Hit in Monster Window\n" , err_print_prefix);#endif /* CONFIG_VERBOSE_MCHECK */ return status;static int int which, u64 serror, u64 gperror, int print)int status = MCHK_DISPOSITION_UNKNOWN_ERROR;0 , gperror, print);1 , aperror, print);return status;int struct el_common *mchk_header, int print)struct el_TITAN_sysdata_mcheck *tmchk =struct el_TITAN_sysdata_mcheck *)unsigned long )mchk_header + mchk_header->sys_offset);int status = MCHK_DISPOSITION_UNKNOWN_ERROR;0 , tmchk->p0_serror, tmchk->p0_gperror,1 , tmchk->p1_serror, tmchk->p1_gperror,return status;void unsigned long vector, unsigned long la_ptr)struct el_common *mchk_header = (struct el_common *)la_ptr;struct el_TITAN_sysdata_mcheck *tmchk =struct el_TITAN_sysdata_mcheck *)unsigned long )mchk_header + mchk_header->sys_offset);/* * Mask of Titan interrupt sources which are reported as machine checks * * 63 - CChip Error * 62 - PChip 0 H_Error * 61 - PChip 1 H_Error * 60 - PChip 0 C_Error * 59 - PChip 1 C_Error #define TITAN_MCHECK_INTERRUPT_MASK 0 xF800000000000000UL/* * Sync the processor /* * Only handle system errors here if ((vector != SCB_Q_SYSMCHK) && (vector != SCB_Q_SYSERR)) {return ;/* * It ' s a system error , handle it here * * The PALcode has already cleared the error , so just parse it /* * Parse the logout frame without printing first . If the only error ( s ) * found are classified as " dismissable " , then just dismiss them and * don ' t print any message if (titan_process_logout_frame(mchk_header, 0 ) != char *saved_err_prefix = err_print_prefix;/* * Either a nondismissable error was detected or no * recognized error was detected in the logout frame * - - report the error in either case "%s" "*System %s Error (Vector 0x%x) reported on CPU %d:\n" , "Correctable" :"Uncorrectable" ,unsigned int )vector, (int )smp_processor_id());#ifdef CONFIG_VERBOSE_MCHECKif (alpha_verbose_mcheck)#endif /* CONFIG_VERBOSE_MCHECK */ /* * Convert any pending interrupts which report as system * machine checks to interrupts /* * Release the logout frame 0 x7);/* * Subpacket Annotations static char *el_titan_pchip0_extended_annotation[] = {"Subpacket Header" , "P0_SCTL" , "P0_SERREN" ,"P0_APCTL" , "P0_APERREN" , "P0_AGPERREN" ,"P0_ASPRST" , "P0_AWSBA0" , "P0_AWSBA1" ,"P0_AWSBA2" , "P0_AWSBA3" , "P0_AWSM0" ,"P0_AWSM1" , "P0_AWSM2" , "P0_AWSM3" ,"P0_ATBA0" , "P0_ATBA1" , "P0_ATBA2" ,"P0_ATBA3" , "P0_GPCTL" , "P0_GPERREN" ,"P0_GSPRST" , "P0_GWSBA0" , "P0_GWSBA1" ,"P0_GWSBA2" , "P0_GWSBA3" , "P0_GWSM0" ,"P0_GWSM1" , "P0_GWSM2" , "P0_GWSM3" ,"P0_GTBA0" , "P0_GTBA1" , "P0_GTBA2" ,"P0_GTBA3" , NULL static char *el_titan_pchip1_extended_annotation[] = {"Subpacket Header" , "P1_SCTL" , "P1_SERREN" ,"P1_APCTL" , "P1_APERREN" , "P1_AGPERREN" ,"P1_ASPRST" , "P1_AWSBA0" , "P1_AWSBA1" ,"P1_AWSBA2" , "P1_AWSBA3" , "P1_AWSM0" ,"P1_AWSM1" , "P1_AWSM2" , "P1_AWSM3" ,"P1_ATBA0" , "P1_ATBA1" , "P1_ATBA2" ,"P1_ATBA3" , "P1_GPCTL" , "P1_GPERREN" ,"P1_GSPRST" , "P1_GWSBA0" , "P1_GWSBA1" ,"P1_GWSBA2" , "P1_GWSBA3" , "P1_GWSM0" ,"P1_GWSM1" , "P1_GWSM2" , "P1_GWSM3" ,"P1_GTBA0" , "P1_GTBA1" , "P1_GTBA2" ,"P1_GTBA3" , NULL static char *el_titan_memory_extended_annotation[] = {"Subpacket Header" , "AAR0" , "AAR1" ,"AAR2" , "AAR3" , "P0_SCTL" ,"P0_GPCTL" , "P0_APCTL" , "P1_SCTL" ,"P1_GPCTL" , "P1_SCTL" , NULL static struct el_subpacket_annotation el_titan_annotations[] = {1 ,"Titan PChip 0 Extended Frame" ,1 ,"Titan PChip 1 Extended Frame" ,1 ,"Titan Memory Extended Frame" ,1 ,"Termination Subpacket" ,static struct el_subpacket *struct el_subpacket *header)if (header->class != EL_CLASS__REGATTA_FAMILY) {"%s ** Unexpected header CLASS %d TYPE %d, aborting\n" ,class , header->type);return NULL;switch (header->type) {case EL_TYPE__REGATTA__PROCESSOR_ERROR_FRAME:case EL_TYPE__REGATTA__SYSTEM_ERROR_FRAME:case EL_TYPE__REGATTA__ENVIRONMENTAL_FRAME:case EL_TYPE__REGATTA__PROCESSOR_DBL_ERROR_HALT:case EL_TYPE__REGATTA__SYSTEM_DBL_ERROR_HALT:"%s ** Occurred on CPU %d:\n" , int )header->by_type.regatta_frame.cpuid);struct el_common *)1 );break ;default :"%s ** REGATTA TYPE %d SUBPACKET\n" , break ;return (struct el_subpacket *)((unsigned long )header + header->length);static struct el_subpacket_handler titan_subpacket_handler = void __initvoid )for (i = 0 ; i < ARRAY_SIZE (el_titan_annotations); i++)/* * Privateer static int struct el_common *mchk_header, int print)int status = MCHK_DISPOSITION_UNKNOWN_ERROR;#ifdef CONFIG_VERBOSE_MCHECKstruct el_PRIVATEER_envdata_mcheck *emchk =struct el_PRIVATEER_envdata_mcheck *)unsigned long )mchk_header + mchk_header->sys_offset);/* TODO - categorize errors, for now, no error */ if (!print)return status;/* TODO - decode instead of just dumping... */ "%s Summary Flags: %016llx\n" " CChip DIRx: %016llx\n" " System Management IR: %016llx\n" " CPU IR: %016llx\n" " Power Supply IR: %016llx\n" " LM78 Fault Status: %016llx\n" " System Doors: %016llx\n" " Temperature Warning: %016llx\n" " Fan Control: %016llx\n" " Fatal Power Down Code: %016llx\n" ,#endif /* CONFIG_VERBOSE_MCHECK */ return status;int struct el_common *mchk_header, int print)struct el_common_EV6_mcheck *ev6mchk = struct el_common_EV6_mcheck *)mchk_header;int status = MCHK_DISPOSITION_UNKNOWN_ERROR;/* * Machine check codes #define PRIVATEER_MCHK__CORR_ECC 0 x86 /* 630 */ #define PRIVATEER_MCHK__DC_TAG_PERR 0 x9E /* 630 */ #define PRIVATEER_MCHK__PAL_BUGCHECK 0 x8E /* 670 */ #define PRIVATEER_MCHK__OS_BUGCHECK 0 x90 /* 670 */ #define PRIVATEER_MCHK__PROC_HRD_ERR 0 x98 /* 670 */ #define PRIVATEER_MCHK__ISTREAM_CMOV_PRX 0 xA0 /* 670 */ #define PRIVATEER_MCHK__ISTREAM_CMOV_FLT 0 xA2 /* 670 */ #define PRIVATEER_MCHK__SYS_HRD_ERR 0 x202 /* 660 */ #define PRIVATEER_MCHK__SYS_CORR_ERR 0 x204 /* 620 */ #define PRIVATEER_MCHK__SYS_ENVIRON 0 x206 /* 680 */ switch (ev6mchk->MCHK_Code) {/* * Vector 630 - Processor , Correctable case PRIVATEER_MCHK__CORR_ECC:case PRIVATEER_MCHK__DC_TAG_PERR:/* * Fall through to vector 670 for processing . . . /* * Vector 670 - Processor , Uncorrectable case PRIVATEER_MCHK__PAL_BUGCHECK:case PRIVATEER_MCHK__OS_BUGCHECK:case PRIVATEER_MCHK__PROC_HRD_ERR:case PRIVATEER_MCHK__ISTREAM_CMOV_PRX:case PRIVATEER_MCHK__ISTREAM_CMOV_FLT:break ;/* * Vector 620 - System , Correctable case PRIVATEER_MCHK__SYS_CORR_ERR:/* * Fall through to vector 660 for processing . . . /* * Vector 660 - System , Uncorrectable case PRIVATEER_MCHK__SYS_HRD_ERR:break ;/* * Vector 680 - System , Environmental case PRIVATEER_MCHK__SYS_ENVIRON: /* System, Environmental */ break ;/* * Unknown default :if (print) {"%s** Unknown Error, frame follows\n" , return status;void unsigned long vector, unsigned long la_ptr)struct el_common *mchk_header = (struct el_common *)la_ptr;struct el_TITAN_sysdata_mcheck *tmchk =struct el_TITAN_sysdata_mcheck *)char *saved_err_prefix = err_print_prefix;#define PRIVATEER_680_INTERRUPT_MASK (0 xE00UL)#define PRIVATEER_HOTPLUG_INTERRUPT_MASK (0 xE00UL)/* * Sync the processor . /* * Only handle system events here . if (vector != SCB_Q_SYSEVENT) return titan_machine_check(vector, la_ptr);/* * Report the event - System Events should be reported even if no * error is indicated since the event could indicate the return * to normal status . "%s*System Event (Vector 0x%x) reported on CPU %d:\n" , unsigned int )vector, (int )smp_processor_id());1 );/* * Convert any pending interrupts which report as 680 machine * checks to interrupts . /* * Dispatch the interrupt ( s ) . /* * Release the logout frame . 0 x7);
Messung V0.5 in Prozent C=93 H=89 G=90
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(vorverarbeitet am 2026-09-28)
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