Quelle xe_drm.h
Sprache: C
/* * This file is auto - generated . Modifications will be lost . * * See https : //android.googlesource.com/platform/bionic/+/master/libc/kernel/ * for more information . #ifndef _UAPI_XE_DRM_H_#define _UAPI_XE_DRM_H_#include "drm.h" #ifdef __cplusplusextern "C" {#endif #define DRM_XE_DEVICE_QUERY 0 x00#define DRM_XE_GEM_CREATE 0 x01#define DRM_XE_GEM_MMAP_OFFSET 0 x02#define DRM_XE_VM_CREATE 0 x03#define DRM_XE_VM_DESTROY 0 x04#define DRM_XE_VM_BIND 0 x05#define DRM_XE_EXEC_QUEUE_CREATE 0 x06#define DRM_XE_EXEC_QUEUE_DESTROY 0 x07#define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0 x08#define DRM_XE_EXEC 0 x09#define DRM_XE_WAIT_USER_FENCE 0 x0a#define DRM_XE_OBSERVATION 0 x0b#define DRM_XE_MADVISE 0 x0c#define DRM_XE_VM_QUERY_MEM_RANGE_ATTRS 0 x0d#define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query)#define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create)#define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset)#define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create)#define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy)#define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind)#define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create)#define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy)#define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property)#define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec)#define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence)#define DRM_IOCTL_XE_OBSERVATION DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param)#define DRM_IOCTL_XE_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_MADVISE, struct drm_xe_madvise)#define DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_QUERY_MEM_RANGE_ATTRS, struct drm_xe_vm_query_mem_range_attr)struct drm_xe_user_extension {struct drm_xe_ext_set_property {struct drm_xe_user_extension base;2 ];struct drm_xe_engine_class_instance {#define DRM_XE_ENGINE_CLASS_RENDER 0 #define DRM_XE_ENGINE_CLASS_COPY 1 #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2 #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3 #define DRM_XE_ENGINE_CLASS_COMPUTE 4 #define DRM_XE_ENGINE_CLASS_VM_BIND 5 struct drm_xe_engine {struct drm_xe_engine_class_instance instance;3 ];struct drm_xe_query_engines {struct drm_xe_engine engines[];enum drm_xe_memory_class {0 ,struct drm_xe_mem_region {6 ];struct drm_xe_query_mem_regions {struct drm_xe_mem_region mem_regions[];struct drm_xe_query_config {#define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0 #define DRM_XE_QUERY_CONFIG_FLAGS 1 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0 )#define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1 )#define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2 )#define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2 #define DRM_XE_QUERY_CONFIG_VA_BITS 3 #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4 struct drm_xe_gt {#define DRM_XE_QUERY_GT_TYPE_MAIN 0 #define DRM_XE_QUERY_GT_TYPE_MEDIA 1 3 ];7 ];struct drm_xe_query_gt_list {struct drm_xe_gt gt_list[];struct drm_xe_query_topology_mask {#define DRM_XE_TOPO_DSS_GEOMETRY 1 #define DRM_XE_TOPO_DSS_COMPUTE 2 #define DRM_XE_TOPO_L3_BANK 3 #define DRM_XE_TOPO_EU_PER_DSS 4 #define DRM_XE_TOPO_SIMD16_EU_PER_DSS 5 struct drm_xe_query_engine_cycles {struct drm_xe_engine_class_instance eci;struct drm_xe_query_uc_fw_version {#define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0 #define XE_QUERY_UC_TYPE_HUC 1 struct drm_xe_query_pxp_status {struct drm_xe_device_query {#define DRM_XE_DEVICE_QUERY_ENGINES 0 #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1 #define DRM_XE_DEVICE_QUERY_CONFIG 2 #define DRM_XE_DEVICE_QUERY_GT_LIST 3 #define DRM_XE_DEVICE_QUERY_HWCONFIG 4 #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5 #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6 #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7 #define DRM_XE_DEVICE_QUERY_OA_UNITS 8 #define DRM_XE_DEVICE_QUERY_PXP_STATUS 9 #define DRM_XE_DEVICE_QUERY_EU_STALL 10 2 ];struct drm_xe_gem_create {#define DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY 0 #define DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE 0 #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0 )#define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1 )#define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2 )#define DRM_XE_GEM_CPU_CACHING_WB 1 #define DRM_XE_GEM_CPU_CACHING_WC 2 3 ];2 ];struct drm_xe_gem_mmap_offset {#define DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER (1 << 0 )2 ];struct drm_xe_vm_create {#define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0 )#define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1 )#define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2 )2 ];struct drm_xe_vm_destroy {2 ];struct drm_xe_vm_bind_op {union {#define DRM_XE_VM_BIND_OP_MAP 0 x0#define DRM_XE_VM_BIND_OP_UNMAP 0 x1#define DRM_XE_VM_BIND_OP_MAP_USERPTR 0 x2#define DRM_XE_VM_BIND_OP_UNMAP_ALL 0 x3#define DRM_XE_VM_BIND_OP_PREFETCH 0 x4#define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0 )#define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1 )#define DRM_XE_VM_BIND_FLAG_NULL (1 << 2 )#define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3 )#define DRM_XE_VM_BIND_FLAG_CHECK_PXP (1 << 4 )#define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR (1 << 5 )#define DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET (1 << 6 )#define DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC - 1 3 ];struct drm_xe_vm_bind {union {struct drm_xe_vm_bind_op bind;2 ];struct drm_xe_exec_queue_create {#define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE 2 #define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0 )2 ];struct drm_xe_exec_queue_destroy {2 ];struct drm_xe_exec_queue_get_property {#define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0 2 ];struct drm_xe_sync {#define DRM_XE_SYNC_TYPE_SYNCOBJ 0 x0#define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0 x1#define DRM_XE_SYNC_TYPE_USER_FENCE 0 x2#define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0 )union {2 ];struct drm_xe_exec {#define DRM_XE_MAX_SYNCS 1024 3 ];2 ];struct drm_xe_wait_user_fence {#define DRM_XE_UFENCE_WAIT_OP_EQ 0 x0#define DRM_XE_UFENCE_WAIT_OP_NEQ 0 x1#define DRM_XE_UFENCE_WAIT_OP_GT 0 x2#define DRM_XE_UFENCE_WAIT_OP_GTE 0 x3#define DRM_XE_UFENCE_WAIT_OP_LT 0 x4#define DRM_XE_UFENCE_WAIT_OP_LTE 0 x5#define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0 )2 ];enum drm_xe_observation_type {enum drm_xe_observation_op {struct drm_xe_observation_param {enum drm_xe_observation_ioctls {'i' , 0 x0),'i' , 0 x1),'i' , 0 x2),'i' , 0 x3),'i' , 0 x4),enum drm_xe_oa_unit_type {struct drm_xe_oa_unit {#define DRM_XE_OA_CAPS_BASE (1 << 0 )#define DRM_XE_OA_CAPS_SYNCS (1 << 1 )#define DRM_XE_OA_CAPS_OA_BUFFER_SIZE (1 << 2 )#define DRM_XE_OA_CAPS_WAIT_NUM_REPORTS (1 << 3 )#define DRM_XE_OA_CAPS_OAM (1 << 4 )4 ];struct drm_xe_engine_class_instance eci[];struct drm_xe_query_oa_units {enum drm_xe_oa_format_type {enum drm_xe_oa_property_id {#define DRM_XE_OA_EXTENSION_SET_PROPERTY 0 1 ,#define DRM_XE_OA_FORMAT_MASK_FMT_TYPE (0 xffu << 0 )#define DRM_XE_OA_FORMAT_MASK_COUNTER_SEL (0 xffu << 8 )#define DRM_XE_OA_FORMAT_MASK_COUNTER_SIZE (0 xffu << 16 )#define DRM_XE_OA_FORMAT_MASK_BC_REPORT (0 xffu << 24 )struct drm_xe_oa_config {char uuid[36 ];struct drm_xe_oa_stream_status {#define DRM_XE_OASTATUS_MMIO_TRG_Q_FULL (1 << 3 )#define DRM_XE_OASTATUS_COUNTER_OVERFLOW (1 << 2 )#define DRM_XE_OASTATUS_BUFFER_OVERFLOW (1 << 1 )#define DRM_XE_OASTATUS_REPORT_LOST (1 << 0 )3 ];struct drm_xe_oa_stream_info {3 ];enum drm_xe_pxp_session_type {0 ,1 ,#define DRM_XE_PXP_HWDRM_DEFAULT_SESSION 0 xfenum drm_xe_eu_stall_property_id {#define DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY 0 1 ,struct drm_xe_query_eu_stall {#define DRM_XE_EU_STALL_CAPS_BASE (1 << 0 )5 ];struct drm_xe_madvise {#define DRM_XE_MEM_RANGE_ATTR_PREFERRED_LOC 0 #define DRM_XE_MEM_RANGE_ATTR_ATOMIC 1 #define DRM_XE_MEM_RANGE_ATTR_PAT 2 union {struct {#define DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE 0 #define DRM_XE_PREFERRED_LOC_DEFAULT_SYSTEM - 1 #define DRM_XE_MIGRATE_ALL_PAGES 0 #define DRM_XE_MIGRATE_ONLY_SYSTEM_PAGES 1 struct {#define DRM_XE_ATOMIC_UNDEFINED 0 #define DRM_XE_ATOMIC_DEVICE 1 #define DRM_XE_ATOMIC_GLOBAL 2 #define DRM_XE_ATOMIC_CPU 3 struct {2 ];struct drm_xe_mem_range_attr {struct {struct {struct {2 ];struct drm_xe_vm_query_mem_range_attr {2 ];#ifdef __cplusplus#endif #endif
Messung V0.5 in Prozent C=84 H=98 G=91
¤ Dauer der Verarbeitung: 0.11 Sekunden
(vorverarbeitet am 2026-06-28)
¤ *© Formatika GbR, Deutschland
2026-07-11
